JP2001168188A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable to form a fine wiring groove and a connecting hole, by highly accurately machining a wiring groove and a connecting hole of dual damascene structure without machining at the connecting hole with a high aspect ratio and at the position having a high step difference. SOLUTION: A silicon oxide first interlayer insulating film 12, an etching stop layer 13, a silicon oxide second interlayer insulating film 14, and a mask layer 15 are formed in this order. Thereafter, a wiring groove pattern 16 is opened in the mask layer 15, and a via-hole pattern 17 is opened in the second interlayer insulating film 14 and the etching stopper 13 so as to at least extend to the wiring groove 16. A wiring layer 18 is formed in the second interlayer insulating film 14 by means of the mask layer 15 as a mask and, at the same time, a via-hole 19 is formed on the first interlayer insulating film 12 by means of the etching stop layer 13 as an etching mask.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a wiring structure is formed on a silicon oxide-based insulating film on an interlayer insulating film by a dual damascene method.

[0002]

2. Description of the Related Art A process technology for dual damascene wiring using copper wiring has been developed to improve the operating speed of a semiconductor device and reduce power consumption. In the dual damascene wiring, a wiring groove and a connection hole (via hole) are formed in an interlayer insulating film, and a conductive material is buried in the wiring groove and the via hole at the same time. Therefore, a conductive material is buried separately in the via hole and the wiring groove. There is an advantage that the manufacturing cost can be reduced as compared with the single damascene method. To form a wiring groove and a via hole in an interlayer insulating film, two patterning steps are usually required. As the method, several types of forming methods have been proposed.

[0003] First, Conventional Example 1 will be described with reference to a manufacturing process sectional view shown in FIG.

As shown in FIG. 3A, after a thin passivation film 111 made of a material that does not diffuse a wiring material is formed of a silicon nitride film or a silicon carbide film on a substrate 110 on which transistors, wirings and the like are formed. First interlayer insulating film 112 in which a via hole is formed is formed of a 500-nm-thick silicon oxide film.

[0005] Next, as shown in FIG. 3 (2), an etching stopper layer 11 is formed on the first interlayer insulating film 112.
3 is formed of a silicon nitride film having a thickness of 100 nm. Next, a resist mask (not shown) used for forming a via hole pattern in the etching stopper layer 113
Is formed, and an opening 121 is formed in the etching stopper layer 113 by etching using the etching mask as an etching mask. After that, the resist mask is removed.

Next, as shown in FIG. 3C, a second interlayer insulating film 114 on which a wiring is formed on the etching stopper layer 113 including the inside of the opening 121 is formed to a thickness of 400 n.
It is formed of a silicon oxide film having a thickness of m. Next, a resist mask 131 used for forming a wiring groove is formed over the second interlayer insulating film 114. This resist mask 1
An opening 132 for forming a wiring groove is formed in 31.

Subsequently, as shown in FIG. 3D, the second interlayer insulating film 114 is etched by using the resist mask 131 to form a wiring groove 115 and the etching stopper layer 113 is etched by an etching mask. Then, the first interlayer insulating film 112 is etched to form a via hole 116. This etching is performed under conditions having characteristics highly selective with respect to silicon nitride. After that, the resist mask 131 is removed.

Next, as shown in FIG. 3 (5), using the first and second interlayer insulating films 112 and 114 as a mask,
The passivation film 111 exposed at the bottom of the via hole 116 is etched. At this time, the etching stopper layer 113 formed of the same kind of material is also etched using the second interlayer insulating film 114 as an etching mask.

Next, a second conventional example will be described with reference to a sectional view of a manufacturing process shown in FIG.

As shown in FIG. 4A, after a thin passivation film 111 made of a material that does not diffuse a wiring material is formed of a silicon nitride film or a silicon carbide film on a substrate 110 on which transistors, wirings and the like are formed. A first interlayer insulating film 112 in which a via hole is formed is formed of a 500-nm-thick silicon oxide film, an etching stopper layer 113 is formed of a 50-nm-thick silicon nitride film, and a second in which a wiring is formed. The interlayer insulating film 114 is formed with a 450 nm thick silicon oxide film.

Next, as shown in FIG.
A resist mask (not shown) used for forming a via hole is formed in the interlayer insulating film 114, the etching stopper layer 113, and the first interlayer insulating film 112. continue,
The second interlayer insulating film 114, the etching stopper layer 113, and the first interlayer insulating film 112 are etched by etching using the resist mask as an etching mask to form a via hole. After that, the resist mask is removed.

Next, as shown in FIG.
A resist mask 131 used to form a wiring groove in the interlayer insulating film 114 is formed. At that time, via hole 1
A resist mask 131 is also formed inside 16. Thereafter, an opening 132 for forming a wiring groove in the resist mask 131 is formed using a normal lithography technique.
To form

As shown in FIG. 4 (4), the second interlayer insulating film 114 is etched using the resist mask 131 (see FIG. 4 (3)) to form a wiring groove 115. After that, the resist mask 131 is removed. Thereby, the via hole 116 is opened again.

Next, as shown in FIG.
Using the first interlayer insulating films 114 and 112 as an etching mask, the passivation film 111 exposed at the bottom of the via hole 116 is etched. At this time, the etching stopper layer 113 formed of the same kind of material, silicon nitride, is also removed at the same time using the second interlayer insulating film 114 as an etching mask.

Next, a third conventional example will be described with reference to a sectional view of a manufacturing process shown in FIG.

As shown in FIG. 5A, after a thin passivation film 111 made of a material that does not diffuse a wiring material is formed of a silicon nitride film or a silicon carbide film on a substrate 110 on which transistors, wirings and the like are formed. The interlayer insulating film 112 where via holes and wiring grooves are formed is 1.0
It is formed of a silicon oxide film having a thickness of 0 μm.

Next, as shown in FIG. 5B, a resist mask (not shown) used for forming a via hole pattern is formed, and the interlayer insulating film 112 is etched by using the resist mask as an etching mask. Thus, a via hole 116 is formed. After that, the resist mask is removed.

Subsequently, as shown in FIG. 5C, a resist mask 131 used for forming a wiring groove in the interlayer insulating film 112 is formed. At this time, a resist mask 131 is also formed inside the via hole 116. Thereafter, an opening 132 for forming a wiring groove is formed in the resist mask 131 by using a normal lithography technique.

Subsequently, as shown in FIG. 5D, the interlayer insulating film 112 is partially etched by using the resist mask 131 (see FIG. 5C). A wiring groove 115 having a depth of 500 nm is formed. After that, the resist mask 131 is removed. Thereby, the via hole 116 is opened again.

Thereafter, as shown in FIG. 5 (5), the via hole 1 is formed using the interlayer insulating film 112 as an etching mask.
The passivation film 111 exposed at the bottom of 16 is etched.

[0021]

However, in the first conventional example described above, after the wiring groove is formed, a via hole is formed and further over-etching is performed, so that the etching is applied to the etching stopper layer at the bottom of the wiring groove. The amount of over-etching increases. Therefore, it is difficult to make the etching stopper layer sufficiently large in etching selectivity with respect to the over-etching amount. For example,
500 converted to the thickness of the etching stopper layer at the bottom of the wiring groove
The thickness of the etching stopper layer is 100 nm, while it is necessary to add over-etching of
Moreover, the selectivity of the etching stopper layer needs to be 5 or more, and further needs to be 10 or more in consideration of the process margin. Therefore, when etching the via hole, it penetrates through the etching stopper layer, and it is difficult to accurately form a wiring groove or a via hole. Therefore, if the etching stopper layer is formed thick to prevent the etching stopper layer from penetrating, the signal transmission delay increases due to the high dielectric constant of the silicon nitride film, and the operation speed of the semiconductor device decreases.

In the second conventional example described above, in the step of forming a via hole in the second interlayer insulating film, the etching stopper layer and the first interlayer insulating film, the aspect ratio of the via hole becomes extremely high, so that etching is performed. Becomes difficult. In the step of forming a resist mask for forming a wiring groove, since a deep via hole is formed on a surface on which the resist mask is formed, an antireflection material or a resist material is buried in the via hole. Is difficult to form. For this reason, processing defects occur. Furthermore, even if the resist mask is formed normally, it is difficult to use a high NA exposure apparatus because lithography must be performed on the uneven surface, so it is difficult to form a fine wiring groove pattern. Becomes

In the third conventional example described above, the second
As in the conventional example, in the step of forming a via hole in the interlayer insulating film, the via hole has an extremely high aspect ratio, so that etching becomes difficult. In the step of forming a resist mask for forming a wiring groove, since a deep via hole is formed on a surface on which the resist mask is formed, an antireflection material or a resist material is buried in the via hole. Is difficult to form. For this reason, processing defects occur. Furthermore, even if the resist mask is formed normally, it is difficult to use a high NA exposure apparatus because lithography must be performed on the uneven surface, so it is difficult to form a fine wiring groove pattern. Becomes

[0024]

SUMMARY OF THE INVENTION The present invention is a method for manufacturing a semiconductor device which has been made to solve the above-mentioned problems.

According to the first method of manufacturing a semiconductor device, a first interlayer insulating film made of a first silicon oxide-based material is formed on a substrate and has an etching selectivity with respect to the first silicon oxide-based material. An etching stopper layer made of a material, a second interlayer insulating film made of a second silicon oxide-based material, and a mask layer made of a material having an etching selectivity with respect to the second silicon oxide-based material are sequentially formed. Forming a wiring groove pattern for forming a wiring groove in the mask layer; and opening a connection hole in the second interlayer insulating film and the etching stopper layer so as to cover at least the wiring groove pattern. Forming a wiring groove in the second interlayer insulating film using the mask layer as an etching mask, and etching the etching stopper layer. A method for manufacturing a semiconductor device comprising the step of forming a connection hole in the first interlayer insulating film by using the.

In the first method of manufacturing a semiconductor device, in the step of forming the wiring groove, the connection hole is formed simultaneously with the formation of the wiring groove. Therefore, the amount of overetching applied to the etching stopper layer at the bottom of the wiring groove is reduced. I need less. Therefore, if the etching stopper layer is formed of a film having an etching selectivity of about 5 with respect to the over-etching amount, a sufficient etching selectivity can be obtained with a thin film thickness of about 100 nm.

In the step of forming a connection hole,
Since a connection hole having a high aspect ratio is not formed, etching for forming the connection hole becomes easy. In the step of forming a resist mask for forming a wiring groove, the resist mask is formed on a mask layer having a small step, so that the resist mask is formed with high precision and a high NA exposure apparatus is used. Therefore, it is easy to form a fine wiring groove pattern.

In the second method of manufacturing a semiconductor device, an interlayer insulating film made of a silicon oxide material and a mask layer made of a material having an etching selectivity with respect to the silicon oxide material are sequentially formed on a substrate. Performing a step of opening a wiring groove pattern for forming a wiring groove in the mask layer; forming a connection hole pattern at least halfway through the interlayer insulating film so as to cover the wiring groove pattern; Forming a wiring groove on the interlayer insulating film using a mask layer as an etching mask and extending the connection hole pattern to form a connection hole penetrating the interlayer insulating film. It is a manufacturing method.

In the second method for manufacturing a semiconductor device, a connection hole pattern which is to be an upper portion of the connection hole is formed in advance in the interlayer insulating film without using the etching stopper layer, and then the wiring groove is formed and the connection is formed simultaneously. Since the connection pattern is completed by extending the hole pattern, the bottom of the connection hole is over-etched when the wiring groove is formed. Therefore, the penetration of the wiring groove does not occur.

In the step of forming the connection hole,
Since a connection hole having a high aspect ratio is not formed, etching for forming the connection hole becomes easy. In the step of forming a resist mask for forming a wiring groove, the resist mask is formed on a mask layer having a small step, so that the resist mask is formed with high precision and a high NA exposure apparatus is used. Therefore, it is easy to form a fine wiring groove pattern.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of an embodiment according to a first manufacturing method of the present invention will be described with reference to a manufacturing process sectional view of FIG.

As shown in FIG. 1A, as an example,
A substrate 10 is formed by forming a semiconductor element such as a transistor on a semiconductor substrate and further forming a wiring, an insulating film and the like. A passivation film 11 is formed on the uppermost layer of the substrate 10.
However, for example, a silicon nitride film or a silicon carbide film, which is a material that does not diffuse the wiring material, is formed to a thickness of about 50 nm.

Thereafter, the first interlayer insulating film 12 in which a connection hole (hereinafter, referred to as a via hole) is formed is used as a first silicon oxide-based material, for example, a silicon oxide (SiO ₂ ) film having a thickness of 500 nm. And an etching stopper layer 13 formed of, for example, a silicon nitride film to a thickness of 50 nm, and a second interlayer insulating film 14 on which wiring is formed.
Is formed as a _second silicon oxide-based material with a thickness of, for example, 450 nm using a silicon oxide (SiO ₂ ) film, and the mask layer 15 is formed with a thickness of, for example, 100 nm with a silicon nitride film.

Next, a normal resist coating process and a lithography process are performed to form a resist mask 31 used for forming a wiring groove on the mask layer 15. An opening 32 for forming a wiring groove is formed in the resist mask 31.

Subsequently, as shown in FIG. 1B, the mask layer 15 is etched using the resist mask 31 [see FIG. 1A] to open the wiring groove pattern 16. In this etching, an ordinary parallel plate type plasma etching apparatus is used, and trifluoromethane (CHF ₃ ), argon (Ar), and oxygen (O ₂ ) are used as an etching gas.
And were used. The substrate temperature was 0 ° C. After that, the resist mask 31 (see FIG. 1A) is removed.

Next, as shown in FIG.
A normal resist coating step and a lithography step are performed to form a resist mask 33 used to form a via hole on the mask layer 15 and the wiring groove pattern 16. An opening 34 for forming a via hole is formed in the resist mask 33 so as to cover at least the wiring groove pattern 16.

Next, as shown in FIG. 1D, the second interlayer insulating film 14 is etched using the resist mask 33 [see FIG. 17 (described as a via hole pattern) is formed. In this etching, an ordinary parallel plate type plasma etching apparatus was used, and octafluorocyclobutane (C ₄ F ₈ ), argon (Ar), and oxygen (O ₂ ) were used as an etching gas. The substrate temperature was 0 ° C.

Subsequently, the above etching is further advanced,
The via hole pattern 17 is extended by etching the etching stopper layer 13. In this etching, an ordinary parallel plate type plasma etching apparatus was used, and trifluoromethane (CHF ₃ ), argon (Ar), and oxygen (O ₂ ) were used as an etching gas. The substrate temperature is 0
Set to ° C. Thereafter, a resist mask 33 [see FIG.
(3)) is removed.

Next, as shown in FIG. 1 (5), the second interlayer insulating film 14 made of silicon oxide is etched using the mask layer 15 as an etching mask to form a wiring groove 18.
To form Further, using the etching stopper layer 13 as an etching mask, the first interlayer insulating film 12 made of silicon oxide is etched to form a via hole 19.
The etching conditions were the same as the etching conditions for silicon oxide described with reference to FIG.

Thereafter, as shown in FIG. 1 (6), the passivation film 1 exposed at the bottom of the via hole 19 is formed.
1 is etched. At this time, the mask layer 15 (see (4) in FIG. 1) and the etching stopper layer 13 made of the same material are also etched and removed. In this etching, an ordinary high-density plasma etching apparatus was used, and sulfur hexafluoride (SF ₆ ) was used as an etching gas so that the silicon nitride film was selectively anisotropically etched. The substrate temperature is 0
° C. As a result, a wiring groove 18 is formed in the second interlayer insulating film 14 and the etching stopper layer 13, and a via hole 19 is formed in the first interlayer insulating film 12 and the passivation film 11 continuously at the bottom of the wiring groove 18. You.

Although a silicon oxide (SiO ₂ ) film is used for the first and second interlayer insulating films 12 and 14, for example, silicon oxyfluoride (SiOF) may be used.

Although the mask layer 15 is formed of a silicon nitride film, it may be formed of a high melting point metal such as a titanium nitride film or a high melting point metal compound film. That is,
Any material can be used as long as it has etching selectivity with respect to a silicon oxide-based material, but a light-transmitting film that can be optically aligned is preferable.

In the first method for manufacturing a semiconductor device, in the step of forming the wiring groove 18, the via hole 19 (connection hole) is formed simultaneously with the formation of the wiring groove 18, so that the etching stopper at the bottom of the wiring groove 18 is formed. The amount of over-etching applied to the layer 13 can be small. Therefore, the etching stopper layer 1 is
For example, if the film 3 is formed of a film having an etching selectivity of about 5, a sufficient etching selectivity can be obtained with a thin film thickness of about 100 nm.

In the step of forming the via hole 19, since the via hole 19 having a high aspect ratio is not formed, the etching for forming the via hole 19 becomes easy. Further, in the step of forming the resist mask 33 for forming the wiring groove 18, the resist mask 33 is formed on the mask layer 15 having a small step, so that the resist mask 33 is formed with high precision and further has a high NA. Therefore, the fine wiring groove pattern 16 can be easily formed.

In the first manufacturing method, since the etching stopper layer 13 is formed of a material having etching selectivity with respect to the silicon oxide-based material, the wiring trench 1 is formed.
When 8 is formed, the etching does not penetrate the etching stopper layer 13. Further, there is no need to form a via hole having a high aspect ratio, and the lithography step can be performed on a surface having a small step.

Since the opening 34 for forming the via hole pattern is formed in the resist mask 33 after the formation of the wiring groove pattern 16 in the mask layer 15, the opening 34 protrudes from the wiring groove pattern 16. However, the via hole pattern 17 does not protrude from the wiring groove pattern 16 because the mask layer 15 serves as an etching mask.
It does not protrude and is not formed.

Next, an example of an embodiment according to the second manufacturing method of the present invention will be described with reference to a manufacturing process sectional view of FIG. In FIG. 2, the same components as those described with reference to FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 2A, as an example,
A substrate 10 is formed by forming a semiconductor element such as a transistor on a semiconductor substrate and further forming a wiring, an insulating film and the like. A passivation film 11 is formed on the uppermost layer of the substrate 10.
However, for example, a silicon nitride film or a silicon carbide film, which is a material that does not diffuse the wiring material, is formed to a thickness of about 50 nm. After that, the interlayer insulating film 41 in which a connection hole (hereinafter, referred to as a via hole) is formed is used as a silicon oxide-based material, for example, silicon oxide (SiO 2).
₂ ) A film is formed with a thickness of 1000 nm, and the mask layer 15 is formed of, for example, a silicon nitride film with a thickness of 100 nm.

Next, a normal resist coating step and a lithography step are performed to form a resist mask 31 used for forming a wiring groove on the mask layer 15. An opening 32 for forming a wiring groove is formed in the resist mask 31.

Subsequently, as shown in FIG. 2B, the mask layer 15 is etched using the resist mask 31 (see FIG. 2A) to open the wiring groove pattern 16. In this etching, an ordinary parallel plate type plasma etching apparatus is used, and trifluoromethane (CHF ₃ ), argon (Ar), and oxygen (O ₂ ) are used as an etching gas.
And were used. The substrate temperature was 0 ° C. After that, the resist mask 31 (see FIG. 2A) is removed.

Next, as shown in FIG.
A normal resist coating step and a lithography step are performed to form a resist mask 33 used to form a via hole on the mask layer 15 and the wiring groove pattern 16. In the resist mask 33, an opening 34 for forming a via hole is formed so as to cover at least the wiring groove passivation 16.

Then, as shown in FIG. 2 (4), the interlayer insulating film 41 is partially applied, for example, to a depth of 750 nm using the resist mask 33 (see FIG. 2 (3)) as an etching mask. By etching, a connection hole pattern (hereinafter, referred to as a via hole pattern) 17 is formed. In this etching, the etching depth was controlled by the etching time. An ordinary parallel plate type plasma etching apparatus was used, and octafluorocyclobutane (C ₄ F ₈ ), argon (Ar), and oxygen (O ₂ ) were used as an etching gas. The substrate temperature was 0 ° C. After that, the resist mask 33 is removed.

Subsequently, as shown in (5) of FIG. 2, using the mask layer 15 as an etching mask, the wiring groove 18 is formed by etching the interlayer insulating film 41 halfway, for example, to a depth of 500 nm. I do. At the same time, a via hole 19 is formed by etching so as to extend the via hole pattern 17 (see (4) in FIG. 2). In this etching, the same conditions as the etching conditions of silicon oxide described in FIG. 2D were used.

Thereafter, as shown in FIG. 1 (6), the passivation film 1 exposed at the bottom of the via hole 19 is formed.
1 is etched. At this time, the mask layer 15 (see (5) in FIG. 2) formed of the same kind of material is also removed by etching. In this etching, an ordinary high-density plasma etching apparatus was used, and sulfur hexafluoride (SF ₆ ) was used as an etching gas so that the silicon nitride film was selectively anisotropically etched. The substrate temperature was 0 ° C. As a result, the wiring groove 18 is formed above the interlayer insulating film 41, and the via hole 19 is formed below the interlayer insulating film 41 and in the passivation film 11 continuously at the bottom of the wiring groove 18.

Although the silicon oxide (SiO ₂ ) film is used for the interlayer insulating film 41, for example, silicon oxyfluoride (SiOF) can be used.

The mask layer 15 is formed of a silicon nitride film, but may be formed of a high melting point metal such as a titanium nitride film or a high melting point metal compound film. That is,
Any material can be used as long as it has etching selectivity with respect to a silicon oxide-based material, but a light-transmitting film that can be optically aligned is preferable.

In the second method for manufacturing a semiconductor device, the upper portion of the via hole 19 is formed by forming a via hole pattern 17 in the interlayer insulating film 13 in advance without using an etching stopper layer. Is formed at the same time as the via hole pattern is extended to complete the via hole 19, so that the bottom of the via hole 19 is over-etched when the wiring groove 18 is formed. Therefore, the wiring groove 18 does not penetrate.

In the step of forming the via hole 19, since the via hole 19 having a high aspect ratio is not formed, the etching for forming the via hole 19 becomes easy. Further, in the step of forming the resist mask 33 for forming the wiring groove 18, the resist mask 33 is formed on the mask layer 15 having a small step, so that the resist mask 33 is formed with high precision and further has a high NA. Therefore, the fine wiring groove pattern 16 can be easily formed.

In the second manufacturing method, since the etching stopper layer made of silicon nitride used in the first manufacturing method is not used, the interlayer insulating film has a lower dielectric constant than the semiconductor device formed by the first manufacturing method. Rate. Therefore, a wiring with a high signal transmission speed is formed. In addition, since it is not necessary to form a hole having a high aspect ratio before the lithography step, the lithography step can be performed on a substantially flat surface.

Since the opening 34 for forming the via hole pattern is formed in the resist mask 33 after the formation of the wiring groove pattern 16 in the mask layer 15, the opening 34 protrudes from the wiring groove pattern 16. However, the via hole pattern 17 does not protrude from the wiring groove pattern 16 because the mask layer 15 serves as an etching mask.
It does not protrude and is not formed.

[0061]

As described above, according to the first manufacturing method of the present invention, since the connection hole is formed simultaneously with the formation of the wiring groove, the amount of overetching applied to the etching stopper layer at the bottom of the wiring groove can be reduced. Can be reduced. Therefore, since the wiring groove does not penetrate the etching stopper layer during the etching for forming the connection hole, the wiring groove and the connection hole can be accurately manufactured. Further, since the etching stopper layer can be formed thin, a signal transmission delay does not increase even if a material having a high dielectric constant having etching selectivity is used.
There is no significant effect on the operation speed of the semiconductor device. Further, since a connection hole having a high aspect ratio is not formed, etching for forming the connection hole becomes easy.
In addition, since a resist mask for forming a wiring groove is formed on a mask layer having a small step, the resist mask can be formed with high precision, and a high NA exposure apparatus can be used. A fine wiring groove pattern can be easily formed. Therefore, processing defects can be prevented, and the yield can be improved.

According to the second manufacturing method of the present invention, the upper portion of the connection hole is previously formed in the interlayer insulating film without using the etching stopper layer, and then the wiring groove is formed and the connection hole is completed at the same time. ing. Moreover, since the bottom of the connection hole is over-etched when the wiring groove is formed, the connection hole can be formed without causing the wiring groove to penetrate. Also, since the connection holes are formed in two stages,
Since there is no need to perform etching with a high aspect ratio, highly accurate etching can be performed. Further, since a resist mask for forming a wiring groove can be formed on a mask layer having a small step, the resist mask can be formed with high precision, and a high NA exposure apparatus can be used. Therefore, a fine wiring groove pattern can be easily formed. Therefore,
Processing defects can be prevented, and the yield can be improved.

[Brief description of the drawings]

FIG. 1 is a manufacturing process sectional view showing an embodiment according to a first manufacturing method of the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing process showing an embodiment according to a second manufacturing method of the present invention.

FIG. 3 is a cross-sectional view of a manufacturing process showing a first conventional example.

FIG. 4 is a sectional view of a manufacturing process showing a second conventional example.

FIG. 5 is a sectional view of a manufacturing process showing a third conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... board | substrate, 12 ... 1st interlayer insulation film, 13 ... etching stopper layer, 14 ... 2nd interlayer insulation film, 15 ... mask layer, 17 ... via hole pattern, 18 ... wiring groove, 19 ...
Beer hall

Claims (2)

[Claims] A first interlayer insulating film made of a first silicon oxide-based material, an etching stopper layer made of a material having an etching selectivity with respect to the first silicon oxide-based material, and Forming a second interlayer insulating film made of a second silicon oxide-based material and a mask layer made of a material having an etching selectivity with respect to the second silicon oxide-based material, Opening a wiring groove pattern for forming a wiring groove; and forming the second wiring groove pattern so as to cover at least the wiring groove pattern.
Forming a connection hole in the interlayer insulating film and the etching stopper layer, and forming a wiring groove in the second interlayer insulating film using the mask layer as an etching mask and using the etching stopper layer as an etching mask. Forming a connection hole in the first interlayer insulating film. A step of sequentially forming, on a substrate, an interlayer insulating film made of a silicon oxide-based material and a mask layer made of a material having an etching selectivity with respect to the silicon oxide-based material; A step of opening a wiring groove pattern for forming a wiring groove; a step of forming a connection hole pattern at least halfway through the interlayer insulating film so as to cover the wiring groove pattern; and using the mask layer as an etching mask. Forming a wiring groove above the interlayer insulating film and extending the connection hole pattern to form a connection hole penetrating the interlayer insulating film.