KR100340072B1 - Method for fabricating metal interconnection of semiconductor device - Google Patents

Method for fabricating metal interconnection of semiconductor device Download PDF

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Publication number
KR100340072B1
KR100340072B1 KR1019950006710A KR19950006710A KR100340072B1 KR 100340072 B1 KR100340072 B1 KR 100340072B1 KR 1019950006710 A KR1019950006710 A KR 1019950006710A KR 19950006710 A KR19950006710 A KR 19950006710A KR 100340072 B1 KR100340072 B1 KR 100340072B1
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insulation layer
insulating film
film
forming
insulating
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KR1019950006710A
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Korean (ko)
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KR960035972A (en
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박상훈
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for fabricating a metal interconnection of a semiconductor device is provided to improve step coverage of the metal interconnection by forming a spacer made of a dual cap insulation layer. CONSTITUTION: The first insulation layer and the first conductive layer are sequentially formed on a substrate(21) having a topology composed of a predetermined pattern. The second insulation layer and the third insulation layer are sequentially formed on the first conductive layer. The third insulation layer, the second insulation layer and the first conductive layer are sequentially etched by using a mask for patterning the first conductive layer. The fourth insulation layer is formed on the resultant structure. The fourth insulation layer is anisotropically blanket-etched until the third insulation layer is eliminated so that the fourth insulation layer spacer is formed on the sidewall of the patterned second insulation layer and the first conductive layer pattern(23) while a predetermined thickness of the first insulation layer is etched. The fifth insulation layer for planarization is formed on the resultant structure. The planarization insulation layer and the first insulation layer in a metal contact hole formation region are etched. A metal layer is formed.

Description

반도체 소자의 금속배선 형성방법Metal wiring formation method of semiconductor device

본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로써, 특히 금속배선의 스텝커버리지를 개선하기 위한 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring of a semiconductor device, and more particularly, to a method for forming metal wiring for improving step coverage of metal wiring.

제 1 도는 종래기술에 따라 금속배선이 형성된 상태의 단면도로서, 그 방법을 살펴보면 다음과 같다.1 is a cross-sectional view of a metal wiring in a state according to the prior art, looking at the method as follows.

실리콘 기판(11)상에 필드산화막(12), 제 1전도막 패턴(13), 제1절연용 산화막(14), 제2전도막 패턴(15), 제2절연용 BPSG막(16)을 각각 형성한 후에 예정된 부위의 상기 제1절연용 산화막(14), 제2 절연용 BPSG막(16)을 식각하여 금속콘택홀을 형성하고, 금속층을 증착한 후 패터닝하여 금속배선(17)을 형성한다.The field oxide film 12, the first conductive film pattern 13, the first insulating oxide film 14, the second conductive film pattern 15, and the second insulating BPSG film 16 are formed on the silicon substrate 11. After each formation, the first insulating oxide layer 14 and the second insulating BPSG layer 16 are etched to form a metal contact hole, and a metal layer is deposited and then patterned to form a metal wiring 17. do.

그러나, 소자가 점차 고집적화 되어가면서 콘택홀의 폭(a)과 높이(b)의 비인 에스펙트 비(aspect ratio)가 1.5 이상이 되어 콘택홀 내부에 형성된 금속배선이 상대적으로 얇아지므로 금속배선의 층덮힘(step coverage)이 나빠지므로써 소자의 신뢰성을 저하시키는 문제점이 발생하게 된다.However, as the device becomes increasingly integrated, the aspect ratio, which is the ratio of the width (a) to the height (b) of the contact hole, is 1.5 or more, so that the metal wiring formed in the contact hole becomes relatively thin, thus covering the layer of the metal wiring. As step coverage becomes worse, a problem of deteriorating device reliability occurs.

상기 종래기술의 문제점을 해결하기 위하여 안출된 본 발명은 금속배선의 층덮힘을 개선하는 반도체 소자의 금속배선 형성방법을 제공함을 그 목적으로 한다.The present invention has been made to solve the problems of the prior art is to provide a method for forming a metal wiring of the semiconductor device to improve the layer covering of the metal wiring.

상기 목적은 달성하기 위하여 본 발명은 소정의 패턴이 형성되어 토포로지를 갖는 기판 상에 제1절연막 및 제1전도막을 차례로 형성하는 단계; 상기 제1전도막상에 제2절연막 및 제3절연막을 차례로 형성하는 단계; 상기 제1전도막을 패터닝하기 위한 마스크를 사용하여 상기 제3절연막, 제2절연막, 제1전도막을 차례로 식각하는 단계, 전체구조 상부에 제4절연막을 형성하는 단계; 상기 제3절연막이 제거될때까지 상기 제4절연막을 비등방성 전면식각하여 패터닝된 상기 제2절연막 및 제1전도막 패턴 측벽에 제4절연막 스페이서를 형성하는 동시에 상기 제1절연막의 전체두께중 일정두께를 식각하는 단계; 전체구조 상부에 평탄화 제5절연막을 형성하는 단계; 예정된 금속 콘택홀 부위의 상기 평탄화 절연막 및 제1절연막을 식각하는 단계; 및 금속막을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention comprises the steps of forming a first insulating film and a first conductive film in sequence on a substrate having a predetermined pattern is formed; Sequentially forming a second insulating film and a third insulating film on the first conductive film; Etching the third insulating film, the second insulating film, and the first conductive film in order by using a mask for patterning the first conductive film, and forming a fourth insulating film on the entire structure; The fourth insulating film is anisotropically etched until the third insulating film is removed, thereby forming a fourth insulating film spacer on the sidewalls of the patterned second insulating film and the first conductive film pattern and at a predetermined thickness of the first insulating film. Etching; Forming a planarization fifth insulating layer on the entire structure; Etching the planarization insulating layer and the first insulating layer in a predetermined metal contact hole; And forming a metal film.

이하, 첨부된 도면 제 2A 도 내지 제 2E 도를 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the attached drawings 2A to 2E.

먼저, 제 2A 도는 필드산화막(22) 및 제1전도막 패턴(23)의 형성으로 토포로지를 갖는 반도체 기판(21) 전체구조 상부에 제1절연용 산화막(24) 및 제2전도막(25)을 각각 소정두께로 형성한 상태의 단면도이다.First, the first insulating oxide film 24 and the second conductive film 25 are formed over the entire structure of the semiconductor substrate 21 having the topology by forming the field oxide film 22 and the first conductive film pattern 23. ) Is a cross-sectional view of a state in which each is formed to a predetermined thickness.

이어서, 제 2B 도에 도시된 바와같이 전체 구조의 상부에 약 500 ∼ 1000Å의 제2절연용 산화막(26)및 약 100∼500Å의 질화막(27)을 각각 차례로 형성하고, 제 2C 도와 상기 제2전도막을 패터닝하기 위한 마스크를 사용하여 질화막(27), 제2절연용 산화막(26) 및 제2전도막(25)을 차례로 식각하여 제2전도막 패턴(25')을 형성하고 약 1000∼2000Å의 제3절연용 산화막(28)을 증착한다.Subsequently, as shown in FIG. 2B, a second insulating oxide film 26 of about 500 to 1000 mW and a nitride film 27 of about 100 to 500 mW are sequentially formed on the top of the entire structure, respectively. Using the mask for patterning the conductive film, the nitride film 27, the second insulating oxide film 26 and the second conductive film 25 were sequentially etched to form the second conductive film pattern 25 '. A third insulating oxide film 28 is deposited.

계속해서, 제 2D 도와 같이 CF4, CHF3등의 가스를 사용한 비등방성 식각법으로 제3절연용 산화막(28)을 식각하여 제2전도막 패턴(25')의 측벽에 산화막 스페이서(28')를 형성하는데, 이때, 질화막(27)과 산화막(28,24)간의 식각속도 차이를 약 1:3 ∼ 1:4 정도로 유지하면서 과도식각을 진행하여, 제3절연용 산화막(28) 하부의 질화막(27)은 완전히 제거되고 제1절연용 산화막(24)은 전체두께중 일정두께가 식각되도록 함으로써, 제1절연용 산화막(24)의 두께를 얇게한다.Subsequently, the third insulating oxide film 28 is etched by an anisotropic etching method using a gas such as CF 4 , CHF 3, or the like as the 2D diagram to form oxide spacers 28 ′ on the sidewalls of the second conductive film pattern 25 ′. In this case, the transient etching is performed while maintaining the difference in etching speed between the nitride film 27 and the oxide films 28 and 24 at about 1: 3 to 1: 4, and thus, the lower portion of the third insulating oxide film 28 is formed. The nitride film 27 is completely removed and the first insulating oxide film 24 is etched by a certain thickness of the entire thickness, thereby reducing the thickness of the first insulating oxide film 24.

이어서, 제 2E 도는 전체구조의 상부에 평탄화용 산화막(29)을 형성하고, 예정된 금속콘택 부위의 평탄화용 산화막(29)과 제1절연용 산화막(24)을 식각하여 금속콘택홀을 형성한 후 금속배선(200)을 형성한다. 이때, 콘택 홀의 깊이는 감소되어 결국 에스펙트 비가 개선됨으로써, 금속배선(200)의 층덮힘이 개선된다.Subsequently, the planarization oxide film 29 is formed on the entire structure of FIG. 2E, the planarization oxide film 29 and the first insulating oxide film 24 are etched to form metal contact holes. The metal wire 200 is formed. In this case, the depth of the contact hole is reduced, and thus the aspect ratio is improved, so that the layer covering of the metal wire 200 is improved.

이상, 상기 설명과 같이 본 발명은 이중 캡(cap) 절연막에 의한 스페이서를 형성하여, 금속배선의 스텝커버리지를 개선함으로써 반도체 소자의 신뢰성 및 수율을 개선하는 효과가 있다.As described above, the present invention has the effect of improving the reliability and yield of the semiconductor device by forming a spacer by a double cap insulating film to improve the step coverage of the metal wiring.

제 1 도는 종래기술에 따라 금속배선이 형성된 상태의 단면도,1 is a cross-sectional view of a metal wiring formed according to the prior art,

제 2A 도 내지 제 2E 도는 본 발명의 일실시예에 따른 금속배선형성 공정도.2A through 2E are metallization process diagrams according to one embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

21: 반도체 기판 22 : 필드산화막21: semiconductor substrate 22: field oxide film

23: 제1전도막 패턴 24: 제1절연용 산화막23: first conductive film pattern 24: first insulating oxide film

25: 제2전도막 25': 제2전도막 패턴25: second conductive film 25 ': second conductive film pattern

26: 제2절연용 산화막 27: 질화막26: second insulating oxide film 27: nitride film

28: 제3절연용 산화막 28': 스페이서28: third insulating oxide film 28 ': spacer

29: 평탄화용 산화막 200: 금속배선29: planarization oxide film 200: metal wiring

Claims (4)

소정의 패턴이 형성되어 토포로지를 갖는 기판 상에 제1절연막 및 제1전도막을 차례로 형성하는 단계;Forming a first insulating film and a first conductive film on a substrate having a topology by forming a predetermined pattern; 상기 제1전도막상에 제2절연막 및 제3절연막을 차례로 형성하는 단계;Sequentially forming a second insulating film and a third insulating film on the first conductive film; 상기 제1전도막을 패터닝하기 위한 마스크를 사용하여 상기 제3절연막, 제2절연막, 제1전도막을 차례로 식각하는 단계;Etching the third insulating film, the second insulating film, and the first conductive film in sequence by using a mask for patterning the first conductive film; 전체구조 상부에 제4절연막을 형성하는 단계;Forming a fourth insulating film on the entire structure; 상기 제3절연막이 제거될때까지 상기 제4절연막을 비등방성 전면 식각하여 패터닝된 상기 제2절연막 및 제1전도막 패턴 측벽에 제4절연막 스페이서를 형성하는 동시에 상기 제1절연막의 전체두께중 일정두께를 식각하는 단계;The fourth insulating film is anisotropically etched until the third insulating film is removed, thereby forming a fourth insulating film spacer on the sidewalls of the patterned second insulating film and the first conductive film pattern. Etching; 전체구조 상부에 평탄화 제5절연막을 형성하는 단계;Forming a planarization fifth insulating layer on the entire structure; 예정된 금속 콘택홀 부위의 상기 평탄화 절연막 및 제1절연막을 식각하는 단계; 및Etching the planarization insulating layer and the first insulating layer in a predetermined metal contact hole; And 금속막을 형성하는 단계를 포함하는 것을 특징으로 하는 금속배선 형성방법.And forming a metal film. 제 1 항에 있어서;The method of claim 1; 상기 제1절연막 및 제4절연막은 산화막인 것을 특징으로 하는 금속배선 형성방법.And the first insulating film and the fourth insulating film are oxide films. 제 2 항에 있어서;The method of claim 2; 상기 제3절연막은 질화막인 것을 특징으로 하는 금속배선 형성방법.And the third insulating film is a nitride film. 제 3 항에 있어서;The method of claim 3; 상기 제4절연막 스페이서를 형성하기 위한 식각시 제4절연막과 제3절연막간의 식각속도 차이를 1:3 ∼ 1:4로 하여 식각하는 것을 특징으로 하는 금속배선 형성방법.The etching method for forming the fourth insulating film spacer, the etching method between the fourth insulating film and the third insulating film, the etching rate of the metal wiring forming method characterized in that the etching is 1: 3 to 1: 4.
KR1019950006710A 1995-03-28 1995-03-28 Method for fabricating metal interconnection of semiconductor device KR100340072B1 (en)

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KR100340072B1 true KR100340072B1 (en) 2002-10-25

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