KR100351909B1 - Method for fabricating of semiconductor device - Google Patents
Method for fabricating of semiconductor device Download PDFInfo
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- KR100351909B1 KR100351909B1 KR1020000068447A KR20000068447A KR100351909B1 KR 100351909 B1 KR100351909 B1 KR 100351909B1 KR 1020000068447 A KR1020000068447 A KR 1020000068447A KR 20000068447 A KR20000068447 A KR 20000068447A KR 100351909 B1 KR100351909 B1 KR 100351909B1
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- interlayer insulating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Abstract
콘택과 콘택을 직접연결하는 적층형 콘택에서 콘택배선층과 층간절연막 사이에 발생하는 단차를 없애서 콘택 프로파일을 개선할 수 있는 반도체소자의 제조방법을 제공하기 위한 것으로써, 이와 같은 목적을 달성하기 위한 반도체소자의 제조방법은 반도체기판에 게이트전극을 형성하는 공정, 상기 게이트전극 양측의 상기 반도체기판에 불순물영역을 형성하는 공정, 상기 게이트전극의 일측 불순물영역에 비아홀을 갖는 제 1 층간절연막을 형성하는 공정, 상기 비아홀내에 플러그층을 형성하는 공정, 상기 플러그층 상부에 콘택홀을 갖는 제 2 층간절연막을 형성하는 공정, 상기 콘택홀내에 매립용 금속 배선을 형성하는 공정, 상기 매립용 금속 배선이 돌출되도록 상기 제 2 층간절연막을 일정깊이 식각하는 공정, 상기 매립용 금속 배선을 감싸도록 상기 제 2 층간절연막상에 금속층을 증착하는 공정, 상기 매립용 금속 배선상부의 상기 금속층상에 마스크층을 형성하는 공정, 상기 마스크층을 이용해서 상기 제 2 층간절연막이 드러나도록 상기 금속층을 식각함과 동시에 상기 매립용 금속 배선상에 직접적층되도록 금속배선을 형성하는 공정을 포함함을 특징으로 한다.To provide a method for manufacturing a semiconductor device that can improve the contact profile by eliminating the step difference between the contact wiring layer and the interlayer insulating film in the stacked contact directly connecting the contact and the contact, a semiconductor device for achieving the above object The manufacturing method of the method may include forming a gate electrode on a semiconductor substrate, forming an impurity region in the semiconductor substrate on both sides of the gate electrode, forming a first interlayer insulating film having a via hole in one impurity region of the gate electrode, Forming a plug layer in the via hole, forming a second interlayer insulating film having a contact hole on the plug layer, forming a buried metal wire in the contact hole, and allowing the buried metal wire to protrude Etching the second interlayer insulating film to a predetermined depth, so as to surround the buried metal wiring Depositing a metal layer on the second interlayer insulating film, forming a mask layer on the metal layer on the buried metal wiring, and etching the metal layer to expose the second interlayer insulating film using the mask layer. And forming a metal wiring to be directly laminated on the buried metal wiring.
Description
본 발명은 반도체소자에 대한 것으로, 특히 매립용 텅스텐과 절연막 사이에 존재하는 턱을 없애서 이후 공정을 용이하게 실시할 수 있는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device which can be easily carried out by eliminating the tuck existing between the buried tungsten and the insulating film.
첨부 도면을 참조하여 종래 반도체소자의 제조방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a method of manufacturing a conventional semiconductor device is as follows.
도 1a 내지 도 1d는 종래 반도체소자의 제조방법을 나타낸 공정단면도 이다.1A through 1D are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.
종래 반도체소자의 제조방법은 도 1a에 도시된 바와 같이 실리콘기판(1)내에 일구간으로 나뉘어 서로 다른 도전성을 나타내도록 웰(2)을 형성하고, 웰(2)내에 일정깊이로 소정간격을 갖도록 트렌치 격리영역(3)을 형성하고, 실리콘기판(1)의 액티브영역의 일영역에 적층되도록 게이트전극(4)과 캡절연막(5)을 형성하고, 게이트전극(4)과 캡절연막(5)의 측면에 측벽스페이서(6)를 형성하고, 게이트전극(4)양측의 실리콘기판(1)의 표면내에 LDD구조의 불순물영역(7)을 형성한다.In the conventional method of manufacturing a semiconductor device, as shown in FIG. 1A, the wells 2 are formed in the silicon substrate 1 to be divided into one section to show different conductivity, and the wells 2 have a predetermined interval at a predetermined depth. The trench isolation region 3 is formed, the gate electrode 4 and the cap insulation layer 5 are formed so as to be stacked in one region of the active region of the silicon substrate 1, and the gate electrode 4 and the cap insulation layer 5 are formed. The sidewall spacers 6 are formed on the side surfaces of the semiconductor substrate 4, and the impurity regions 7 of the LDD structure are formed on the surface of the silicon substrate 1 on both sides of the gate electrode 4.
이후에 상기 결과물 전면에 제 1 층간절연막(8)을 형성하고, 게이트전극(4) 사이의 불순물영역(7)들에 비아홀을 형성하고, 비아홀내에 폴리 플러그(9)를 형성한다.Thereafter, a first interlayer insulating film 8 is formed on the entire surface of the resultant, via holes are formed in the impurity regions 7 between the gate electrodes 4, and a poly plug 9 is formed in the via holes.
그리고 폴리 플러그(9)를 포함한 실리콘기판(1) 전면에 제 2 층간절연막(10)을 형성한다.A second interlayer insulating film 10 is formed over the silicon substrate 1 including the poly plug 9.
이후에 일 폴리 플러그(9) 상부와 트렌치 격리영역(3) 사이의 불순물영역(7)상과 일 게이트전극(4)이 노출되도록 제 2 층간절연막(10)과 제 1 층간절연막(8)과 캡절연막(5)을 선택적으로 식각해서 콘택홀을 형성한다.Thereafter, the second interlayer insulating film 10 and the first interlayer insulating film 8 and the second interlayer insulating film 8 are exposed to expose the impurity region 7 and the first gate electrode 4 between the upper portion of the poly plug 9 and the trench isolation region 3. The cap insulating film 5 is selectively etched to form contact holes.
그리고 상기 콘택홀을 포함한 제 2 층간절연막(10)상에 텅스텐을 증착한 후에 평탄화공정으로 콘택홀을 매립하고 평탄하게 매립용 텅스텐배선(11)을 형성한다.Then, after depositing tungsten on the second interlayer insulating film 10 including the contact hole, the contact hole is buried in the planarization process, and the buried tungsten wiring 11 is formed flat.
다음에 도 1b에 도시한 바와 같이 매립용 텅스텐 배선(31)을 포함한 제 2 층간절연막(10)상에 텅스텐층(12)을 증착한다.Next, as shown in FIG. 1B, the tungsten layer 12 is deposited on the second interlayer insulating film 10 including the buried tungsten wiring 31.
그리고 텅스텐층(12) 전면에 감광막(13)을 도포한 후 도 1c에 도시한 바와 같이 에 폴리 플러그(9)상부의 매립용 텅스텐 배선(11) 상부에만 감광막(13)이 남도록 노광 및 현상하여 선택적으로 감광막(13)을 패터닝한다.After the photosensitive film 13 is applied to the entire surface of the tungsten layer 12, the photosensitive film 13 is exposed and developed so that the photosensitive film 13 remains only on the upper part of the tungsten wire 11 for embedding on the poly plug 9 as shown in FIG. 1C. Optionally, the photosensitive film 13 is patterned.
다음에 패터닝된 감광막(3)을 마스크로 도 1d에 도시한 바와 같이 텅스텐층(12)을 식각해서 매립용 텅스텐 배선(11)과 적층되는 텅스텐 배선(12a)을 형성한다.Next, the tungsten layer 12 is etched using the patterned photosensitive film 3 as a mask to form a tungsten wiring 12a laminated with the buried tungsten wiring 11.
텅스텐층(12)을 식각할 때 폴리 플러그(9) 상부를 제외한 영역의 텅스텐층(12)과 매립용 텅스텐 배선(11)도 함께 식각된다.When the tungsten layer 12 is etched, the tungsten layer 12 and the buried tungsten wiring 11 in the region except the upper portion of the poly plug 9 are also etched together.
이에 따라서 트렌치 격리영역(13) 사이의 불순물영역(17)과 콘택된 매립용 텅스텐 배선(11)과 게이트전극(4)상부에 콘택된 매립용 텅스텐배선(11)도 같이 식각되므로 이곳의 매립용 텅스텐 배선(11)은 제 2 층간절연막(10)과 단차를 갖게 된다.As a result, the buried tungsten wiring 11 contacted with the impurity region 17 between the trench isolation regions 13 and the buried tungsten wiring 11 contacted over the gate electrode 4 are also etched. The tungsten wiring 11 has a step with the second interlayer insulating film 10.
상기와 같은 종래 반도체소자의 제조방법은 다음과 같은 문제가 있다.The conventional method of manufacturing a semiconductor device as described above has the following problems.
폴리 플러그 상부의 매립용 텅스텐 배선과 직접 적층 콘택되는 텅스텐 배선을 제외한 나머지 매립용 텅스텐 배선과 제 2 층간절연막 사이에 단차가 발생되므로 콘택 프로파일이 나빠진다.A step difference occurs between the buried tungsten wire and the second interlayer insulating film except for the buried tungsten wire on the top of the poly plug and the tungsten wire which is directly laminated contact, so that the contact profile is deteriorated.
본 발명은 상기와 같은 문제를 해결하기 위하여 안출한 것으로 특히, 콘택과 콘택을 직접연결하는 적층형 콘택에서 콘택배선층과 층간절연막 사이에 발생하는 단차를 없애서 콘택 프로파일을 개선할 수 있는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems. In particular, a method of manufacturing a semiconductor device capable of improving a contact profile by eliminating a step generated between a contact wiring layer and an interlayer insulating film in a stacked contact directly connecting a contact to a contact. The purpose is to provide.
도 1a 내지 도 1d는 종래 반도체소자의 제조방법을 나타낸 공정단면도1A through 1D are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.
도 2a 내지 도 2e는 본 발명 반도체소자의 제조방법을 나타낸 공정단면도2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device of the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21 : 실리콘기판 22 : 웰21 silicon substrate 22 well
23 : 트렌치 격리영역 24 : 게이트전극23 trench isolation region 24 gate electrode
25 : 캡절연막 26 : 측벽스페이서25 cap insulation film 26 sidewall spacer
27 : 불순물영역 28 : 제 1 층간절연막27 impurity region 28 first interlayer insulating film
29 : 폴리 플러그 30 : 제 2 층간절연막29 poly plug 30 second interlayer insulating film
31 : 매립용 텅스텐 배선 32 : 텅스텐층31 buried tungsten wiring 32 tungsten layer
33 : 배선 패턴층 33a : 텅스텐 배선33: wiring pattern layer 33a: tungsten wiring
34 : 감광막34: photosensitive film
상기와 같은 목적을 달성하기 위한 본 발명 반도체소자의 제조방법은 반도체기판에 게이트전극을 형성하는 공정, 상기 게이트전극 양측의 상기 반도체기판에 불순물영역을 형성하는 공정, 상기 게이트전극의 일측 불순물영역에 비아홀을 갖는 제 1 층간절연막을 형성하는 공정, 상기 비아홀내에 플러그층을 형성하는 공정, 상기 플러그층 상부에 콘택홀을 갖는 제 2 층간절연막을 형성하는 공정, 상기 콘택홀내에 매립용 금속 배선을 형성하는 공정, 상기 매립용 금속 배선이 돌출되도록 상기 제 2 층간절연막을 일정깊이 식각하는 공정, 상기 매립용 금속 배선을 감싸도록 상기 제 2 층간절연막상에 금속층을 증착하는 공정, 상기 매립용 금속 배선상부의 상기 금속층상에 마스크층을 형성하는 공정, 상기 마스크층을 이용해서 상기 제 2 층간절연막이 드러나도록 상기 금속층을 식각함과 동시에 상기 매립용 금속 배선상에 직접적층되도록 금속배선을 형성하는 공정을 포함함을 특징으로 한다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object includes the steps of forming a gate electrode on a semiconductor substrate, forming an impurity region on the semiconductor substrate on both sides of the gate electrode, Forming a first interlayer insulating film having a via hole, forming a plug layer in the via hole, forming a second interlayer insulating film having a contact hole on the plug layer, and forming a buried metal wiring in the contact hole And etching the second interlayer insulating film to a predetermined depth so that the buried metal wiring is protruded, and depositing a metal layer on the second interlayer insulating film to surround the buried metal wiring. Forming a mask layer on the metal layer, wherein the second interlayer insulating film is formed using the mask layer. Nadorok to the metal layer at the same time as etching, it characterized in that it comprises a step of forming a metal interconnection layer to be directly embedded in the metal for the wirings.
첨부 도면을 참조하여 본 발명 반도체소자의 제조방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a method for manufacturing a semiconductor device of the present invention will be described.
도 2a 내지 도 2e는 본 발명 반도체소자의 제조방법을 나타낸 공정단면도이다.2A through 2E are cross-sectional views illustrating a method of manufacturing the semiconductor device of the present invention.
본 발명 반도체소자의 제조방법은 도 2a에 도시된 바와 같이 실리콘기판(21)내에 일구간으로 나뉘어 서로 다른 도전성을 나타내도록 웰(22)을 형성하고, 웰(22)내에 일정깊이로 소정간격을 갖도록 트렌치 격리영역(23)을 형성하고, 실리콘기판(21)의 액티브영역의 일영역에 적층되도록 게이트전극(24)과 캡절연막(25)을 형성하고, 게이트전극(24)과 캡절연막(25)의 측면에 측벽스페이서(26)를 형성하고, 게이트전극(24)양측의 실리콘기판(21)의 표면내에 LDD구조의 불순물영역(27)을 형성한다.In the method of manufacturing the semiconductor device of the present invention, as shown in FIG. 2A, the wells 22 are formed in the silicon substrate 21 to be divided into one section to show different conductivity, and a predetermined interval is formed in the wells 22 at a predetermined depth. The trench isolation region 23 is formed to have a thickness, the gate electrode 24 and the cap insulation layer 25 are formed so as to be stacked in one region of the active region of the silicon substrate 21, and the gate electrode 24 and the cap insulation layer 25 are formed. The sidewall spacers 26 are formed on the side surfaces of the (), and the impurity regions 27 of the LDD structure are formed on the surface of the silicon substrate 21 on both sides of the gate electrode 24.
이후에 상기 결과물 전면에 제 1 층간절연막(28)을 형성하고, 게이트전극(24) 사이의 불순물영역(27)들에 비아홀을 형성하고, 비아홀내에 폴리 플러그(29)를 형성한다.Subsequently, a first interlayer insulating layer 28 is formed on the entire surface of the resultant, via holes are formed in the impurity regions 27 between the gate electrodes 24, and poly plugs 29 are formed in the via holes.
그리고 폴리 플러그(29)를 포함한 실리콘기판(21) 전면에 제 2 층간절연막(30)을 형성한다.A second interlayer insulating film 30 is formed on the entire surface of the silicon substrate 21 including the poly plug 29.
이후에 일 폴리 플러그(29) 상부와 트렌치 격리영역(23) 사이의 불순물영역(27)상과 일 게이트전극(24)이 노출되도록 제 2 층간절연막(30)과 제 1 층간절연막(28)과 캡절연막(25)을 선택적으로 식각해서 콘택홀을 형성한다.Thereafter, the second interlayer insulating film 30 and the first interlayer insulating film 28 are exposed to expose the impurity region 27 and the gate electrode 24 between the upper portion of the poly plug 29 and the trench isolation region 23. The cap insulation layer 25 is selectively etched to form contact holes.
그리고 상기 콘택홀을 포함한 제 2 층간절연막(30)상에 텅스텐을 증착한 후에 평탄화공정으로 콘택홀을 매립하고 평탄하게 매립용 텅스텐배선(31)을 형성한다.Then, after depositing tungsten on the second interlayer insulating film 30 including the contact hole, the contact hole is buried in the planarization process, and the buried tungsten wiring 31 is formed flat.
다음에 도 2b에 도시한 바와 같이 종래 기술에 의해서 발생할 수 있는 매립용 텅스텐배선(31)과 제 2 층간절연막(30)과의 단차만큼의 제 2 층간절연막(30)을미리 식각한다. 이에 따라서 매립용 텅스텐 배선(31)의 상부가 돌출 형성된다.Next, as shown in FIG. 2B, the second interlayer insulating film 30 is etched in advance as much as a step between the buried tungsten wiring 31 and the second interlayer insulating film 30, which may be generated by the prior art. Accordingly, the upper part of the buried tungsten wiring 31 is formed to protrude.
이후에 도 2c에 도시한 바와 같이 돌출된 매립용 텅스텐 배선(31)을 감싸도록 텅스텐층(32)을 증착한다.Thereafter, as illustrated in FIG. 2C, a tungsten layer 32 is deposited to surround the protruding buried tungsten wire 31.
그리고 텅스텐층(32) 전면에 감광막(33)을 도포한 후에 도 2d에 도시한 바와 같이 폴리 플러그(29)상부의 매립용 텅스텐 배선(31) 상부에만 감광막(33)이 남도록 노광 및 현상하여 선택적으로 감광막(33)을 패터닝한다.After the photoresist film 33 is applied to the entire surface of the tungsten layer 32, the photoresist film 33 is exposed and developed so that the photoresist film 33 remains only on the upper part of the buried tungsten wire 31 on the poly plug 29 as shown in FIG. 2D. The photosensitive film 33 is patterned by this.
다음에 패터닝된 감광막(33)을 마스크로 도 2e에 도시한 바와 같이 텅스텐층(32)을 식각해서 매립용 텅스텐 배선(31)과 적층되는 텅스텐 배선(32a)을 형성한다.Next, the tungsten layer 32 is etched using the patterned photosensitive film 33 as a mask to form a tungsten wire 32a laminated with the buried tungsten wire 31.
텅스텐 배선(32a)을 식각할 때 폴리 플러그(29)상부의 매립용 텅스텐 배선(31)을 제외한 나머지 상측의 텅스텐층(32)과 매립용 텅스텐 배선(31)은 제 2 층간절연막(30)이 노출될때까지 식각된다.When the tungsten wire 32a is etched, the tungsten layer 32 and the buried tungsten wire 31 on the upper side except for the buried tungsten wire 31 on the upper side of the poly plug 29 are formed of the second interlayer insulating film 30. Etched until exposed.
이에 따라서 매립용 텅스텐 배선(31)과 제 2 층간절연막(30)에는 단차가 발생되지 않고 평탄한 면을 이룬다.Accordingly, the buried tungsten wiring 31 and the second interlayer insulating film 30 form a flat surface without generating a step.
상기와 같은 본 발명 반도체소자의 제조방법은 다음과 같은 효과가 있다.The method of manufacturing the semiconductor device of the present invention as described above has the following effects.
매립용 텅스텐 배선과 층간절연막 사이에 단차가 발생하는 것을 방지해서 차후에 공정을 평탄하게 진행하기가 용이해진다.It is possible to prevent a step from occurring between the buried tungsten wiring and the interlayer insulating film, thereby facilitating the process later.
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