JP2000114373A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To design of wiring considering only device characteristics by setting the depth of a wiring connecting hole and a wiring groove separately, when the hole and the wiring groove are formed. SOLUTION: This manufacturing method consists of a process where an inter-layer insulating film is formed by accumulating a first SiN film 12, a first SiO film 13, a second SiN film 14 and a thin second SiO film 20 in this order on an insulating film 10, where a lower metal buried wiring 11 is formed, a process where a via hole 16 whose bottom part reaches the first SiN film is formed by etching the second SiO film, the second SiN film and the first SiO film, a process where a wiring groove 18 whose bottom part has a specified depth in the middle of the film thickness of the first SiO film is formed by etching the second SiO film, the second SiN film and the first SiO film by RIE(reactive ion etching), and a process where an opening is formed so that the bottom part of the via hole reaches the lower metal buried wiring by etching the whole surface by RIE.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a wiring connection hole and a wiring groove using a dual damascene process.

[0002]

2. Description of the Related Art In manufacturing a semiconductor device, when a metal wiring is buried by forming a wiring connection hole (contact hole or via hole) and a wiring groove in an insulating film formed on a semiconductor substrate, usually, a dual damascene process is used. Are used to form wiring connection holes and wiring grooves.

However, in the conventional process of forming the wiring connection hole and the wiring groove, there are limited conditions in relation to the depth of the wiring connection hole and the wiring groove and the thickness of the interlayer insulating film. There is a problem in that the depth and the depth of the wiring groove cannot be set independently, and it is not possible to design the wiring only in consideration of the characteristics of the semiconductor device.

[0004] This problem will be described in detail below. FIG.
4A to 4C show cross sections of a substrate in a process of forming a second or later Cu embedded wiring in a semiconductor device having a conventional multilayer Cu embedded wiring structure.

[0005] First, as shown in FIG.
On the upper surface of the insulating film 30 on the semiconductor substrate on which the buried wiring 31 is formed, a first SiN film 32 for a Cu wiring cap film, a SiO film 33 as an interlayer insulating film, and a CMP (Chemical Mechanical A second SiN film 34 for a stopper for polishing is sequentially formed.

Next, a via hole for connecting an interlayer wiring and a wiring groove for a buried wiring are formed in the interlayer insulating film by using a dual damascene process. First, as shown in FIG. 3B, a resist pattern 35 having an opening pattern corresponding to a via hole for connecting an interlayer wiring is formed on an interlayer insulating film by using a photolithography method and an RIE (reactive ion etching) method. Form. Then, the second SiN is formed by RIE using the resist pattern 35 as a mask.
The film 34 and the SiO film 33 are etched to form a via hole 36. At this time, the depth of the via hole 36 is
The RIE is temporarily stopped in a state where the thickness of the O film 33 reaches halfway.

Next, after the resist pattern 35 is peeled off, as shown in FIG. 3C, a resist pattern 37 having an opening pattern corresponding to the buried wiring groove is formed. At this time, the pattern opening corresponding to the buried wiring groove is continuous with the via hole 36.

Then, the second SiN film 34 and the second SiN film 34 are formed by RIE using the resist pattern 37 as a mask.
The iO film 33 is etched to form a wiring groove 38 having a desired depth. At this time, RIE is performed in a state where the bottom (tip) of the via hole 36 has reached the first SiN film 32 (the depth of the wiring groove 38 has reached the middle of the thickness of the SiO film 33).
Is stopped to leave the first SiN film 32 for a role to be described later.

Next, the resist pattern 37 is peeled off by, for example, an O ₂ ashing method to remove the second SiN film 3.
Expose 4. At this time, the first SiN film 32 plays a role in preventing the lower Cu embedded wiring 31 from being oxidized.

Next, as shown in FIG.
E is performed to open the bottom of the via hole 36 so as to reach the lower layer Cu embedded wiring 31. Next, FIG.
As shown in FIG. 2B, after a Cu film 39 for an embedded wiring is formed on the entire surface by a sputtering method, the Cu film 39 is melted by a laser irradiation method.

Subsequently, as shown in FIG. 4 (c), the Cu film 39 in an extra portion other than the wiring portion is removed by the C film so that the Cu film 39 remains in the desired wiring groove to form a Cu embedded wiring.
It is polished and removed by the MP method.

In the conventional RIE process of the via hole and the wiring groove as described above, the second SiN film 34 is formed.
And the depth of the via hole 36 is
The first RIE in which the etching is stopped in a state where the thickness of the O film 33 has reached halfway, so that the bottom of the via hole 36 reaches the first SiN film 32 and the wiring groove 38 has a desired depth. Second RI for etching
E and two stages.

As described above, the method of determining the depths of the via holes 36 and the wiring grooves 38 by the two-step RIE processing appropriately adjusts the relationship between the etching amount by the first RIE and the etching amount by the second RIE. It is necessary to set the thickness, and for this purpose, it is necessary to appropriately set the thickness of the interlayer insulating film.

However, via holes 36 and wiring grooves 38
In other words, if there is a limiting condition between the depth of the via and the thickness of the interlayer insulating film, in other words, the depth of the via hole 36 and the depth of the wiring groove 38 cannot be set independently. Thus, there is a restriction in designing wiring.

[0015]

As described above, the step of forming a via hole and a wiring groove by using the conventional dual damascene process is limited by the relationship between the depth of the via hole and the wiring groove and the thickness of the interlayer insulating film. Therefore, the depth of the via hole and the depth of the wiring groove cannot be set independently, and there has been a problem that it is not possible to design the wiring only in consideration of the characteristics of the semiconductor device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems. When forming a wiring connection hole and a wiring groove by using a dual damascene process, the depth of the wiring connection hole and the wiring groove are reduced. An object of the present invention is to provide a method of manufacturing a semiconductor device, which can be set independently, enables wiring design in consideration of only characteristics of a semiconductor device, and can realize a good embedded wiring. I do.

[0017]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first cap film as an interlayer insulating film on the entire upper surface of a semiconductor substrate in which a lower metal buried wiring is formed; SiN film, first SiO film, metal C
A step of sequentially depositing and forming a second SiN film and a second SiO film for an MP stopper, and forming a first resist pattern having an opening pattern corresponding to a via hole for connecting an interlayer wiring on the interlayer insulating film. Forming the second SiO film using the first resist pattern as a mask;
Etching a second SiN film and a first SiO film to form a via hole with a bottom reaching the first SiN film; removing the first resist pattern; Forming a second resist pattern having an opening pattern corresponding to the buried wiring groove on the film and having a pattern opening connected to the via hole; and forming the second resist pattern by a reactive ion etching method using the second resist pattern as a mask. Forming a wiring groove with a bottom portion reaching a desired depth in the middle of the thickness of the first SiO film by etching the SiO film, the second SiN film, and the first SiO film; Removing the second resist pattern and etching the entire surface by the reactive ion etching method so that the bottom of the via hole is the lower metal layer. Characterized by comprising the step of opening so as to reach the order included wiring.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the step of forming the wiring groove includes the step of forming the first SiN film exposed at the bottom of the via hole. Is exposed to a plasma of a first processing gas containing a fluorocarbon-based gas having no hydrogen bond.
And a plasma of a second processing gas containing a fluorocarbon-based gas having a hydrogen bond and a CO gas,
The first S exposed to the plasma of the first processing gas
For the iN film, the second SiO film, the second SiN film (not exposed to the plasma of the first processing gas) and the first SiO film are etched at substantially the same rate, selectively. And a second step.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings. 1 (a) to 2 (c)
FIG. 4 shows a cross section of a substrate in a step of forming a second or later Cu embedded wiring in a semiconductor device having a multilayer Cu embedded wiring structure according to the first embodiment of the present invention.

First, as shown in FIG. 1A, a Cu film as an interlayer insulating film is formed on the upper surface of the insulating film 10 on the semiconductor substrate in which the element and the lower Cu embedded wiring 11 are formed.
First SiN film 12 for wiring cap film, first SiO
Film 13, second S for stopper for post-process CMP
An iN film 14 and a thin second SiO film 20 are sequentially deposited to form a laminated insulating film.

Next, via holes for connecting interlayer wiring and wiring grooves for buried wiring are formed in the interlayer insulating film using a dual damascene process. First, a resist pattern (pattern of a photosensitive resin film) 15 having an opening pattern corresponding to a via hole for connecting an interlayer wiring is formed on an interlayer insulating film by using a photography method and an RIE method.

Then, the second SiO film 20, the second SiN film 14, and the first SiO film 13 are etched by RIE using the resist pattern 15 as a mask to form a via hole 16. At this time, the via hole 16
The RIE is stopped with the bottom (tip) of the first SiN film 12 reaching the first SiN film 12, thereby leaving the first SiN film 12 for a role to be described later.

Next, after removing the resist pattern 15, as shown in FIG. 1B, a resist pattern 17 having an opening pattern corresponding to the embedded wiring groove is formed. At this time, the pattern opening corresponding to the buried wiring groove is continuous with the via hole 16.

A gas system mainly composed of C ₄ F ₈ (for example, C ₄ F ₈₎
RIE using ₄ F ₈ / CO / Ar) and the second SiO film 2 using the resist pattern 17 as a mask.
Etching is performed halfway through the film thickness of 0.

[0025] Then, before the second SiN film 14 is exposed, to continue the RIE is switched to CHF ₃ principal gas system (e.g. CHF ₃ / CO), as shown in FIG. 1 (c),
The second SiO film 20 and the second SiO film 20 are formed until the bottom of the wiring groove 18 reaches a desired depth in the middle of the thickness of the first SiO film 13.
The SiN film 14 and the first SiO film 13 are etched.

Next, the resist pattern 17 is removed by, for example, an O ₂ ashing method to remove the second SiO film 2.
0 is exposed. At this time, the first SiN film 12 serves to prevent the lower Cu embedded wiring 11 from being oxidized.

Next, as shown in FIG.
E is performed to open the via hole 16 so that the bottom of the via hole 16 reaches the lower Cu embedded wiring 11. Next, FIG.
As shown in (b), after a Cu film 19 for embedded wiring is formed on the entire surface by a sputtering method, the Cu film 19 is melted by a laser irradiation method.

Subsequently, as shown in FIG.
Excess portions of the film 19 other than the wiring portion (the second SiO 2
Upper portion of the film 20) and the second S
The iO film 20 is polished and removed by the CMP method, so that Cu embedded wiring remains in desired via holes and wiring grooves.

When the wiring connection hole 16 and the wiring groove 18 are formed using the dual damascene process as in the above embodiment, first, the first insulating film 12 reaches the first SiN film 12 on the lower metal embedded wiring 11 in the interlayer insulating film. A via hole 16 in a state of being formed is formed.

Next, when forming the wiring groove 18, first, C
₄ performs a first round of RIE using F ₈ main gas system (e.g., _{C 4 F 8 / CO / Ar} ), etched to the middle of the thickness of the second SiO 2 film 20.

[0031] Then, before the second SiN film 14 is exposed, CHF ₃ main gas system (e.g. CHF ₃ / CO) the switching continue to the second RIE, bottom first wiring grooves 18 The second SiO film 20, the second SiN film 14, and the first SiO film 13 are etched until a desired depth in the middle of the thickness of the SiO film 13 is reached.

In this case, in the first RIE, after exposing the first SiN film 12 to C ₄ F ₈ gas plasma, which is a fluorocarbon-based gas having no hydrogen bond, the first SiN film 12 is exposed to a fluorocarbon-based gas having a hydrogen bond. When the second RIE is performed with a certain CHF ₃ gas plasma, the first SiN film 1
2 is significantly slowed down and the second SiO 2
It is known that the effect of obtaining a sufficient selectivity with respect to the etching with respect to the film 20 and the first SiO film 13 is known (as described in detail in the specification of Japanese Patent Application No. Hei 8-135028 of the present inventors). We are using.

That is, the first SiN film 12 exposed to the C ₄ F ₈ gas plasma in the first RIE is selectively etched, and the second SiO film 20 and the second SiN
The film 14 (which is covered with the second SiO film 20 at the time of the first RIE and is not exposed to the C ₄ F ₈ gas plasma) and the first SiO film 13 are etched at substantially the same speed. Become.

Therefore, according to the above embodiment, the depth of the wiring connection hole 16 and the depth of the wiring groove 18 are set independently,
Wiring can be designed in consideration of only the characteristics of the semiconductor device, and good embedded wiring can be realized.

In the step of forming the wiring groove 18 in the above embodiment, basically, the first SiN film 12 exposed at the bottom of the via hole is formed by removing the first SiN film 12 containing a fluorocarbon-based gas having no hydrogen bond. A first step of exposing to a plasma of a first processing gas, and a second step of exposing to a plasma of a first processing gas using a plasma of a second processing gas containing a fluorocarbon-based gas having a hydrogen bond and a CO gas. Selectively for the first SiN film 12 and the second S
a second step of etching the iO film 20, the second SiN film 14 and the first SiO film 13 that have not been exposed to the plasma of the first processing gas at substantially the same rate.

Here, the fluorocarbon-based gas having no hydrogen bond is desirably a gas capable of generating a large amount of CF ₂ + ions in plasma, like the above-mentioned C ₄ F ₈ gas. Further, as the first processing gas, for example, the above-mentioned mixed gas of C ₄ F ₈ and CO and Ar or C
₄ mixed gas of F ₈ and Ar can be mentioned.

The fluorocarbon-based gas having a hydrogen bond includes, for example, the above-mentioned CHF ₃ gas or CH ₃ F gas. Further, as the second processing gas, for example, the above-mentioned mixed gas of CHF ₃ and CO can be used.

Before the Cu film 19 for the embedded wiring is formed on the entire surface by sputtering, a film containing a high melting point metal as a barrier metal layer for preventing diffusion of Cu into the interlayer insulating film. May be formed.

In the above embodiment, the method of embedding the Cu wiring has been described. However, the same effect as in the above embodiment can be obtained when the embedded wiring is formed by embedding a metal containing Cu as a main component or another metal. Is obtained.

[0040]

As described above, according to the method of manufacturing a semiconductor device of the present invention, when forming a wiring connection hole and a wiring groove using a dual damascene process, the depth of the wiring connection hole and the wiring groove depth are reduced. Independently, the wiring can be designed in consideration of only the characteristics of the semiconductor device, and a good embedded wiring can be realized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a substrate showing a part of a process of forming a Cu embedded wiring according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a substrate showing a step that follows the step of FIG.

FIG. 3 is a cross-sectional view of a substrate showing a part of a step of forming a via hole and a wiring groove using a conventional dual damascene process.

FIG. 4 is a sectional view of the substrate showing a step that follows the step of FIG. 3;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Insulation film on a semiconductor substrate, 11 ... Lower Cu embedded wiring, 12 ... First SiN film for Cu wiring cap film, 13 ... First SiO film, 14 ... Second SiN film for stopper for CMP Reference numeral 15, 17: resist pattern (pattern of photosensitive resin film), 16: via hole, 18: wiring groove, 19: Cu film for embedded wiring, 20: thin second SiO film.

Continued on the front page F term (reference)

Claims (11)

[Claims] 1. A first SiN film for a cap film, a first SiO film, and a metal C as an interlayer insulating film over the entire upper surface of a semiconductor substrate on which a lower metal embedded wiring is formed.
A step of sequentially depositing and forming a second SiN film and a second SiO film for an MP stopper; and forming a first resist pattern having an opening pattern corresponding to a via hole for connecting an interlayer wiring on the interlayer insulating film. Forming a via hole using the first resist pattern as a mask to etch the second SiO film, the second SiN film, and the first SiO film so that the bottom reaches the first SiN film; Forming a first resist pattern; forming a second resist pattern having an opening pattern corresponding to the buried wiring groove on the interlayer insulating film and having a pattern opening connected to the via hole; And forming the second SiO film and the second Si by a reactive ion etching method using the second resist pattern as a mask.
The N film and the first SiO film are etched so that the bottom is
Forming a wiring groove reaching a desired depth in the middle of the thickness of the SiO film, removing the second resist pattern, performing an entire surface etching by the reactive ion etching method, Opening the via hole so that the bottom of the via hole reaches the lower metal buried wiring. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the wiring groove includes the step of forming the first SiN exposed at a bottom of the via hole.
A first step of exposing the film to a plasma of a first processing gas containing a fluorocarbon-based gas having no hydrogen bond, and using a plasma of a second processing gas containing a fluorocarbon-based gas having a hydrogen bond and a CO gas Selectively etching the first SiN film exposed to the plasma of the first processing gas;
A second step of etching the film, the second SiN film, and the first SiO film at substantially the same rate. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the fluorocarbon-based gas having no hydrogen bond is capable of generating a large amount of CF ₂ + ions in plasma. Production method. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the fluorocarbon-based gas capable of generating a large amount of CF ₂ + ions in the plasma is a C ₄ F ₈ gas. Method. 5. The method of manufacturing a semiconductor device according to claim 2, wherein the first processing gas is a mixed gas of C ₄ F ₈ and Ar. A method for manufacturing a semiconductor device. 6. The method of manufacturing a semiconductor device according to claim 2, wherein the first processing gas is a mixed gas of C ₄ F ₈ , CO, and Ar. Manufacturing method of a semiconductor device. 7. The method for manufacturing a semiconductor device according to claim 2, wherein the fluorocarbon-based gas having a hydrogen bond is CHF.
_A method for manufacturing a semiconductor device, comprising _three gases. 8. The method for manufacturing a semiconductor device according to claim 2, wherein the fluorocarbon-based gas having a hydrogen bond is CH _3.
A method for manufacturing a semiconductor device, comprising F gas. 9. The method of manufacturing a semiconductor device according to claim 2, wherein the second processing gas is a mixed gas of CHF ₃ and CO. Manufacturing method. 10. The method of manufacturing a semiconductor device according to claim 1, wherein the step of removing the second resist pattern includes an O ₂ ashing method. Manufacturing method. 11. The method for manufacturing a semiconductor device according to claim 1, further comprising, after the step of opening the bottom of the via hole so as to reach the lower metal buried wiring, further comprising: Is formed on the entire surface, and the metal is melted by a laser irradiation method.
A step of leaving a metal-buried wiring in the via hole and the wiring groove by polishing and removing the metal on the upper part of the SiO film and the second SiO film remaining therebelow by a chemical mechanical polishing method. A method for manufacturing a semiconductor device, comprising: