JP3988592B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a step of forming a wiring groove and a connection hole in a low dielectric constant (Low-k) film to form a dual damascene wiring.
[0002]
[Prior art]
When the wiring of a semiconductor device is miniaturized, the increase in inter-wiring capacitance becomes significant, and wiring delay becomes a problem. For the purpose of improving the wiring delay and increasing the speed of the semiconductor device, a low dielectric constant film called a low-k film has been adopted as an interlayer insulating film. According to the Cu dual damascene wiring in which the low dielectric constant film is combined with the Cu wiring having a resistance lower than that of the conventional Al wiring, the capacitance between the wirings can be reduced.
As the low dielectric constant film, there are various types such as an organic type or inorganic type formed by application of a solution, or a SiOF type, SiOC type, CF type formed by chemical vapor deposition (CVD). Developed and studied.
[0003]
Since the coating type organic low dielectric constant film has a composition relatively close to that of the resist, the etching selection ratio with the resist is insufficient, or the resist is damaged when the resist is removed. Therefore, when forming a Cu dual damascene wiring using a coating-type organic low dielectric constant film, wiring grooves and connection holes are usually formed using a hard mask made of an inorganic material in addition to a resist.
[0004]
Also, Cu dual damascene wiring is formed by simultaneously burying Cu in wiring grooves and connection holes previously formed in the interlayer insulating film, so both patterns are transferred to the wafer in the formation process of the wiring grooves and connection holes. Is done. If a misalignment between the wiring groove and the connection hole occurs, there is a possibility that a resistance increase due to contact failure, a short circuit, or the like occurs. Therefore, a dual hard mask method using a two-layer hard mask has been developed in order to increase the alignment accuracy between the wiring groove and the connection hole.
[0005]
Hereinafter, a method for forming a Cu dual damascene wiring by a conventional dual hard mask method will be described with reference to FIGS. First, as shown in FIG. 20A, a silicon nitride film 102 is formed as a barrier insulating film on the lower wiring 101 with a thickness of 50 nm, for example. The silicon nitride film 102 prevents Cu diffusion.
[0006]
A silicon oxide film 103 is formed as a connection layer insulating film on the silicon nitride film 102 with a thickness of, for example, 500 nm. In the silicon oxide film 103, connection holes for connecting the wirings are formed. As the silicon oxide film 103, NSG (non-doped silicate glass), PSG (phospho silicate glass), BPSG (boro-phospho silicate glass) having a relative dielectric constant of about 4.0, or FSG having a relative dielectric constant of about 3.5. (Fluoro silicate glass) or the like is used.
[0007]
An organic film 104 is formed as a wiring layer insulating film on the silicon oxide film 103 with a thickness of, for example, 400 nm. A wiring groove is formed in the organic film 104, and Cu wiring is embedded in the wiring groove. Examples of the organic film 104 include SiLK (trade name, manufactured by Dow Chemical Co., Ltd.) and FLARE (trade name, US Allied Signal), which are polyaryl ether (PAE) materials having a relative dielectric constant of about 2.7. Used. These organic films are generally made of SiO. ₂ Since the dielectric constant is low compared to the above, the parasitic capacitance of the wiring can be reduced. The material of the organic film 104 is applied by, for example, a spin coating method.
[0008]
A silicon oxide film 105 is formed on the organic film 104 as a first hard mask with a thickness of 200 nm, for example. The silicon oxide film 105 can be formed by, for example, a parallel plate plasma CVD method using silane gas as a raw material.
A silicon nitride film 106 is formed as a second hard mask on the silicon oxide film 105, for example, with a thickness of 100 nm. The silicon nitride film 106 can be formed by, for example, a parallel plate plasma CVD method using silane gas as a raw material. The combination of the hard mask materials may be changed to another example as long as it is applicable to the dual hard mask method.
[0009]
Next, as shown in FIG. 20B, a resist 107 having a wiring groove pattern is formed by lithography. At this time, the lower layer wiring 101 is used for alignment. Lithography is, for example, photolithography using a KrF laser, and the numerical aperture NA is, for example, 0.60.
[0010]
Next, as shown in FIG. 20C, the silicon nitride film 106 is etched using the resist 107 as a mask to transfer the wiring groove pattern to the second hard mask, and then the resist 107 is removed. For example, the etching of the silicon nitride film 106 is CHF. _Three / O ₂ / Parallel plate plasma etching using Ar gas as etching gas.
[0011]
Next, as shown in FIG. 21 (d), a resist 108 having a connection hole pattern is formed by lithography. At this time, the lower layer wiring 101 is used for alignment. This lithography may be photolithography similar to the resist 107.
[0012]
Next, as shown in FIG. 21E, using the resist 108 as a mask, a process corresponding to the etching for the thickness (100 nm) of the silicon nitride film 106 and the etching of the silicon oxide film 105 are performed. As a result, the connection hole pattern is transferred to the first hard mask. Thereafter, the resist 108 is removed.
[0013]
Here, the etching for the thickness (100 nm) of the silicon nitride film 106 is performed in consideration of the case where the connection hole pattern protrudes from the wiring groove pattern due to misalignment in the lithography process. If only the silicon oxide film 105 is etched, the silicon nitride film 106 serves as a mask in the portion where the connection hole pattern protrudes from the wiring groove pattern, and the silicon oxide film 105 is not etched. In this case, the connection hole cannot be formed in a normal shape.
[0014]
When the silicon nitride film 106 is also etched, the connection hole pattern is transferred to both the first hard mask and the second hard mask at the portion where the connection hole pattern protrudes from the wiring groove pattern. Therefore, the connection hole can be formed in a normal shape. Etching of the silicon nitride film 106 is performed in the same manner as the step shown in FIG. Etching of the silicon oxide film 105 is performed by, for example, C _Five F ₈ Parallel plate plasma etching using / CO / Ar gas as an etching gas is performed.
[0015]
Next, as shown in FIG. 21F, the organic film 104 which is the wiring layer insulating film is etched to transfer the connection hole pattern formed in the first hard mask (silicon oxide film 105). This etching also removes the resist 108.
Next, as shown in FIG. 22G, the silicon oxide films 103 and 105 are etched. As a result, a connection hole 109 is formed in the silicon oxide film 103 which is a connection layer insulating film. Further, the wiring groove pattern formed on the second hard mask (silicon nitride film 106) is transferred to the first hard mask (silicon oxide film 105).
[0016]
Next, as shown in FIG. 22H, the organic film 104 is etched using the first hard mask (silicon oxide film 105) and the second hard mask (silicon nitride film 106) as a mask. A wiring trench 110 is formed in the substrate.
Next, as shown in FIG. 22I, the silicon nitride films 102 and 106 are etched. As a result, a connection hole is formed in the barrier insulating film (silicon nitride film 102), and the second hard mask (silicon nitride film 106) is removed.
[0017]
Through the above steps, the wiring groove 110 and the connection hole 109 are formed. Thereafter, a Cu layer is formed so as to fill the wiring trench 110 and the connection hole 109, and then, for example, chemical mechanical polishing (CMP) is performed to remove an excess Cu layer on the insulating film, and the surface Is planarized to form Cu dual damascene wiring.
[0018]
[Problems to be solved by the invention]
However, according to the conventional dual hard mask method, the lower layer wiring 101 is used for alignment when forming the resist 108 having the opening of the connection hole pattern in the photolithography process shown in FIG. Since the connection hole pattern is inside the wiring groove pattern, the wiring groove pattern transferred to the second hard mask (silicon nitride film 106) cannot be used for alignment. That is, the alignment of the connection hole pattern is not directly aligned with the wiring groove pattern.
[0019]
In the step shown in FIG. 20B, alignment is performed using the lower layer wiring 101 when the resist 107 having the opening of the wiring groove pattern is formed. Therefore, according to the above-described conventional method, the alignment of the wiring groove pattern and the connection hole pattern is double indirect alignment via the lower layer wiring 101.
[0020]
In general, the misalignment amount is about 1.4 times in double indirect alignment with respect to direct alignment. Therefore, when trying to form a fine wiring pattern by the above-described conventional method, a wiring short circuit failure is unavoidable. For example, in KrF photolithography, about 100 nm is a 3 sigma value of misalignment amount in direct alignment, but is about 140 nm in indirect alignment.
[0021]
Here, a case where a fine wiring pattern having a wiring interval of 200 nm is formed will be described as an example. In a semiconductor integrated circuit having a gate length of 0.13 μm, it is considered that a wiring interval of 200 nm is typically required. As shown in FIG. 23A, it is assumed that the wirings 111 are formed with an interval of 200 nm, and the connection holes 112 are formed without margins at the ends of the wirings 111 in the width direction.
[0022]
As shown in FIG. 23B, when the shift amount between the wiring pattern and the connection hole pattern is 140 nm, the separation width between the connection hole 112 and the adjacent wiring 111 is 60 nm. In this case, considering the variation in the etching process, there is a high possibility that a short circuit will occur.
[0023]
Therefore, it is difficult to apply the conventional dual hard mask method to such a very fine wiring pattern. When the fine wiring is formed using the conventional dual hard mask method, there arises a problem that the product yield is lowered due to the variation in misalignment amount and the production cost is increased.
[0024]
Alternatively, it is possible to suppress the misalignment amount of typically 100 nm by performing the lithography process again and again several times. However, in this case, the production cost increases due to a decrease in throughput and an increase in consumption of resist material.
[0025]
The dual hard mask method is a method developed in order to use an organic material that is damaged when the resist is peeled for the wiring layer insulating film. According to the dual hard mask method, since the wiring layer insulating film is not exposed in the lithography process, the wiring layer insulating film is prevented from being damaged. However, since the wiring groove pattern lithography is performed, the connection hole pattern lithography is performed. Indirect alignment is inevitable.
[0026]
The present invention has been made in view of the above problems. Therefore, the present invention does not damage the organic low dielectric constant film at the time of resist peeling, and improves the alignment accuracy between the wiring groove and the connection hole. An object is to provide a method for manufacturing a semiconductor device.
[0027]
[Means for Solving the Problems]
In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes an insulating film, an organic low dielectric constant film, a first hard mask, a second hard mask, a third hard mask, A step of sequentially stacking a fourth hard mask, a step of forming a first resist having an opening with a connection hole pattern on the fourth hard mask, and the fourth resist using the first resist as a mask. Etching the thickness of each of the third and second hard masks in order, transferring the connection hole pattern to the second to fourth hard masks, removing the first resist, Forming a second resist having an opening with a wiring groove pattern including the connection hole pattern on the fourth hard mask; and using the second resist as a mask, Etching the thickness of the mask, transferring the wiring groove pattern to the fourth hard mask, removing the second resist, and using the fourth hard mask as a mask, the third hard mask. The hard mask is etched for a thickness, the wiring groove pattern is transferred to the third hard mask, and the first hard mask is etched for the thickness using the second hard mask as a mask. And transferring the connection hole pattern to the first hard mask, etching the organic low dielectric constant film by a thickness using the first and second hard masks as a mask, and Transferring the connection hole pattern to the low dielectric constant film; removing the fourth hard mask by etching; and using the third hard mask as a mask. Etching a thickness of the second hard mask to transfer the wiring groove pattern to the second hard mask; removing the third hard mask by etching; and removing the second hard mask The first hard mask is etched to a thickness using the mask as a mask, the wiring groove pattern is transferred to the first hard mask, and the organic low dielectric constant film is used as a mask to thicken the insulating film. Etching for a certain amount to form a connection hole in the insulating film, and etching the organic low dielectric constant film for a thickness using the first and second hard masks as a mask, Forming a wiring groove in the low dielectric constant film; removing the second hard mask by etching; and embedding a conductor in the wiring groove and the connection hole. It is characterized by having.
[0028]
Alternatively, the method of manufacturing a semiconductor device according to the present invention includes a step of sequentially stacking an insulating film, an organic low dielectric constant film, a first hard mask, and a second hard mask on a lower layer wiring, and the second hard mask. Further, a step of forming a first resist having an opening with a connection hole pattern, etching the second hard mask with a thickness using the first resist as a mask, and further forming the first hard Etching the mask halfway, transferring the connection hole pattern to the upper surface side of the first hard mask and the second hard mask, removing the first resist, and the second hard mask Forming a second resist having an opening with a wiring groove pattern including the connection hole pattern on the mask; and using the second resist as a mask, the second hard mask. Etching the thickness, transferring the wiring groove pattern to the second hard mask, removing the second resist, and using the second hard mask as a mask. Etching less than the thickness of the hard mask is performed, the wiring groove pattern is transferred to the upper surface side of the first hard mask, and the first hard mask in the portion where the connection hole pattern is transferred is removed. Etching the thickness of the organic low dielectric constant film using the first hard mask as a mask, and transferring the connection hole pattern to the organic low dielectric constant film; and the second Etching is performed on the first hard mask using a hard mask as a mask, the wiring groove pattern corresponding to the thickness is transferred to the first hard mask, and the organic low dielectric constant is transferred. Etching the insulating film to a thickness by using the film as a mask to form a connection hole in the insulating film; and using the first and second hard masks as a mask to form a thickness in the organic low dielectric constant film A step of forming a wiring groove in the organic low dielectric constant film, a step of removing the second hard mask by etching, and a step of embedding a conductor in the wiring groove and the connection hole It is characterized by having.
[0029]
Alternatively, in the method for manufacturing a semiconductor device of the present invention, a step of sequentially stacking an organic low dielectric constant film, a first hard mask, and a second hard mask on a lower wiring, and on the second hard mask, Forming a first resist having an opening with a connection hole pattern; etching the second hard mask by a thickness using the first resist as a mask; and further etching the first hard mask halfway Etching to the upper surface side of the first hard mask and the second hard mask, transferring the connection hole pattern to the second hard mask, removing the first resist, and on the second hard mask Forming a second resist having an opening with a wiring groove pattern including the connection hole pattern; and using the second resist as a mask to form a thickness on the second hard mask Etching, transferring the wiring groove pattern to the second hard mask, removing the second resist, and using the second hard mask as a mask, the thickness of the first hard mask is increased. Etching less than that, transferring the wiring groove pattern to the upper surface side of the first hard mask, and removing the first hard mask in the portion where the connection hole pattern is transferred; Etching less than the thickness of the organic low dielectric constant film by using the first hard mask as a mask, and transferring the connection hole pattern to the upper surface side of the organic low dielectric constant film; Etching the first hard mask using a hard mask as a mask, and transferring the wiring groove pattern corresponding to the thickness to the first hard mask; And using the second hard mask as a mask, the organic low dielectric constant film is etched less than the thickness to form a wiring groove on the upper surface side of the organic low dielectric constant film, and the connection hole pattern is transferred Removing the organic low dielectric constant film in the formed portion, forming a connection hole on the bottom side of the organic low dielectric constant film, removing the second hard mask by etching, and the wiring And a step of embedding a conductor in the groove and the connection hole.
[0030]
Alternatively, in the method for manufacturing a semiconductor device of the present invention, the first organic low dielectric constant film, the insulating film, the second organic low dielectric constant film, the first hard mask, and the second hard mask are formed on the lower layer wiring. Sequentially forming a layer, a step of forming a first resist having an opening with a connection hole pattern on the second hard mask, and a thickness of the second hard mask using the first resist as a mask. Etching for a certain amount, further etching the first hard mask halfway, and transferring a connection hole pattern to the upper surface side of the first hard mask and the second hard mask; Removing the resist, forming a second resist having an opening with a wiring groove pattern including the connection hole pattern on the second hard mask, and masking the second resist. Etching the second hard mask to a thickness, transferring the wiring groove pattern to the second hard mask, removing the second resist, and the second hard mask. Etching less than the thickness of the first hard mask using the mask as a mask, transferring the wiring groove pattern to the upper surface side of the first hard mask, and the portion of the portion where the connection hole pattern is transferred Removing the first hard mask; and etching the second organic low dielectric constant film by a thickness using the first hard mask as a mask to form the second organic low dielectric constant film Transferring the connection hole pattern; etching the first hard mask using the second hard mask as a mask; and forming the wiring groove pattern corresponding to a thickness on the first hard mask. And transferring the connection hole pattern to the insulating film by etching the insulating film for a thickness using the second organic low dielectric constant film as a mask; and Using the second hard mask as a mask, the second organic low dielectric constant film is etched by a thickness to form a wiring groove in the second organic low dielectric constant film, and the insulating film is masked. Etching the thickness of the first organic low dielectric constant film to form a connection hole in the first organic low dielectric constant film, and removing the second hard mask by etching. And a step of embedding a conductor in the wiring groove and the connection hole.
[0031]
Thereby, in the formation of the dual damascene wiring, the alignment of the connection hole pattern can be performed by direct alignment with the wiring groove pattern. Therefore, the amount of misalignment can be reduced as compared with the conventional method in which the lower layer wiring is used for alignment and the wiring groove pattern and the connection hole pattern are double-indirectly aligned. As a result, the product yield is increased and the production cost can be suppressed. Further, the semiconductor device can be further highly integrated.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.
(Embodiment 1)
A method for forming the Cu dual damascene wiring of the present embodiment will be described with reference to FIGS. First, as shown in FIG. 1A, a silicon nitride film 2 is formed as a barrier insulating film on the lower wiring 1 with a thickness of 50 nm, for example. The silicon nitride film 2 prevents Cu diffusion.
[0033]
A silicon oxide film 3 is formed on the silicon nitride film 2 as a connection layer insulating film with a thickness of, for example, 500 nm. In the silicon oxide film 3, connection holes for connecting the wirings are formed. As the silicon oxide film 3, NSG, PSG, BPSG having a relative dielectric constant of about 4.0, FSG having a relative dielectric constant of about 3.5, or the like is used.
[0034]
An organic film 4 is formed on the silicon oxide film 3 as a wiring layer insulating film, for example, with a thickness of 400 nm. A wiring groove is formed in the organic film 4, and Cu wiring is embedded in the wiring groove. As the organic film 4, SiLK (trade name, manufactured by Dow Chemical Co., USA) or FLARE (trade name, manufactured by US Allied Signal), which is a PAE material having a relative dielectric constant of about 2.7, is used. These organic films are generally made of SiO. ₂ Since the dielectric constant is low compared to the above, the parasitic capacitance of the wiring can be reduced.
[0035]
The organic film in the embodiment of the present invention refers to a film made of all organic materials that are eroded by oxygen plasma, an organic resist stripping solution, or the like during resist stripping. Accordingly, not only a film mainly composed of an organic polymer but also a fluororesin, a silica-based material containing an organic component, porous silica, and the like are included in the organic film.
The material of the organic film 4 is applied by, for example, a spin coating method.
[0036]
A silicon oxide film 5 is formed on the organic film 4 as a first hard mask with a thickness of 200 nm, for example. The silicon oxide film 5 can be formed by, for example, a parallel plate plasma CVD method using silane gas as a raw material.
A silicon nitride film 6 is formed as a second hard mask on the silicon oxide film 5 with a thickness of, for example, 100 nm. The silicon nitride film 6 can be formed by, for example, a parallel plate plasma CVD method using silane gas as a raw material.
[0037]
A silicon oxide film 7 is formed on the silicon nitride film 6 as a third hard mask with a thickness of 200 nm, for example. The silicon oxide film 7 can be formed in the same manner as the silicon oxide film 5.
A silicon nitride film 8 is formed as a fourth hard mask on the silicon oxide film 7 with a thickness of, for example, 100 nm. The silicon nitride film 8 can be formed in the same manner as the silicon nitride film 6. The combination of hard mask materials may be changed to other examples.
[0038]
Next, as shown in FIG. 1B, a resist 9 having a connection hole pattern is formed by lithography. At this time, the lower layer wiring 1 is used for alignment. Lithography is, for example, photolithography using a KrF laser, and the numerical aperture NA is, for example, 0.60.
[0039]
Next, as shown in FIG. 2C, the silicon nitride film 8, the silicon oxide film 7 and the silicon nitride film 6 are sequentially etched using the resist 9 as a mask, and connection hole patterns are formed on the second to fourth hard masks. Transcript. Thereafter, the resist 9 is removed.
[0040]
Etching of the silicon nitride films 6 and 8 is, for example, CHF _Three / O ₂ / Parallel plate plasma etching using Ar gas as etching gas. Etching of the silicon oxide film 7 is performed by, for example, C _Five F ₈ Parallel plate plasma etching using / CO / Ar gas as an etching gas is performed. In the step of removing the resist 9, the organic film 4 is protected by the first to fourth hard masks.
[0041]
Next, as shown in FIG. 2D, a wiring groove pattern resist 10 is formed by lithography. At this time, the connection hole pattern transferred to the second to fourth hard masks is used for alignment. Since this alignment is direct alignment, the amount of misalignment can be greatly reduced compared to indirect alignment by the conventional method.
[0042]
Next, as shown in FIG. 3E, the silicon nitride film 8 is etched using the resist 10 as a mask to transfer the wiring groove pattern to the fourth hard mask. Thereafter, the resist 10 is removed. Etching of the silicon nitride film 8 can be performed in the same manner as when the connection hole pattern is formed in the step shown in FIG. In the step of removing the resist 10, the organic film 4 is protected by the first to fourth hard masks.
[0043]
Next, as shown in FIG. 3F, the silicon oxide films 5 and 7 are etched by a thickness (200 nm). Thereby, the connection hole pattern is transferred to the silicon oxide film 5 which is the first hard mask. Further, the wiring groove pattern formed in the fourth hard mask (silicon nitride film 8) is transferred to the silicon oxide film 7 which is the third hard mask.
[0044]
Next, as shown in FIG. 4G, the organic film 4 which is a wiring layer insulating film is etched to form a first hard mask (silicon oxide film 5) and a second hard mask (silicon nitride film 6). The connection hole pattern formed on the substrate is transferred. The organic film 4 is etched by ECR (electron cyclotron resonance) plasma etching using ammonia gas as an etching gas, for example.
[0045]
Next, as shown in FIG. 4H, the silicon nitride film 8 which is the fourth hard mask is removed by etching. At the same time, the silicon nitride film 6 as the second hard mask is etched using the third hard mask (silicon oxide film 7) as a mask, and the wiring groove pattern is transferred to the second hard mask.
[0046]
In the step shown in FIG. 4G, instead of etching only the thickness of the organic film 4, as shown in FIG. 5G ′, etching is performed halfway through the silicon oxide film 3 which is the connection layer insulating film. Alternatively, the connection hole part 11a may be formed. Also in this case, next, as shown in FIG. 5H ′, the silicon nitride films 6 and 8 are etched to remove the silicon nitride film 8, and at the same time, transfer the wiring groove pattern to the silicon nitride film 6. To do.
[0047]
Alternatively, the order of the etching process of the organic film 4 shown in FIG. 4G and the etching process of the silicon nitride films 6 and 8 shown in FIG. In this case, first, as shown in FIG. 6G ″, the silicon nitride films 6 and 8 are etched to remove the silicon nitride film 8 and at the same time, transfer the wiring groove pattern to the silicon nitride film 6. 6H, the organic film 4 is etched using the silicon oxide film 5 as the first hard mask as a mask to transfer the connection hole pattern to the organic film 4. Then, as shown in FIG.
[0048]
After any of the steps shown in FIG. 4H, FIG. 5H ′, or FIG. 6H ″, the silicon oxide films 3, 5, and 7 are etched as shown in FIG. 7I. As a result, the silicon oxide film 7 as the third hard mask is removed, and the first hard mask (silicon oxide film 5) is etched using the second hard mask (silicon nitride film 6) as a mask. Thus, the wiring groove pattern is transferred to the silicon oxide film 5. Further, the silicon oxide film 3 which is the connection layer insulating film is etched using the organic film 4 as a mask, whereby the connection hole 11 is formed in the silicon oxide film 3. It is formed.
[0049]
Next, as shown in FIG. 7J, the organic film 4 is etched using the first and second hard masks (silicon oxide film 5 and silicon nitride film 6) as a mask. Thereby, the wiring trench 12 is formed in the organic film.
Next, as shown in FIG. 7K, the silicon nitride films 2 and 6 are etched. Thereby, the silicon nitride film 6 is removed, and at the same time, a connection hole is formed in the silicon nitride film 2 which is a barrier insulating film.
[0050]
Through the above steps, the wiring trench 12 and the connection hole 11 are formed. Thereafter, a Cu layer is formed so as to fill the wiring trench 12 and the connection hole 11, and then, for example, CMP is performed to remove an extra Cu layer on the insulating film, and the surface is planarized. Damascene wiring is formed.
[0051]
According to the manufacturing method of the semiconductor device of the present embodiment, since the wiring groove pattern is transferred after the connection hole pattern is transferred, the wiring groove pattern can be directly aligned with the connection hole pattern. is there. Therefore, the amount of misalignment can be reduced as compared with the conventional method in which alignment is performed by indirect alignment using lower layer wiring. As a result, even when the connection hole is formed in a fine wiring having a narrow wiring interval, a short circuit failure is prevented and the product yield is improved.
[0052]
In addition, since the misalignment amount can be suppressed without performing the lithography process again, the production cost can be reduced.
According to the manufacturing method of the semiconductor device of this embodiment, it is possible to form finer wiring without reducing the short margin. Therefore, it is possible to further integrate the semiconductor device.
[0053]
(Embodiment 2)
A method for forming the Cu dual damascene wiring of the present embodiment will be described with reference to FIGS. First, as shown in FIG. 8A, a silicon nitride film 2 is formed as a barrier insulating film on the lower wiring 1 with a thickness of, for example, 50 nm. The silicon nitride film 2 prevents Cu diffusion.
[0054]
A silicon oxide film 3 is formed on the silicon nitride film 2 as a connection layer insulating film with a thickness of, for example, 500 nm. An organic film 4 is formed on the silicon oxide film 3 as a wiring layer insulating film, for example, with a thickness of 400 nm. The silicon oxide film 3 and the organic film 4 can be formed by using the same material as in the first embodiment and the same method as in the first embodiment.
[0055]
A silicon oxide film 5 is formed on the organic film 4 as a first hard mask with a thickness of 200 nm, for example. A silicon nitride film 6 is formed as a second hard mask on the silicon oxide film 5 with a thickness of, for example, 100 nm. The silicon oxide film 5 and the silicon nitride film 6 can be formed by the same method as in the first embodiment.
[0056]
Next, as shown in FIG. 8B, a resist 9 having a connection hole pattern is formed by lithography. At this time, the lower layer wiring 1 is used for alignment. Lithography can be performed in the same manner as in the first embodiment.
[0057]
Next, as shown in FIG. 9C, the silicon nitride film 6 is etched by a thickness (100 nm) using the resist 9 as a mask. Further, the silicon oxide film 5 as the first hard mask is partially etched (so as not to reach the organic film 4), for example, by etching for a thickness of 100 nm, and the connection hole pattern is transferred to the silicon oxide film 5. Etching of the silicon nitride film 6 and the silicon oxide film 5 can be performed by the same method as in the first embodiment. Thereafter, the resist 9 is removed. In the step of removing the resist 9, the organic film 4 is protected by the first and second hard masks.
[0058]
Next, as shown in FIG. 9D, a wiring groove pattern resist 10 is formed by lithography. At this time, the connection hole pattern transferred to the first and second hard masks is used for alignment. Since this alignment is direct alignment, the amount of misalignment can be greatly reduced compared to indirect alignment by the conventional method.
[0059]
Next, as shown in FIG. 9E, the silicon nitride film 6 is etched using the resist 10 as a mask, and the wiring groove pattern is transferred to the second hard mask. Thereafter, the resist 10 is removed. Etching of the silicon nitride film 6 can be performed in the same manner as in the case of forming the connection hole pattern in the step shown in FIG. In the removal process of the resist 10, the organic film 4 is protected by the first and second hard masks.
[0060]
Next, as shown in FIG. 10F, the silicon oxide film 5 is etched until the connection hole pattern formed in the silicon oxide film 5 reaches the organic film 4. When the silicon oxide film 5 is etched by a thickness of 100 nm in the step shown in FIG. 9C, the connection hole pattern is formed by performing the etching by a thickness of 100 nm in the step shown in FIG. The organic film 4 is reached.
[0061]
At this time, the silicon oxide film 5 is etched using the silicon nitride film 6 as the second hard mask as a mask, and the wiring groove pattern is transferred. Except for the portion included in the connection hole pattern, the silicon oxide film 5 having a thickness of 100 nm is left in the portion of the wiring trench pattern. The etching amount of the silicon oxide film 5 in the step shown in FIG. 10F is adjusted according to the etching amount of the silicon oxide film 5 in the step shown in FIG. Do not reach.
[0062]
Next, as shown in FIG. 10G, the organic film 4 which is a wiring layer insulating film is etched to form a first hard mask (silicon oxide film 5) and a second hard mask (silicon nitride film 6). The connection hole pattern formed on the substrate is transferred. Etching of the organic film 4 can be performed in the same manner as in the first embodiment.
[0063]
Next, as shown in FIG. 10H, using the organic film 4 as a mask, the silicon oxide film 3 which is the connection layer insulating film is etched by a thickness (500 nm), and the connection hole 11 is formed in the silicon oxide film 3. Form. At this time, the silicon oxide film 5 is etched using the silicon nitride film 6 as a mask, and the wiring groove pattern is transferred to the first hard mask.
[0064]
Next, as shown in FIG. 11I, the organic film 4 is etched using the first and second hard masks (silicon oxide film 5 and silicon nitride film 6) as a mask. As a result, the wiring trench 12 is formed in the organic film 4.
[0065]
Next, as shown in FIG. 11J, the silicon nitride films 2 and 6 are etched. Thereby, the silicon nitride film 6 is removed, and at the same time, a connection hole is formed in the silicon nitride film 2 which is a barrier insulating film. Thereafter, Cu is embedded in the wiring groove 12 and the connection hole 11 as in the first embodiment, thereby forming a Cu dual damascene wiring.
[0066]
According to the semiconductor device manufacturing method of the present embodiment, the wiring groove pattern can be aligned by direct alignment with the connection hole pattern as in the first embodiment. Therefore, the misalignment amount is reduced. Thereby, the product yield can be improved and the production cost can be reduced. In addition, the semiconductor device can be more highly integrated.
[0067]
(Embodiment 3)
In the first and second embodiments, the wiring trench 12 is formed using the silicon oxide film 3 as an etching stopper layer. On the other hand, in the present embodiment, both the wiring groove and the connection hole are formed in the single-layer low dielectric constant film by adjusting the etching amount without providing a layer serving as an etching stopper for the wiring groove.
[0068]
Hereinafter, a method for forming the Cu dual damascene wiring of the present embodiment will be described with reference to FIGS. First, as shown in FIG. 12A, a silicon nitride film 2 is formed as a barrier insulating film on the lower wiring 1 with a thickness of, for example, 50 nm. The silicon nitride film 2 prevents Cu diffusion.
[0069]
An organic film 13 is formed on the silicon nitride film 2 with a thickness of, for example, 900 nm. The organic film 13 can be formed by the same method as in the first embodiment, using the same material as that of the organic film 4 in the first embodiment.
[0070]
A silicon oxide film 5 is formed on the organic film 13 as a first hard mask with a thickness of 200 nm, for example. A silicon nitride film 6 is formed as a second hard mask on the silicon oxide film 5 with a thickness of, for example, 100 nm. The silicon oxide film 5 and the silicon nitride film 6 can be formed by the same method as in the first embodiment.
[0071]
Next, as shown in FIG. 12B, a resist 9 having a connection hole pattern is formed by lithography. At this time, the lower layer wiring 1 is used for alignment. Lithography can be performed in the same manner as in the first embodiment.
[0072]
Next, as shown in FIG. 13C, the silicon nitride film 6 is etched by a thickness (100 nm) using the resist 9 as a mask. Furthermore, the silicon oxide film 5 as the first hard mask is partially etched (so as not to reach the organic film 13), for example, by etching for a thickness of 100 nm, and the connection hole pattern is transferred to the silicon oxide film 5. Etching of the silicon nitride film 6 and the silicon oxide film 5 can be performed by the same method as in the first embodiment. Thereafter, the resist 9 is removed. In the step of removing the resist 9, the organic film 13 is protected by the first and second hard masks.
[0073]
Next, as shown in FIG. 13D, a wiring groove pattern resist 10 is formed by lithography. At this time, the connection hole pattern transferred to the first and second hard masks is used for alignment. Since this alignment is direct alignment, the amount of misalignment can be greatly reduced compared to indirect alignment by the conventional method.
[0074]
Next, as shown in FIG. 13E, the silicon nitride film 6 is etched using the resist 10 as a mask to transfer the wiring groove pattern to the second hard mask. Thereafter, the resist 10 is removed. In the step of removing the resist 10, the organic film 13 is protected by the first and second hard masks.
[0075]
Next, as shown in FIG. 14F, the silicon oxide film 5 is etched until the connection hole pattern formed in the silicon oxide film 5 reaches the organic film 13. When the silicon oxide film 5 is etched by a thickness of 100 nm in the step shown in FIG. 13C, the connection hole pattern is formed by performing the etching by a thickness of 100 nm in the step shown in FIG. The organic film 13 is reached.
[0076]
At this time, the silicon oxide film 5 is etched using the silicon nitride film 6 as the second hard mask as a mask, and the wiring groove pattern is transferred. Except for the portion included in the connection hole pattern, the silicon oxide film 5 having a thickness of 100 nm is left in the portion of the wiring trench pattern. In the step shown in FIG. 14F, the etching amount of the silicon oxide film 5 is adjusted to prevent the wiring groove pattern from reaching the organic film 13 as in the second embodiment.
[0077]
Next, as shown in FIG. 14G, the organic film 13 is etched to transfer the connection hole pattern formed in the first hard mask (silicon oxide film 5). Here, the organic film 13 having a certain thickness is left on the barrier insulating film (silicon nitride film 2) without etching the thickness of the organic film 13 (900 nm). The thickness of the organic film 13 left in the connection hole portion is made smaller than the depth of the wiring groove formed in the organic film 13 in the subsequent process. Etching of the organic film 13 can be performed similarly to the etching of the organic film 4 in the first embodiment.
[0078]
Next, as shown in FIG. 14H, the first hard mask (silicon oxide film 5) is etched using the second hard mask (silicon nitride film 6) as a mask, and the first hard mask is wired. Transfer the groove pattern.
[0079]
Next, as shown in FIG. 15I, the organic film 13 is etched using the first and second hard masks (silicon oxide film 5 and silicon nitride film 6) as a mask. As a result, a wiring groove 14 is formed in the organic film 13. Further, the organic film 13 in the connection hole pattern portion is further etched using the silicon nitride film 2 as an etching stopper layer. Thereby, the connection hole 15 is formed in the organic film 13.
[0080]
Next, as shown in FIG. 15J, the silicon nitride films 2 and 6 are etched. Thereby, the silicon nitride film 6 is removed, and at the same time, a connection hole is formed in the silicon nitride film 2 which is a barrier insulating film. Thereafter, Cu is embedded in the wiring groove 14 and the connection hole 15 in the same manner as in the first embodiment to form a Cu dual damascene wiring.
[0081]
According to the semiconductor device manufacturing method of the present embodiment, the wiring groove pattern can be aligned by direct alignment with the connection hole pattern as in the first embodiment. Therefore, the misalignment amount is reduced. Thereby, the product yield can be improved and the production cost can be reduced. In addition, the semiconductor device can be more highly integrated.
[0082]
(Embodiment 4)
In the third embodiment, the wiring groove and the connection hole are formed in the single-layer low dielectric constant film by adjusting the etching amount. On the other hand, in this embodiment, an etching stopper layer is provided between two low dielectric constant films, a wiring groove is formed in the low dielectric constant film on the etching stopper layer, and a connection hole is formed in the lower low dielectric constant film. Form.
[0083]
Hereinafter, a method for forming the Cu dual damascene wiring of the present embodiment will be described with reference to FIGS. First, as shown in FIG. 16A, a silicon nitride film 2 is formed as a barrier insulating film on the lower wiring 1 with a thickness of, for example, 50 nm. The silicon nitride film 2 prevents Cu diffusion. A lower organic film 16 is formed on the silicon nitride film 2 with a thickness of, for example, 400 nm.
[0084]
A silicon oxide film 17 is formed on the lower organic film 16 as an etching stopper layer, for example, with a thickness of 100 nm. An upper organic film 18 is formed on the silicon oxide film 17 with a thickness of, for example, 400 nm. The lower organic film 16 and the upper organic film 18 can be formed by the same method as in the first embodiment, using the same material as that of the organic film 4 in the first embodiment.
[0085]
A silicon oxide film 5 is formed on the upper organic film 18 as a first hard mask with a thickness of 200 nm, for example. A silicon nitride film 6 is formed as a second hard mask on the silicon oxide film 5 with a thickness of, for example, 100 nm. The silicon oxide film 5 and the silicon nitride film 6 can be formed by the same method as in the first embodiment.
[0086]
Next, as shown in FIG. 16B, a resist 9 having a connection hole pattern is formed by lithography. At this time, the lower layer wiring 1 is used for alignment. Lithography can be performed in the same manner as in the first embodiment.
[0087]
Next, as shown in FIG. 17C, the silicon nitride film 6 is etched by a thickness (100 nm) using the resist 9 as a mask. Further, the silicon oxide film 5 as the first hard mask is partially etched (so as not to reach the upper organic film 18), for example, by etching for a thickness of 100 nm, and the connection hole pattern is transferred to the silicon oxide film 5.
[0088]
Etching of the silicon nitride film 6 and the silicon oxide film 5 can be performed by the same method as in the first embodiment. Thereafter, the resist 9 is removed. In the step of removing the resist 9, the upper organic film 18 is protected by the first and second hard masks.
[0089]
Next, as shown in FIG. 17D, a wiring groove pattern resist 10 is formed by lithography. At this time, the connection hole pattern transferred to the first and second hard masks is used for alignment. Since this alignment is direct alignment, the amount of misalignment can be greatly reduced compared to indirect alignment by the conventional method.
[0090]
Next, as shown in FIG. 17E, the silicon nitride film 6 is etched using the resist 10 as a mask to transfer the wiring groove pattern to the second hard mask. Thereafter, the resist 10 is removed. In the step of removing the resist 10, the upper organic film 18 is protected by the first and second hard masks.
[0091]
Next, as shown in FIG. 18F, the silicon oxide film 5 is etched until the connection hole pattern formed in the silicon oxide film 5 reaches the upper organic film 18. When the silicon oxide film 5 is etched by a thickness of 100 nm in the step shown in FIG. 17C, the connection hole pattern is formed by performing the etching by a thickness of 100 nm in the step shown in FIG. It reaches the upper organic film 18.
[0092]
At this time, the silicon oxide film 5 is etched using the silicon nitride film 6 as the second hard mask as a mask, and the wiring groove pattern is transferred. Except for the portion included in the connection hole pattern, the silicon oxide film 5 having a thickness of 100 nm is left in the portion of the wiring trench pattern. In the step shown in FIG. 18F, as in the second embodiment, the etching amount of the silicon oxide film 5 is adjusted so that the wiring groove pattern does not reach the upper organic film 18.
[0093]
Next, as shown in FIG. 18G, the upper organic film 18 is etched to transfer the connection hole pattern formed in the first hard mask (silicon oxide film 5). At this time, the silicon oxide film 17 is used as an etching stopper layer. Etching of the upper organic film 18 can be performed in the same manner as the etching of the organic film 4 in the first embodiment.
[0094]
Next, as shown in FIG. 18H, the first hard mask (silicon oxide film 5) is etched using the second hard mask (silicon nitride film 6) as a mask, and the first hard mask is wired. Transfer the groove pattern. At this time, the silicon oxide film 17 is etched using the upper organic film 18 as a mask, and a part 19 a of the connection hole is formed in the silicon oxide film 17.
[0095]
Next, as shown in FIG. 19 (i), the upper organic film 18 is etched using the first and second hard masks (silicon oxide film 5 and silicon nitride film 6) as a mask. As a result, a wiring groove 20 is formed in the upper organic film 18. At this time, the lower organic film 16 is etched using the silicon oxide film 17 as a mask. Thereby, a connection hole 19 is formed in the lower organic film 16.
[0096]
Next, as shown in FIG. 19J, the silicon nitride films 2 and 6 are etched. Thereby, the silicon nitride film 6 is removed, and at the same time, a connection hole is formed in the silicon nitride film 2 which is a barrier insulating film. Thereafter, Cu is embedded in the wiring groove 20 and the connection hole 19 in the same manner as in the first embodiment to form a Cu dual damascene wiring.
[0097]
According to the semiconductor device manufacturing method of the present embodiment, the wiring groove pattern can be aligned by direct alignment with the connection hole pattern as in the first embodiment. Therefore, the misalignment amount is reduced. Thereby, the product yield can be improved and the production cost can be reduced. In addition, the semiconductor device can be more highly integrated.
[0098]
Embodiments of the semiconductor device manufacturing method of the present invention are not limited to the above description. For example, the insulating film material can be changed as long as it is a material to which the above process can be applied. In addition, various modifications can be made without departing from the scope of the present invention.
[0099]
【The invention's effect】
According to the method for manufacturing a semiconductor device of the present invention, the organic low dielectric constant film is not damaged when the resist is peeled off, and the alignment accuracy between the wiring groove and the connection hole is improved.
[Brief description of the drawings]
FIGS. 1A and 1B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
2 (c) and 2 (d) are cross-sectional views showing the manufacturing process of the semiconductor device manufacturing method according to the first embodiment of the present invention, showing the process following FIG. 1 (b).
FIGS. 3E and 3F are cross-sectional views showing the manufacturing process of the semiconductor device manufacturing method according to the first embodiment of the present invention, and show the process following FIG.
4 (g) and 4 (h) are cross-sectional views showing a manufacturing process of the method for manufacturing a semiconductor device according to the first embodiment of the present invention, showing a process following FIG. 3 (f).
FIGS. 5 (g ′) and 5 (h ′) are cross-sectional views showing the manufacturing steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention, and are modifications of FIGS. 4 (g) and (h). It is an example.
6 (g ″) and FIG. 6 (h ″) are cross-sectional views illustrating manufacturing steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention, and are modifications of FIGS. 4 (g) and (h). It is an example.
7 (i) to 7 (k) are cross-sectional views showing the manufacturing process of the method for manufacturing a semiconductor device according to the first embodiment of the present invention, and FIG. 4 (h), FIG. 5 (h ′) or FIG. The process following any one of FIG.6 (h '') is shown.
FIGS. 8A and 8B are cross-sectional views illustrating manufacturing steps of a method of manufacturing a semiconductor device according to the second embodiment of the present invention.
FIGS. 9C to 9E are cross-sectional views showing the manufacturing process of the method for manufacturing a semiconductor device according to the second embodiment of the present invention, showing the process following FIG. 8B.
FIGS. 10F to 10H are cross-sectional views illustrating manufacturing steps of the method for manufacturing a semiconductor device according to the second embodiment of the present invention, showing the steps following FIG.
FIGS. 11 (i) and 11 (j) are cross-sectional views showing the manufacturing process of the semiconductor device manufacturing method according to the second embodiment of the present invention, showing the process following FIG. 10 (h).
FIGS. 12A and 12B are cross-sectional views illustrating manufacturing steps of a method of manufacturing a semiconductor device according to the third embodiment of the present invention.
FIGS. 13C to 13E are cross-sectional views showing the manufacturing process of the method for manufacturing a semiconductor device according to the third embodiment of the present invention, showing the process following FIG. 12B.
14 (f) to 14 (h) are cross-sectional views showing the manufacturing process of the semiconductor device manufacturing method according to the third embodiment of the present invention, showing the process following FIG. 13 (e).
FIGS. 15 (i) and 15 (j) are cross-sectional views showing the manufacturing process of the semiconductor device manufacturing method according to the third embodiment of the present invention, showing the process following FIG. 14 (h).
FIGS. 16A and 16B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.
FIGS. 17C to 17E are cross-sectional views illustrating manufacturing steps of the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention, showing the steps following FIG.
18 (f) to 18 (h) are cross-sectional views showing the manufacturing process of the semiconductor device manufacturing method according to the fourth embodiment of the present invention, showing the process following FIG. 17 (e).
FIGS. 19 (i) and 19 (j) are cross-sectional views showing the manufacturing process of the semiconductor device manufacturing method according to the fourth embodiment of the present invention, showing the process following FIG. 18 (h).
20 (a) to 20 (c) are cross-sectional views showing manufacturing steps of a conventional method for manufacturing a semiconductor device.
21 (d) to 21 (f) are cross-sectional views showing manufacturing steps of a conventional method for manufacturing a semiconductor device, showing steps following FIG. 20 (c).
22 (g) to 22 (i) are cross-sectional views showing a manufacturing process of a conventional method for manufacturing a semiconductor device, showing a process following FIG. 21 (f).
FIGS. 23A and 23B are diagrams for explaining the relationship between the misalignment amount and the inter-wire short margin. FIGS.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Lower layer wiring, 2 ... Silicon nitride film, 3 ... Silicon oxide film, 4 ... Organic film, 5 ... Silicon oxide film, 6 ... Silicon nitride film, 7 ... Silicon oxide film, 8 ... Silicon nitride film, 9, 10 ... Resist, 11 ... connection hole, 12 ... wiring groove, 13 ... organic film, 14 ... wiring groove, 15 ... connection hole, 16 ... lower organic film, 17 ... silicon oxide film, 18 ... upper organic film, 19 ... connection hole, DESCRIPTION OF SYMBOLS 20 ... Wiring groove, 101 ... Lower layer wiring, 102 ... Silicon nitride film, 103 ... Silicon oxide film, 104 ... Organic film, 105 ... Silicon oxide film, 106 ... Silicon nitride film, 107, 108 ... Resist, 109 ... Connection hole, 110: wiring groove, 111: wiring, 112: connection hole.

Claims (10)

Forming an insulating film on the lower layer wiring;
Forming an organic low dielectric constant film having a different etching rate from the insulating film on the insulating film;
Forming a first hard mask on the organic low dielectric constant film, which is different in etching rate from the organic low dielectric constant film and is etched under the same conditions as the insulating film;
Forming a second hard mask having an etching rate different from any of the insulating film, the organic low dielectric constant film, and the first hard mask on the first hard mask;
On the second hard mask, a third hard mask having an etching rate different from that of the organic low dielectric constant film and the second hard mask and etched under the same conditions as the insulating film and the first hard mask is provided. Forming, and
On the third hard mask, the insulating film, the organic low dielectric constant film, and the first and third hard masks have different etching rates, and are etched under the same conditions as the second hard mask. 4 forming a hard mask;
Forming a first resist having an opening with a connection hole pattern on the fourth hard mask;
Etching the thickness of each of the fourth, third, and second hard masks in turn using the first resist as a mask, and transferring a connection hole pattern to the second to fourth hard masks;
Removing the first resist;
Forming a second resist having an opening with a wiring groove pattern including the connection hole pattern on the fourth hard mask;
Etching the thickness of the fourth hard mask using the second resist as a mask, transferring the wiring groove pattern to the fourth hard mask, and removing the second resist ,
Etching for a thickness is performed on the third hard mask using the fourth hard mask as a mask, the wiring groove pattern is transferred to the third hard mask, and the second hard mask is used as the mask. Etching the thickness of the first hard mask, and transferring the connection hole pattern to the first hard mask;
Etching the organic low dielectric constant film for a thickness using the first and second hard masks as a mask, and transferring the connection hole pattern to the organic low dielectric constant film; and
The fourth hard mask is removed by etching, the second hard mask is etched by a thickness using the third hard mask as a mask, and the wiring groove pattern is transferred to the second hard mask. And the process of
The third hard mask is removed by etching, the first hard mask is etched to a thickness using the second hard mask as a mask, and the wiring groove pattern is transferred to the first hard mask. And etching the thickness of the insulating film using the organic low dielectric constant film as a mask to form a connection hole in the insulating film;
Etching the thickness of the organic low dielectric constant film using the first and second hard masks as a mask to form a wiring groove in the organic low dielectric constant film; and
Removing the second hard mask by etching;
A method of manufacturing a semiconductor device, comprising: embedding a conductor in the wiring groove and the connection hole. After transferring the connection hole pattern to the organic low dielectric constant film and before etching the second and fourth hard masks, the first and second hard masks and the organic low dielectric constant film The method for manufacturing a semiconductor device according to claim 1, further comprising a step of etching the insulating film halfway using the mask as a mask. Before transferring the connection hole pattern to the organic low dielectric constant film, the fourth hard mask is removed by etching, and the third hard mask is used as a mask for the thickness of the second hard mask. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the wiring groove pattern is transferred to the second hard mask by performing an etching process. Before forming the insulating film on the lower layer wiring, a barrier insulating film having an etching rate different from that of the insulating film on the lower layer wiring and etched under the same conditions as the second hard mask, Further comprising the step of forming the barrier insulating film for preventing the diffusion of the wiring material;
After the wiring trench is formed, the second hard mask is removed by etching, and the barrier insulating film is etched by a thickness using the insulating film as a mask to remove the barrier insulating film at the bottom of the connection hole. A method for manufacturing a semiconductor device according to claim 1. Forming an insulating film on the lower layer wiring;
Forming an organic low dielectric constant film having a different etching rate from the insulating film on the insulating film;
On the organic low dielectric constant film, a step of forming a first hard mask having an etching rate different from that of the organic low dielectric constant film and etched under the same conditions as the insulating film;
Forming a second hard mask having an etching rate different from any of the insulating film, the organic low dielectric constant film, and the first hard mask on the first hard mask;
Forming a first resist having an opening with a connection hole pattern on the second hard mask;
Using the first resist as a mask, the second hard mask is etched for a thickness, and further, the first hard mask is etched halfway, and the upper surface side of the first hard mask and the second hard mask are etched. Transferring the connection hole pattern to the hard mask;
Removing the first resist;
Forming a second resist having an opening with a wiring groove pattern including the connection hole pattern on the second hard mask;
Etching the second hard mask with a thickness using the second resist as a mask, and transferring the wiring groove pattern to the second hard mask;
Removing the second resist;
Etching less than the thickness of the first hard mask using the second hard mask as a mask, transferring the wiring groove pattern to the upper surface side of the first hard mask, and transferring the connection hole pattern Removing the first hard mask of the formed portion;
Etching a thickness of the organic low dielectric constant film using the first hard mask as a mask to transfer the connection hole pattern to the organic low dielectric constant film; and Etching is performed on the first hard mask as a mask, the wiring groove pattern corresponding to the thickness is transferred to the first hard mask, and the thickness of the insulating film is increased by using the organic low dielectric constant film as a mask Etching to form a connection hole in the insulating film;
Etching the thickness of the organic low dielectric constant film using the first and second hard masks as a mask to form a wiring groove in the organic low dielectric constant film; and
Removing the second hard mask by etching;
A method of manufacturing a semiconductor device, comprising: embedding a conductor in the wiring groove and the connection hole. Before forming the insulating film on the lower layer wiring, a barrier insulating film having an etching rate different from that of the insulating film on the lower layer wiring and etched under the same conditions as the second hard mask, Further comprising the step of forming the barrier insulating film for preventing the diffusion of the wiring material;
After the wiring trench is formed, the second hard mask is removed by etching, and the barrier insulating film is etched by a thickness using the insulating film as a mask to remove the barrier insulating film at the bottom of the connection hole. A method for manufacturing a semiconductor device according to claim 5. Forming an organic low dielectric constant film on the lower wiring; and
Forming a first hard mask having an etching rate different from that of the organic low dielectric constant film on the organic low dielectric constant film;
Forming a second hard mask having a different etching rate from the organic low dielectric constant film and the first hard mask on the first hard mask; and
Forming a first resist having an opening with a connection hole pattern on the second hard mask;
Using the first resist as a mask, the second hard mask is etched for a thickness, and further, the first hard mask is etched halfway, and the upper surface side of the first hard mask and the second hard mask are etched. Transferring the connection hole pattern to the hard mask;
Removing the first resist;
Forming a second resist having an opening with a wiring groove pattern including the connection hole pattern on the second hard mask;
Etching the second hard mask with a thickness using the second resist as a mask, and transferring the wiring groove pattern to the second hard mask;
Removing the second resist;
Etching less than the thickness of the first hard mask using the second hard mask as a mask, transferring the wiring groove pattern to the upper surface side of the first hard mask, and transferring the connection hole pattern Removing the first hard mask of the formed portion;
Etching the organic low dielectric constant film less than the thickness using the first hard mask as a mask, and transferring the connection hole pattern to the upper surface side of the organic low dielectric constant film;
Etching the first hard mask using the second hard mask as a mask, and transferring the wiring groove pattern for a thickness to the first hard mask;
Etching less than the thickness of the organic low dielectric constant film using the first and second hard masks as a mask to form a wiring groove on the upper surface side of the organic low dielectric constant film, and the connection hole Removing the organic low dielectric constant film in the portion where the pattern is transferred, and forming a connection hole on the bottom side of the organic low dielectric constant film;
Removing the second hard mask by etching;
A method of manufacturing a semiconductor device, comprising: embedding a conductor in the wiring groove and the connection hole. Before forming the organic low dielectric constant film on the lower layer wiring, the barrier insulation is etched on the lower layer wiring under the same conditions as the second hard mask, and the etching rate is different from that of the first hard mask. A step of forming a barrier insulating film that prevents diffusion of the material of the lower layer wiring,
After forming the wiring trench, the second hard mask is removed by etching, and the barrier insulating film is etched by a thickness using the organic low dielectric constant film as a mask, so that the barrier at the bottom of the connection hole is formed. The method of manufacturing a semiconductor device according to claim 7, wherein the insulating film is removed. Forming a first organic low dielectric constant film on the lower wiring;
Forming an insulating film having an etching rate different from that of the first organic low dielectric constant film on the first organic low dielectric constant film;
Forming a second organic low dielectric constant film on the insulating film, the second organic low dielectric constant film being different in etching rate from the insulating film and etched under the same conditions as the first organic low dielectric constant film;
A first hard mask is formed on the second organic low dielectric constant film, which is different in etching rate from the first and second organic low dielectric constant films and is etched under the same conditions as the insulating film. Process,
Forming a second hard mask having an etching rate different from any of the first and second organic low dielectric constant films, the insulating film, and the first hard mask on the first hard mask;
Forming a first resist having an opening with a connection hole pattern on the second hard mask;
Using the first resist as a mask, the second hard mask is etched for a thickness, and further, the first hard mask is etched halfway, and the upper surface side of the first hard mask and the second hard mask are etched. Transferring the connection hole pattern to the hard mask;
Removing the first resist;
Forming a second resist having an opening with a wiring groove pattern including the connection hole pattern on the second hard mask;
Etching the second hard mask with a thickness using the second resist as a mask, and transferring the wiring groove pattern to the second hard mask;
Removing the second resist;
Etching less than the thickness of the first hard mask using the second hard mask as a mask, transferring the wiring groove pattern to the upper surface side of the first hard mask, and transferring the connection hole pattern Removing the first hard mask of the formed portion;
Etching the second organic low dielectric constant film by a thickness using the first hard mask as a mask, and transferring the connection hole pattern to the second organic low dielectric constant film;
Etching is performed on the first hard mask using the second hard mask as a mask, the wiring groove pattern corresponding to the thickness is transferred to the first hard mask, and the second organic low dielectric constant film Etching the thickness of the insulating film using as a mask, and transferring the connection hole pattern to the insulating film;
Using the first and second hard masks as masks, the second organic low dielectric constant film is etched to a thickness to form wiring trenches in the second organic low dielectric constant film, and Etching the first organic low dielectric constant film for a thickness using an insulating film as a mask to form a connection hole in the first organic low dielectric constant film; and
Removing the second hard mask by etching;
A method of manufacturing a semiconductor device, comprising: embedding a conductor in the wiring groove and the connection hole. Before forming the first organic low dielectric constant film on the lower layer wiring, the etching rate is different from that of the first hard mask on the lower layer wiring, and is etched under the same conditions as the second hard mask. A step of forming the barrier insulating film for preventing diffusion of the material of the lower layer wiring,
After the formation of the wiring trench, the second hard mask is removed by etching, and the barrier insulating film is etched by a thickness using the first organic low dielectric constant film as a mask to form the bottom of the connection hole The method for manufacturing a semiconductor device according to claim 9, wherein the barrier insulating film is removed.

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