KR100447989B1 - Gate electrode formation method of semiconductor device - Google Patents
Gate electrode formation method of semiconductor device Download PDFInfo
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- KR100447989B1 KR100447989B1 KR10-1998-0055249A KR19980055249A KR100447989B1 KR 100447989 B1 KR100447989 B1 KR 100447989B1 KR 19980055249 A KR19980055249 A KR 19980055249A KR 100447989 B1 KR100447989 B1 KR 100447989B1
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- Prior art keywords
- film
- titanium silicide
- gate electrode
- layer
- forming
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 230000015572 biosynthetic process Effects 0.000 title 1
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 27
- 229920005591 polysilicon Polymers 0.000 claims description 27
- 238000009792 diffusion process Methods 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 20
- 230000004888 barrier function Effects 0.000 claims description 18
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 claims description 7
- 238000000206 photolithography Methods 0.000 claims description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 238000000151 deposition Methods 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract description 2
- 229910021332 silicide Inorganic materials 0.000 abstract description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 2
- 230000000903 blocking effect Effects 0.000 abstract 3
- 229910052710 silicon Inorganic materials 0.000 abstract 3
- 239000010703 silicon Substances 0.000 abstract 3
- 238000013508 migration Methods 0.000 abstract 2
- 230000005012 migration Effects 0.000 abstract 2
- 238000004220 aggregation Methods 0.000 abstract 1
- 230000002776 aggregation Effects 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 17
- 229920000642 polymer Polymers 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
Abstract
본 발명은 티타늄 실리사이드를 포함하는 게이트 전극에 있어서, 상기 티타늄 실리사이드막과 도핑된 실리사이드막의 계면에 발생되는 응집 현상을 방지할 수 있는 반도체 소자의 게이트 전극 형성방법을 개시한다. 개시된 본 발명은, 반도체 기판 상에 게이트 절연막, 도핑된 실리콘막을 순차적으로 형성하는 단계와, 상기 도핑된 실리콘막 상부에 원자 이동 저지막을 형성하는 단계와, 상기 원자 이동 저지막 상부에 티타늄 실리사이드막을 형성하는 단계와, 상기 티타늄 실리사이드막 상부에 마스크 산화막을 증착하는 단계, 및 상기 마스크 산화막, 티타늄 실리사이드막, 원자 이동 저지막 및 도핑된 실리콘막을 패터닝하여 게이트 전극을 형성하는 단계를 포함한다.The present invention discloses a method for forming a gate electrode of a semiconductor device in a gate electrode including titanium silicide, which can prevent aggregation phenomenon occurring at an interface between the titanium silicide film and the doped silicide film. According to the present invention, a method of sequentially forming a gate insulating film and a doped silicon film on a semiconductor substrate, forming an atomic migration blocking film on the doped silicon film, and forming a titanium silicide film on the atomic migration blocking film And depositing a mask oxide layer on the titanium silicide layer, and patterning the mask oxide layer, the titanium silicide layer, the atomic transfer blocking layer, and the doped silicon layer to form a gate electrode.
Description
본 발명은 반도체 소자의 게이트 전극 형성방법에 관한 것으로 보다 구체적으로는 티타늄 실리사이드막을 포함하는 게이트 전극 형성방법에 관한 것이다.The present invention relates to a method of forming a gate electrode of a semiconductor device, and more particularly to a method of forming a gate electrode comprising a titanium silicide film.
일반적으로, 게이트 전극은 모스 트랜지스터를 셀렉팅하는 전극으로서, 주로 불순물이 도핑된 폴리실리콘막이 대부분 이용된다. 이러한 도핑된 폴리실리콘막을 이용한 게이트 전극은 공정이 안정하다는 장점을 가지지만, 폴리실리콘막의 높은 비저항으로 인하여 디자인룰(design rule)이 작아짐에 따라 소자의 동작 속도가 저하된다는 문제점이 있다.In general, a gate electrode is an electrode for selecting a MOS transistor, and a polysilicon film mainly doped with impurities is used. The gate electrode using the doped polysilicon film has an advantage that the process is stable, but there is a problem that the operation speed of the device decreases as the design rule becomes smaller due to the high resistivity of the polysilicon film.
따라서 종래에는 고융점 실리사이드막 특히 티타늄 실리사이드막을 사용하는 구조가 제안되었다. 도 1는 티타늄 실리사이드막을 포함하는 게이트 전극을 나타낸 도면으로, 도 1를 참조하여 종래의 게이트 전극 형성방법을 설명한다.Therefore, conventionally, a structure using a high melting point silicide film, particularly a titanium silicide film, has been proposed. 1 is a view illustrating a gate electrode including a titanium silicide layer, and a conventional method of forming a gate electrode will be described with reference to FIG.
먼저, 도 1에 도시된 바와 같이, 반도체 기판(1) 상부에 열산화 방식에 의하에 게이트 절연막(2)을 형성한다. 이어, 게이트 절연막(2) 상부에 도핑된 폴리실리콘막(3)을 증착하고, 도핑된 폴리실리콘(3) 상부에 티타늄 실리사이드막(5)을 증착한다음, 티타늄 실리사이드막(5) 상부에 마스크 산화막(6)을 형성한다.First, as shown in FIG. 1, the gate insulating film 2 is formed on the semiconductor substrate 1 by thermal oxidation. Subsequently, a doped polysilicon layer 3 is deposited on the gate insulating layer 2, a titanium silicide layer 5 is deposited on the doped polysilicon layer 3, and then a mask is formed on the titanium silicide layer 5. The oxide film 6 is formed.
그후, 공지의 포토리소그라피 공정 및 패터닝 공정에 의하여 산화막(6)과 티타늄 실리사이드막(5) 및 도핑된 폴리실리콘막(3)을 순차적으로 패터닝하여 게이트 전극을 형성한다.Thereafter, the oxide film 6, the titanium silicide film 5, and the doped polysilicon film 3 are sequentially patterned by a known photolithography process and a patterning process to form a gate electrode.
그러나, 상기와 같이 티타늄 실리사이드막을 이용한 게이트 전극은 다음과 같은 문제점을 갖는다.However, the gate electrode using the titanium silicide film as described above has the following problems.
일반적으로 게이트 전극을 형성한 다음에는 소정의 열공정을 진행하게 되는데, 이과정에서 티타늄 실리사이드층의 티타늄 원자가 폴리실리콘쪽으로 확산되어, 폴리실리콘 형태가 변형되었다. 이로 인하여, 게이트 전극의 GOI(gate oxide integrity)특성이 나빠져서, 소자의 신뢰성이 저하된다.In general, after the gate electrode is formed, a predetermined thermal process is performed. In this process, titanium atoms of the titanium silicide layer are diffused toward polysilicon, thereby deforming the polysilicon form. As a result, the GOI (gate oxide integrity) characteristics of the gate electrode are deteriorated, and the reliability of the device is lowered.
또한, 티타늄 실리사이드막과 폴리실리콘막은 Cl2/O2플라즈마 또는 HBr/O2플라즈마를 이용하여 식각되는데, 이러한 플라즈마 가스로 식각 공정을 진행할 때, 특히 티타늄 실리사이드막을 식각하는 과정에서 산화 폴리머가 발생되어, 폴리실리콘막 표면에 남게 된다. 이때, 산화 폴리머는 쉽게 제거되지 않고 남아있게 된다.In addition, the titanium silicide layer and the polysilicon layer are etched using Cl 2 / O 2 plasma or HBr / O 2 plasma. When the etching process is performed with the plasma gas, an oxide polymer is generated during the etching of the titanium silicide layer. And remain on the surface of the polysilicon film. At this time, the oxidized polymer is not easily removed and remains.
이러한 문제점을 해결하기 위하여, 종래의 다른 방법으로는 폴리실리콘막과 티타늄 실리사이드막 사이에 티타늄 질화막을 개재하였다. 그러나, 상기 티타늄 질화막을 개재하는 방법은 티타늄 또는 실리콘 원자의 확산은 줄일 수 있었으나, 식각시 발생되는 산화 폴리머의 발생은 방지할 수 없었다.In order to solve this problem, another conventional method has interposed a titanium nitride film between the polysilicon film and the titanium silicide film. However, in the method of interposing the titanium nitride layer, diffusion of titanium or silicon atoms can be reduced, but generation of an oxidized polymer generated during etching cannot be prevented.
따라서, 본 발명의 목적은 티타늄 실리사이드막과 폴리실리콘막 사이의 원자확산을 방지하면서, 게이트 전극을 형성하기 위한 식각 공정시 식각 폴리머의 발생을 방지할 수 있는 반도체 소자의 게이트 전극 형성방법을 제공하는 것을 목적으로 한다.Accordingly, an object of the present invention is to provide a method for forming a gate electrode of a semiconductor device capable of preventing generation of an etching polymer during an etching process for forming a gate electrode while preventing atomic diffusion between the titanium silicide film and the polysilicon film. For the purpose of
도 1은 종래의 게이트 전극 형성방법을 설명하기 위한 도면.1 is a view for explaining a conventional method for forming a gate electrode.
도 2a 내지 도 2e는 본 발명에 따른 반도체 소자의 게이트 전극 형성방법을 설명하기 위한 각 공정별 단면도.2A through 2E are cross-sectional views of respective processes for explaining a method of forming a gate electrode of a semiconductor device according to the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
10 - 반도체 기판 11 - 게이트 절연막10-semiconductor substrate 11-gate insulating film
12 - 폴리실리콘막 13 - 확산 방지막12-polysilicon film 13-diffusion barrier
14 - 티타늄 실리사이드막 15 - 마스크 산화막14-Titanium Silicide Film 15-Mask Oxide
상기한 본 발명의 목적을 달성하기 위하여, 본 발명의 일 실시예에 따르면, 반도체 기판 상에 게이트 절연막, 폴리실리콘막, 원자 이동을 저지하는 확산 방지막,티타늄 실리사이드막 및 하드 마스크막을 순차적으로 형성하는 단계; 및 포토리소그라피 공정에 의해 상기 하드마스크막, 티타늄 실리사이드막, 확산 방지막 및 폴리실리콘막을 소정형상으로 식각하여 게이트 전극을 형성하는 단계를 포함하며,In order to achieve the above object of the present invention, according to an embodiment of the present invention, to form a gate insulating film, a polysilicon film, a diffusion preventing film, a titanium silicide film and a hard mask film in order to prevent the movement of atoms in sequence step; And etching the hard mask film, the titanium silicide film, the diffusion barrier film, and the polysilicon film into a predetermined shape by a photolithography process to form a gate electrode.
상기 확산 방지막으로는 티타늄 실리사이드막을 식각할 시에 이용되는 식각 가스에 대하여 식각 선택비가 우수한 물질인 티타늄 알루미늄 나이트라이드막을 형성되는 것을 특징으로 한다.The diffusion barrier layer is characterized in that the titanium aluminum nitride film is formed of a material having excellent etching selectivity with respect to the etching gas used to etch the titanium silicide film.
상기 티타늄 알루미늄 질화막은 화학 기상 증착방법 또는 물리적 기상 증착방법으로 형성되며, 약 50 내지 200Å 정도의 두께로 형성된다.The titanium aluminum nitride film is formed by a chemical vapor deposition method or a physical vapor deposition method, it is formed to a thickness of about 50 ~ 200Å.
상기 게이트전극 형성 단계에서, 상기 티타늄 실리사이드막은 Cl2/O2플라즈마 또는 HBr/O2플라즈마 가스로 식각하거나, SF6플라즈마 가스로 식각하되, 상기 식각 가스의 30% 정도 이상 O2가스를 주입하면서 식각함이 바람직하다.In the forming of the gate electrode, the titanium silicide layer may be etched with Cl 2 / O 2 plasma or HBr / O 2 plasma gas, or etched with SF 6 plasma gas, but may be etched while injecting at least 30% of the etching gas with O 2 gas. desirable.
또한, 상기 확산 방지막은 플로우린 계열의 플라즈마 가스로 식각한다.In addition, the diffusion barrier layer is etched with a fluorine-based plasma gas.
상기 티타늄 실리사이드막 상부에 마스크 산화막을 증착하는 단계와, 상기 마스크 산화막, 티타늄 실리사이드막, 확산 방지막 및 폴리실리콘막을 순차적으로 패터닝하여 게이트 전극을 형성하는 단계 사이에 막들간의 접착력을 강화시키기 위하여, 결과물을 어닐링하는 공정을 추가로 포함한다.In order to enhance the adhesion between the films between the step of depositing a mask oxide film on the titanium silicide film, and sequentially forming the mask oxide film, titanium silicide film, diffusion barrier film and polysilicon film to form a gate electrode Annealing step further includes.
본 발명에 의하면, 티타늄 실리사이드막을 포함하는 게이트 전극을 형성할 때, 티타늄 실리사이드막과 폴리실리콘막 사이에, 티타늄 실리사이드막과 Cl2/O2플라즈마 또는 HBr/O2플라즈마 가스에 대한 식각 선택비가 우수한 막을 확산 방지막으로 개재한다음, 티타늄 실리사이드막과 확산 방지막 및 폴리실리콘막을 각각 선택적으로 제거한다.According to the present invention, when the gate electrode including the titanium silicide film is formed, the etching selectivity of the titanium silicide film and the Cl 2 / O 2 plasma or the HBr / O 2 plasma gas is excellent between the titanium silicide film and the polysilicon film. After the film is interposed with the diffusion barrier, the titanium silicide layer, the diffusion barrier and the polysilicon layer are selectively removed.
이에따라, 티타늄 실리사이드막과 폴리실리콘막 사이의 원자 확산을 줄일 수 있고, 각각의 막을 선택적으로 제거하므로써, 식각 폴리머의 발생을 저지할 수 있다.Accordingly, the atomic diffusion between the titanium silicide film and the polysilicon film can be reduced, and by selectively removing each film, generation of an etching polymer can be prevented.
(실시예)(Example)
이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도면 도 2a 내지 도 2e는 본 발명에 따른 반도체 소자의 게이트 전극 형성방법을 설명하기 위한 각 공정별 단면도이다.2A through 2E are cross-sectional views of respective processes for describing a method of forming a gate electrode of a semiconductor device according to the present invention.
먼저, 도 2a를 참조하여, 반도체 기판(10) 표면에 게이트 절연막(11)을 형성한다. 여기서, 게이트 절연막(11)은 열산화 방식으로 형성될수도 있고, 실리콘 산화막(SiO2)/탄탈륨 산화막(Ta2O5)/실리콘 산화막(SiO2)의 적층막으로 사용될 수도 있다. 이 게이트 절연막(11)은 약 30 내지 70Å 두께로 증착한다. 이어서, 게이트 절연막(11) 상부에 게이트 전극을 구성하기 위하여, 도핑된 폴리실리콘막(12), 확산 방지막(13), 티타늄 실리사이드막(14) 및 하드 마스크막(15)을 순차적으로 형성한다.First, referring to FIG. 2A, a gate insulating layer 11 is formed on a surface of a semiconductor substrate 10. Here, the gate insulating film 11 may be formed by a thermal oxidation method, or may be used as a laminated film of a silicon oxide film (SiO 2 ) / tantalum oxide film (Ta 2 O 5 ) / silicon oxide film (SiO 2 ). The gate insulating film 11 is deposited to a thickness of about 30 to 70 Å. Subsequently, in order to form a gate electrode on the gate insulating film 11, the doped polysilicon film 12, the diffusion barrier film 13, the titanium silicide film 14, and the hard mask film 15 are sequentially formed.
이때, 본 실시예에서의 확산 방지막(13)은 티타늄 실리사이드막(14)과는 Cl2/O2플라즈마 또는 HBr/O2플라즈마 가스에 대하여 적어도 20분의 1 정도의 우수한 식각 선택비를 갖는 막으로, 예를들어 티타늄알루미늄 나이트라이드막(TiAlN)을 이용한다. 여기서, 티타늄알루미늄 나이트라이드막은 화학 기상 증착방법 또는 물리적 기상 증착방법으로 형성할 수 있고, 약 50 내지 200Å 정도로 증착함이 바람직하다.At this time, the diffusion barrier 13 in the present embodiment is a film having an excellent etching selectivity of at least about 1/20 with respect to the Cl 2 / O 2 plasma or HBr / O 2 plasma gas from the titanium silicide film 14. For example, a titanium aluminum nitride film (TiAlN) is used. Here, the titanium aluminum nitride film can be formed by a chemical vapor deposition method or a physical vapor deposition method, it is preferable to deposit about 50 to 200Å.
하드 마스크막(15)는 산화막 또는 질화막으로 형성된다.The hard mask film 15 is formed of an oxide film or a nitride film.
그후, 하드 마스크막(15)까지 형성한 결과물을 소정 온도에서 어닐링하여 막들간의 접착력을 강화시킨다.Thereafter, the resultant formed up to the hard mask film 15 is annealed at a predetermined temperature to enhance the adhesion between the films.
그리고나서, 하드 마스크막(15) 상부에 공지의 포토리소그라피 공정을 사용하여 포토레지스트 패턴(16)을 형성한다.Then, the photoresist pattern 16 is formed on the hard mask film 15 using a known photolithography process.
다음으로, 도 2b에 도시된 바와 같이, 포토레지스트 패턴(16)을 마스크로 하여, 하드 마스크막(15)을 식각한다. 이때, 하드 마스크막(15)은 메리타입 리액터(MERIE type reactor)의 CF4플라즈마를 이용하여 식각된다.Next, as shown in FIG. 2B, the hard mask film 15 is etched using the photoresist pattern 16 as a mask. At this time, the hard mask film 15 is etched using CF 4 plasma of a MERIE type reactor.
그후, 도 2c에 도시된 바와 같이, 노출된 티타늄 실리사이드막(14)을 상기 포토레지스트 패턴(16) 및 하드 마스크막(15)을 마스크로 하여 식각한다. 이때, 상기 티타늄 실리사이드막(14)은 Cl2/O2플라즈마 또는 HBr/O2플라즈마 가스로 식각하여, 티타늄 실리사이드막(14)만이 식각되고, 상기 플라즈마 가스에 대하여 식각 선택비가 우수한 확산 방지막(13)은 식각되지 않는다.Thereafter, as shown in FIG. 2C, the exposed titanium silicide layer 14 is etched using the photoresist pattern 16 and the hard mask layer 15 as a mask. In this case, the titanium silicide layer 14 is etched by Cl 2 / O 2 plasma or HBr / O 2 plasma gas, so that only the titanium silicide layer 14 is etched, and the diffusion barrier layer 13 having an excellent etching selectivity with respect to the plasma gas. ) Is not etched.
상기 플라즈마 가스 외에도 SF6플라즈마 가스를 이용하여 식각할 수 있는데, 이 가스를 사용할때는 산소(O2) 가스를 상기 SF6플라즈마 가스의 30% 이상 주입하여 티타늄 실리사이드막(14)과 확산 방지막(13)이 식각 선택비가 나도록 한다.In addition to the plasma gas SF 6 may be etched using a plasma gas, when using a gas of oxygen (O 2) of 30% or more implanted titanium silicide film 14 and the diffusion of the SF 6 plasma gas, the gas-barrier film (13 ) Has an etching selectivity.
다음, 도 2d에 도시된 바와 같이, 노출된 확산 방지막(13)을 플로우린 계열의 플라즈마 가스로 식각한다. 이때, 폴리실리콘막(12)에 영향을 주지 않도록 확산 방지막(13)만을 선택적으로 제거한다.Next, as shown in FIG. 2D, the exposed diffusion barrier 13 is etched with a fluorine-based plasma gas. At this time, only the diffusion barrier 13 is selectively removed so as not to affect the polysilicon film 12.
그후, 도 2e에 도시된 바와 같이, 노출된 폴리실리콘막을 패터닝한다음, 공지의 방식으로 포토레지스트 패턴을 제거한다. 이에따라 게이트 전극이 완성된다.Thereafter, as shown in Fig. 2E, the exposed polysilicon film is patterned and then the photoresist pattern is removed in a known manner. This completes the gate electrode.
이상에서 자세히 설명된 바와 같이, 본 발명에 의하면, 티타늄 실리사이드막을 포함하는 게이트 전극을 형성할 때, 티타늄 실리사이드막과 폴리실리콘막 사이에, 티타늄 실리사이드막과 Cl2/O2플라즈마 또는 HBr/O2플라즈마 가스에 대한 식각 선택비가 우수한 막을 확산 방지막으로 개재한다음, 티타늄 실리사이드막과 확산 방지막 및 폴리실리콘막을 각각 선택적으로 제거한다.As described in detail above, according to the present invention, when forming the gate electrode including the titanium silicide film, between the titanium silicide film and the polysilicon film, the titanium silicide film and Cl 2 / O 2 plasma or HBr / O 2 A film having an excellent etching selectivity to plasma gas was interposed as a diffusion barrier, and then the titanium silicide layer, the diffusion barrier and the polysilicon layer were selectively removed.
이에따라, 티타늄 실리사이드막과 폴리실리콘막 사이의 원자 확산을 줄일 수 있고, 각각의 막을 선택적으로 제거하므로써, 식각 폴리머의 발생을 저지할 수 있다.Accordingly, the atomic diffusion between the titanium silicide film and the polysilicon film can be reduced, and by selectively removing each film, generation of an etching polymer can be prevented.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101979509B1 (en) * | 2017-04-20 | 2019-05-16 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Self-aligned gate hard mask and method forming same |
| US10686075B2 (en) | 2017-04-20 | 2020-06-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned gate hard mask and method forming same |
| US11205724B2 (en) | 2017-04-20 | 2021-12-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned gate hard mask and method forming same |
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