KR970054044A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents

Capacitor Manufacturing Method of Semiconductor Device Download PDF

Info

Publication number
KR970054044A
KR970054044A KR1019950055948A KR19950055948A KR970054044A KR 970054044 A KR970054044 A KR 970054044A KR 1019950055948 A KR1019950055948 A KR 1019950055948A KR 19950055948 A KR19950055948 A KR 19950055948A KR 970054044 A KR970054044 A KR 970054044A
Authority
KR
South Korea
Prior art keywords
insulating film
insulating layer
etching
conductive layer
forming
Prior art date
Application number
KR1019950055948A
Other languages
Korean (ko)
Other versions
KR100246467B1 (en
Inventor
박정호
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950055948A priority Critical patent/KR100246467B1/en
Publication of KR970054044A publication Critical patent/KR970054044A/en
Application granted granted Critical
Publication of KR100246467B1 publication Critical patent/KR100246467B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 반도체 메모리장치으 커패시터 제조방법에 관한 것으로, 안정화된 커패시터 전하저장 전극을 제조하기 위한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor in a semiconductor memory device, and to manufacturing a stabilized capacitor charge storage electrode.

이를 위해 본 발명은 기판상에 형성된 제1절연막 전면에 도전층을 형성하는 단계와, 상기 도전층상에 제2절연막을 형성하는 단계, 상기 제2절연막을 선택적으로 건식식각하여 소저으이 제2절연막패턴을 형성하는 단계, 상기 제2절연막패턴을 마스크로 하여 상기 도전층을 측벽식각을 특징으로 하는 가스를 이용하여 건식식각하는 단계, 상기 제2절연막의 건식식각시 그 측면에 형성된 폴리머를 습식식각에 의해 제거하는 단계, 상기 제2절연막패턴 측면에 도전층 스페이서를 형성하는 단계, 및 상기 제2절연막패턴을 습식식각에 의해 제거하는 단계를 포함하여 이루어지는 반도체 메모리장치의 커패시터 제조방법을 제공한다.To this end, the present invention comprises the steps of forming a conductive layer on the entire surface of the first insulating film formed on the substrate, forming a second insulating film on the conductive layer, selectively dry-etching the second insulating film to form a second insulating film pattern Forming a thin film; and etching the conductive layer using a gas having a sidewall etch using the second insulating film pattern as a mask. The polymer formed on the side surface of the second insulating film is wet-etched. And removing the second insulating film pattern by wet etching, and forming a conductive layer spacer on the side surface of the second insulating film pattern.

Description

반도체 메모리장치의 커패시터 제조방법Capacitor Manufacturing Method of Semiconductor Memory Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 의한 커패시터 전하저장 전극 형성방법을 도시한 공정순서도이다.2 is a process flowchart showing a method of forming a capacitor charge storage electrode according to the present invention.

Claims (5)

기판상에 형성된 제1절연막 전면에 도전층을 형성하는 단계와, 상기 도전층상에 제2절연막을 형성하는 단계, 상기 제2절연막을 선택적으로 건식식각하여 소저의 제2절연막패턴을 형성하는 단계,상기 제2절연막패턴을 마스크로 하여 상기 도전층을 측벽식각을 특징으로 하는 가스를 이용하여 건식식각하는 단계, 상기 제2절연막을 건식식각시 그 측면에 형성된 폴리머를 습식식각에 의해 제거하는 단계, 상기 제2절연막패턴 측면에 도전층 스페이서를 형성하는 단계, 및 상기 제2절연막패턴을 습식식각에 의해 제거하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 메모리장치의 커패시터 제조방법.Forming a conductive layer on the entire surface of the first insulating layer formed on the substrate, forming a second insulating layer on the conductive layer, selectively dry etching the second insulating layer to form a second insulating layer pattern; Dry etching the conductive layer using a gas having sidewall etching using the second insulating layer pattern as a mask, and removing the polymer formed on a side surface of the second insulating layer by wet etching during dry etching; Forming a conductive layer spacer on a side surface of the second insulating film pattern, and removing the second insulating film pattern by wet etching. 제1항에 있어서, 상기 제1절연막과 제2절연막은 식각 선택비가 서로 다른 절연막을 사용하여 형성하는 것을 특징으로 하는 반도체 메모리장치의 커패시터 제조방법.The method of claim 1, wherein the first insulating layer and the second insulating layer are formed using an insulating layer having a different etching selectivity. 제3항에 있어서, 상기 제2절연막은 산화막으로 형성하는 것을 특징으로 하는 반도체 메모리장치의 커패시터 제조방법.4. The method of claim 3, wherein the second insulating layer is formed of an oxide film. 제1항에 있어서, 상기 제2절연막패턴을 습식식각은 HF 또는 BOE를 이용하여 행하는 것을 특징으로 하는 반도체 메모리장치으 커패시터 제조방법.The method of claim 1, wherein the wet etching of the second insulating layer pattern is performed using HF or BOE. 제1항에 있어서, 상기 측벽식각을 특징으로 하는 가스로 SF6를 이용하는 것을 특징으로 하는 반도체 메모리장치의 커패시터 제조방법.2. The method of claim 1, wherein SF 6 is used as the gas characterized by the sidewall etching. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950055948A 1995-12-23 1995-12-23 Manufacturing method of capacitor in semiconductor device using the side-lobe of phase-reversal mask KR100246467B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950055948A KR100246467B1 (en) 1995-12-23 1995-12-23 Manufacturing method of capacitor in semiconductor device using the side-lobe of phase-reversal mask

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950055948A KR100246467B1 (en) 1995-12-23 1995-12-23 Manufacturing method of capacitor in semiconductor device using the side-lobe of phase-reversal mask

Publications (2)

Publication Number Publication Date
KR970054044A true KR970054044A (en) 1997-07-31
KR100246467B1 KR100246467B1 (en) 2000-03-15

Family

ID=19444106

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950055948A KR100246467B1 (en) 1995-12-23 1995-12-23 Manufacturing method of capacitor in semiconductor device using the side-lobe of phase-reversal mask

Country Status (1)

Country Link
KR (1) KR100246467B1 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03222417A (en) * 1990-01-29 1991-10-01 Nec Corp Manufacture of semiconductor device
JPH0677430A (en) * 1992-08-28 1994-03-18 Hitachi Ltd Semiconductor device and manufacture thereof

Also Published As

Publication number Publication date
KR100246467B1 (en) 2000-03-15

Similar Documents

Publication Publication Date Title
KR970024206A (en) A method for manufacturing a capacitor of a semiconductor memory device.
KR940010316A (en) Method of manufacturing charge storage electrode
KR970054044A (en) Capacitor Manufacturing Method of Semiconductor Device
KR970054043A (en) Capacitor Manufacturing Method of Semiconductor Memory Device
KR960026870A (en) Capacitor Manufacturing Method of Semiconductor Device
KR970024184A (en) Method of fabricating a capacitor in semiconductor device
KR970030777A (en) Capacitor Manufacturing Method of Semiconductor Device
KR970052320A (en) Method for forming charge storage electrode of semiconductor device
KR970030817A (en) Capacitor Manufacturing Method of Semiconductor Device
KR970054009A (en) Capacitor Manufacturing Method of Semiconductor Device
KR980005476A (en) Method for forming storage electrode of semiconductor device
KR960002789A (en) Capacitor Manufacturing Method of Semiconductor Device
KR970052284A (en) Method for forming charge storage electrode of semiconductor device
KR970054122A (en) Method for forming storage electrode of semiconductor device
KR960019732A (en) Method for forming charge storage electrode of semiconductor device
KR970053820A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960043155A (en) Method for manufacturing charge storage electrode of capacitor
KR960026793A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960043192A (en) Semiconductor Capacitors and Manufacturing Method Thereof
KR960026856A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960006031A (en) Capacitor Manufacturing Method of Semiconductor Device
KR950024345A (en) Semiconductor Memory Device Manufacturing Method
KR960026812A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960043181A (en) Manufacturing method of stack capacitor
KR960036066A (en) Capacitor Manufacturing Method of Semiconductor Device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20061122

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee