KR970054043A

KR970054043A - Capacitor Manufacturing Method of Semiconductor Memory Device

Info

Publication number: KR970054043A
Application number: KR1019950055940A
Authority: KR
Inventors: 박찬동; 김명선
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1995-12-23
Filing date: 1995-12-23
Publication date: 1997-07-31

Abstract

본 발명은 반도체 메모리장치으 커패시터 제조방법에 관한 것으로, 안정화된 커패시터 전하저장 전극을 제조하기 위한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor in a semiconductor memory device, and to manufacturing a stabilized capacitor charge storage electrode.

이를 위해 본 발명은 기판상에 형성된 제1절연막 전면에 도전층을 형성하는 단계와, 상기 도전층상에 제2절연막을 형성하는 단계, 상기 제2절연막을 선택적으로 건식식각하여 소저으이 제2절연막패턴을 형성하는 단계, 상기 제2절연막패턴을 마스크로 하여 상기 도전층을 측벽식각을 특징으로 하는 가스를 이용하여 건식식각하는 단계, 상기 제2절연막의 건식식각시 그 측면에 형성된 폴리머를 습식식각에 의해 제거하는 단계, 상기 제2절연막패턴 측면에 도전층 스페이서를 형성하는 단계, 및 상기 제2절연막패턴을 습식식각에 의해 제거하는 단계를 포함하여 이루어지는 반도체 메모리장치의 커패시터 제조방법을 제공한다.To this end, the present invention comprises the steps of forming a conductive layer on the entire surface of the first insulating film formed on the substrate, forming a second insulating film on the conductive layer, selectively dry-etching the second insulating film to form a second insulating film pattern Forming a thin film; and etching the conductive layer using a gas having a sidewall etch using the second insulating film pattern as a mask. The polymer formed on the side surface of the second insulating film is wet-etched. And removing the second insulating film pattern by wet etching, and forming a conductive layer spacer on the side surface of the second insulating film pattern.

Description

Capacitor Manufacturing Method of Semiconductor Memory Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 의한 커패시터 전하저장 전극 형성방법을 도시한 공정순서도이다.2 is a process flowchart showing a method of forming a capacitor charge storage electrode according to the present invention.

Claims

Forming a conductive layer on the entire surface of the first insulating layer formed on the substrate, forming a second insulating layer on the conductive layer, selectively dry etching the second insulating layer to form a second insulating layer pattern; Dry etching the conductive layer using a gas having sidewall etching using the second insulating layer pattern as a mask, and removing the polymer formed on a side surface of the second insulating layer by wet etching during dry etching; Forming a conductive layer spacer on a side surface of the second insulating film pattern, and removing the second insulating film pattern by wet etching.

The method of claim 1, wherein the first insulating layer and the second insulating layer are formed using an insulating layer having a different etching selectivity.

4. The method of claim 3, wherein the second insulating layer is formed of an oxide film.

The method of claim 1, wherein the wet etching of the second insulating layer pattern is performed using HF or BOE.

2. The method of claim 1, wherein SF ₆ is used as the gas characterized by the sidewall etching.

※ Note: The disclosure is based on the initial application.