KR960036066A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents

Capacitor Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR960036066A
KR960036066A KR1019950006708A KR19950006708A KR960036066A KR 960036066 A KR960036066 A KR 960036066A KR 1019950006708 A KR1019950006708 A KR 1019950006708A KR 19950006708 A KR19950006708 A KR 19950006708A KR 960036066 A KR960036066 A KR 960036066A
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KR
South Korea
Prior art keywords
storage electrode
charge storage
forming
conductive film
insulating layer
Prior art date
Application number
KR1019950006708A
Other languages
Korean (ko)
Inventor
박상훈
손곤
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950006708A priority Critical patent/KR960036066A/en
Publication of KR960036066A publication Critical patent/KR960036066A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 통상적인 트랜지스터 구조 및 제1절연막이 형성된 기판상에 예정된 전하저장전극 콘택 홀보다는 큰 트기(폭)를 갖는 마스크를 사용하여 상기 제1절연막의 전체두께중 소정두께를 식각하는 단계: 전체구조 상부에 제1전도막을 형성하고 상기 제1절연막이 노출될때까지 상기 제1전도막을 비등방성 전면식각하는 단계: 노출된 제1절연막을 식각하여 전하저장전극 콘택 홀을 형성하는 단계: 전체 구조의 상부에 제2전도막을 형성하는 단계: 예정된 전하저장전극의 높이를 결정하며 전하저장전극의 실린더 형태를 결정하는 제2절연막 패턴을 형성하는 단계: 전체구조의 상부에 제3전도막을 형성하는 단계: 및 전하저장전극 마스크를 사용하여, 상기 제3전도막 비등방성 식각, 제2절연막 제거, 제2전도막 비등방성 식각을 차례로 실시하는 단계를 포함하여, 제1전도막 내지 제3전도막으로 이루어지는 전하저장전극을 형성하는 것을 특징으로 하는 캐패시터 형성 방법에 관한 것으로, 실린더 형태의 캐패시터 제조시에 폴리실리콘 스페이서를 사용한 자기정렬 방식으로 미세 콘택홀 형성하며, 전하저장전극의 표면적을 증대시키는 반도체 소자의 고집적화를 앞당기는 효과가 있다.Etching a predetermined thickness of the entire thickness of the first insulating film using a mask having a larger transistor (width) than a predetermined charge storage electrode contact hole on a substrate having a conventional transistor structure and the first insulating film is formed: Forming a first conductive layer on the structure and anisotropically etching the first conductive layer until the first insulating layer is exposed: etching the exposed first insulating layer to form a charge storage electrode contact hole: Forming a second conductive film on the top: Forming a second insulating film pattern for determining the predetermined height of the predetermined charge storage electrode and the cylinder shape of the charge storage electrode: Forming a third conductive film on the top of the overall structure: And sequentially performing the third conductive film anisotropic etching, the second insulating film removing, and the second conductive film anisotropic etching using a charge storage electrode mask. The present invention relates to a capacitor forming method comprising forming a charge storage electrode comprising a first conductive film to a third conductive film. In addition, there is an effect of accelerating the high integration of the semiconductor device to increase the surface area of the charge storage electrode.

Description

반도체 소자의 캐패시터 제조방법Capacitor Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A도 내지 제2H도는 본 발명의 일실시예에 따른 캐패시터 형성 공정도.2A through 2H are capacitor formation process diagrams according to one embodiment of the present invention.

Claims (3)

통상적인 트랜지스터 구조 및 제1절연막이 형성된 기판 상에 예정된 전하저장전극 콘택 홀 보다는 큰 크기(폭)을 갖는 마스크를 사용하여 상기 제1절연막의 전체두께중 소정두께를 식각하는 단계: 전체구조 상부에 제1전도막을 형성하고 상기 제1절연막이 노출될 때까지 상기 제1전도막을 비등방성 전면식각하는 단계: 노출된 제1절연막을 식각하열 전하저장전극 콘택 홀을 형성하는 단계: 전체구조의 상부에 제2전도막을 형성하는 단계: 예정된 전하저장전극의 높이를 결정하며 전하저장전극의 실린더 형태를 결정하는 제2절연막 패턴을 형성하는 단계: 전체구조의 상부에 제3전도막을 형성하는 단계: 및 전하저장전극 마스크를 사용하며, 상기 제3전도막 비등방성 식각, 제2절연막 제거, 제2전도막 비등방성 식각을 차례로 실시하는 단계를 포함하여, 제1전도막 내지 제3전도막으로 이루어지는 전하저장전극을 형성하는 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법.Etching a predetermined thickness of the entire thickness of the first insulating layer using a mask having a size (width) larger than that of a predetermined charge storage electrode contact hole on a substrate having a conventional transistor structure and the first insulating layer formed thereon: Forming a first conductive layer and anisotropically etching the first conductive layer until the first insulating layer is exposed: forming an exposed first insulating layer as an etch-discharge charge storage electrode contact hole; Forming a second conductive film: Forming a second insulating film pattern for determining the predetermined height of the predetermined charge storage electrode and the cylinder shape of the charge storage electrode: Forming a third conductive film on top of the overall structure: and charge Using a storage electrode mask, and performing the third conductive film anisotropic etching, the second insulating film removal, and the second conductive film anisotropic etching in order. A method for forming a capacitor of a semiconductor device, comprising forming a charge storage electrode comprising a conductive film to a third conductive film. 제1항에 있어서; 상기 제2절연막 패턴은 예정된 전하저장전극의 최대폭 보다는 적고 상기 제1절연막이 식각된 부위 보다는 큰 폭이 오픈되도록 패터닝된 평탄화된 산화막인 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법.The method of claim 1; And the second insulating layer pattern is a planarized oxide layer patterned such that the width of the second insulating layer pattern is smaller than a predetermined width of the predetermined charge storage electrode and larger than a portion where the first insulating layer is etched. 제1항에 있어서; 상기 제2절연막 패턴은 예정된 전하저장전극의 최대폭 보다는 적고 상기 제1절연막이 식각된 부위보다는 큰 폭으로 패터닝된 평탄화된 산화막인 것을 특징으로 하는 반도체 소자의 캐패시터 형성방법.The method of claim 1; And the second insulating layer pattern is a planarized oxide layer less than a predetermined maximum width of a predetermined charge storage electrode and patterned to a greater width than a portion where the first insulating layer is etched. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950006708A 1995-03-28 1995-03-28 Capacitor Manufacturing Method of Semiconductor Device KR960036066A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950006708A KR960036066A (en) 1995-03-28 1995-03-28 Capacitor Manufacturing Method of Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950006708A KR960036066A (en) 1995-03-28 1995-03-28 Capacitor Manufacturing Method of Semiconductor Device

Publications (1)

Publication Number Publication Date
KR960036066A true KR960036066A (en) 1996-10-28

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Family Applications (1)

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KR1019950006708A KR960036066A (en) 1995-03-28 1995-03-28 Capacitor Manufacturing Method of Semiconductor Device

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