KR970024226A - Storage electrode formation method of semiconductor memory device - Google Patents

Storage electrode formation method of semiconductor memory device Download PDF

Info

Publication number
KR970024226A
KR970024226A KR1019950036472A KR19950036472A KR970024226A KR 970024226 A KR970024226 A KR 970024226A KR 1019950036472 A KR1019950036472 A KR 1019950036472A KR 19950036472 A KR19950036472 A KR 19950036472A KR 970024226 A KR970024226 A KR 970024226A
Authority
KR
South Korea
Prior art keywords
storage electrode
platinum
forming
electrode pattern
layer
Prior art date
Application number
KR1019950036472A
Other languages
Korean (ko)
Inventor
정우영
유원종
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950036472A priority Critical patent/KR970024226A/en
Publication of KR970024226A publication Critical patent/KR970024226A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

반도체 메모리소자의 스토리지 전극 형성방법에 대해 기재되어 있다. 이는, 트랜지스터가 형성되어 있는 반도체기판 상에 층간절연층을 형성하는 제1단계, 층간절연층 상에 백금층을 형성하는 제2단계, 백금층 상에 산화막을 형성하는 제3단계, 산화막을 패터닝하여 스토리지 전극 패턴을 형성하는 제4단계 및 스토리지 전극 패턴을 식각마스크로하여 백금층을 이방성식각함으로써 스토리지 전극 패턴과 동일한 모양의 백금판과 백금판과 스토리지 전극 패턴의 측벽에 형성된 백금 스페이서를 동시에 형성하는 제5단계를 포함하는 것을 특징으로 한다. 따라서, 스토리지 전극의 표면적을 넓힐 수 있다.A method of forming a storage electrode of a semiconductor memory device is described. This includes a first step of forming an interlayer insulating layer on a semiconductor substrate on which a transistor is formed, a second step of forming a platinum layer on an interlayer insulating layer, a third step of forming an oxide film on a platinum layer, and patterning an oxide film. The fourth step of forming the storage electrode pattern and the anisotropic etching of the platinum layer using the storage electrode pattern as an etch mask to simultaneously form a platinum plate having the same shape as the storage electrode pattern, and a platinum spacer formed on the sidewall of the platinum electrode and the storage electrode pattern Characterized in that it comprises a fifth step. Thus, the surface area of the storage electrode can be increased.

Description

반도체 메모리소자의 스토리지 전극 형성방법Storage electrode formation method of semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1A도 내지 제1D도는 본 발명의 일 실시예에 따른 반도체 메모리소자의 스토리지 전극 형성방법을 설명하기 위해 도시한 단면도들이다.1A to 1D are cross-sectional views illustrating a method of forming a storage electrode of a semiconductor memory device according to an embodiment of the present invention.

Claims (2)

트랜지스터가 형성되어 있는 반도체기판 상에 층간절연층을 형성하는 제1단계; 상기 층간절연층 상에 백금층을 형성하는 제2단계; 상기 백금층 상에 산화막을 형성하는 제3단계; 상기 산화막을 패터닝하여 스토리지 전극 패턴을 형성하는 제4단계 및 상기 스토리지 전극 패턴을 식각마스크로하여 상기 백금층을 이방성식각함으로써 상기 스토리지 전극 패턴과 동일한 모양의 백금판과 상기 백금판과 스토리지 전극 패턴의 측벽에 형성된 백금 스페이서를 동시에 형성하는 제5단계를 포함하는 것을 특징으로 하는 반도체 메모리소자의 스토리지 전극 형성방법.A first step of forming an interlayer insulating layer on the semiconductor substrate on which the transistor is formed; Forming a platinum layer on the interlayer insulating layer; A third step of forming an oxide film on the platinum layer; Forming a storage electrode pattern by patterning the oxide layer; and anisotropically etching the platinum layer using the storage electrode pattern as an etch mask to form a platinum plate having the same shape as the storage electrode pattern, and the platinum plate and the storage electrode pattern. And a fifth step of simultaneously forming platinum spacers formed on the sidewalls. 제1항에 있어서, 상기 제5단계 후, 상기 백금 스페이서가 형성되어 있는 반도체기판 전면에 포토레지스트를 도포하는 제6단계, 상기 스토리지 전극 패턴의 일부 표면이 노출되도록 상기 포토레지스트를 패터닝함으로써 포토레지스트 패턴을 형성하는 제7단계 및 상기 포토레지스트 패턴을 식각마스크로하여 노출된 상기 스토리지 전극 패턴 및 상기 스토리지 전극 패턴 하부에 형성되어 있는 백금판을 식각하는 제8단계를 더 포함하는 것을 특징으로 하는 반도체 메모리소자의 스토리지 전극 형성방법.The photoresist of claim 1, wherein, after the fifth step, applying the photoresist to the entire surface of the semiconductor substrate on which the platinum spacers are formed, patterning the photoresist to expose a portion of the storage electrode pattern. And forming a pattern and an eighth step of etching the exposed storage electrode pattern and the platinum plate formed under the storage electrode pattern by using the photoresist pattern as an etching mask. A storage electrode forming method of a memory device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950036472A 1995-10-20 1995-10-20 Storage electrode formation method of semiconductor memory device KR970024226A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950036472A KR970024226A (en) 1995-10-20 1995-10-20 Storage electrode formation method of semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950036472A KR970024226A (en) 1995-10-20 1995-10-20 Storage electrode formation method of semiconductor memory device

Publications (1)

Publication Number Publication Date
KR970024226A true KR970024226A (en) 1997-05-30

Family

ID=66583966

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950036472A KR970024226A (en) 1995-10-20 1995-10-20 Storage electrode formation method of semiconductor memory device

Country Status (1)

Country Link
KR (1) KR970024226A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100629021B1 (en) * 1997-09-03 2006-11-30 지멘스 악티엔게젤샤프트 Structuring method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100629021B1 (en) * 1997-09-03 2006-11-30 지멘스 악티엔게젤샤프트 Structuring method

Similar Documents

Publication Publication Date Title
KR950001901A (en) Contact hole manufacturing method
KR980006303A (en) Capacitor Manufacturing Method of Semiconductor Device
KR950010053A (en) Method for manufacturing bit line via hole in memory cell
KR970024226A (en) Storage electrode formation method of semiconductor memory device
KR970024184A (en) Method of fabricating a capacitor in semiconductor device
KR930014995A (en) Manufacturing method of nonvolatile memory
KR970024210A (en) DRAM manufacturing method of semiconductor device
KR970013348A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960039145A (en) Bit line self-aligned contact formation method
KR970048928A (en) Fine Pattern Formation Method of Semiconductor Device
KR970053203A (en) Semiconductor device and manufacturing method thereof
KR970054054A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960015906A (en) Manufacturing Method of Semiconductor Memory Device
KR970003959A (en) Method of forming charge storage electrode of capacitor
KR960035809A (en) Contact Forming Method of Semiconductor Device
KR970053093A (en) Inverting layer drain transistor manufacturing method
KR970053941A (en) Method for manufacturing charge storage electrode of semiconductor device
KR970030326A (en) Contact hole formation method of semiconductor device
KR960019732A (en) Method for forming charge storage electrode of semiconductor device
KR960036066A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960043176A (en) Capacitor Manufacturing Method
KR960019726A (en) Manufacturing Method of Semiconductor Device
KR960012504A (en) Semiconductor Memory Manufacturing Method
KR940010195A (en) Fine contact formation method for highly integrated devices
KR970053861A (en) Manufacturing Method of Load Register for Semiconductor Device

Legal Events

Date Code Title Description
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid