KR960039145A - Bit line self-aligned contact formation method - Google Patents

Bit line self-aligned contact formation method Download PDF

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Publication number
KR960039145A
KR960039145A KR1019950008280A KR19950008280A KR960039145A KR 960039145 A KR960039145 A KR 960039145A KR 1019950008280 A KR1019950008280 A KR 1019950008280A KR 19950008280 A KR19950008280 A KR 19950008280A KR 960039145 A KR960039145 A KR 960039145A
Authority
KR
South Korea
Prior art keywords
etching
bit line
ion implantation
source
word line
Prior art date
Application number
KR1019950008280A
Other languages
Korean (ko)
Inventor
김대영
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950008280A priority Critical patent/KR960039145A/en
Publication of KR960039145A publication Critical patent/KR960039145A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 고집적 반도체 소자의 비트라인 콘택시 워드라인 간의 간격을 충분히 확보하는 비트라인 자기정렬콘택 형성방법에 관한 것으로, 워드라인용 전도막 및 제1식각장벽물질을 차례로 형성한 후 패터닝하여 워드라인을 디파인(define)하는 단계; 소오스/드레인 이온주입을 위해 워드라인 측벽에 스페이서를 형성하는 단계; 상기패터닝된 워드라인 측벽에 소오스/드레인 형성을 위한 이온주입을 실시하는 단계; 소오스/드레인 이온주입을 실시한후 상기 스페이서를 제거하는 단계; 전체구조 상부에 제2식각장벽물질 및 평탄화 절연막을 차례로 형성하는 단계; 비트라인 콘택 마스크를 사용하여 상기 평탄화 절연막을 식각하고 제2식각장벽물질 비등방성 전면식각하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention relates to a method for forming a bit line self-aligned contact that sufficiently secures a space between word lines in a bit line contact of a highly integrated semiconductor device. Fine defining; Forming a spacer on the sidewall of the wordline for source / drain ion implantation; Performing ion implantation to form a source / drain on the patterned word line sidewalls; Removing the spacers after performing source / drain ion implantation; Sequentially forming a second etching barrier material and a planarization insulating layer on the entire structure; And etching the planarization insulating layer using a bit line contact mask and anisotropically etching the second etching barrier material.

Description

비트라인 자기정렬콘택 형성방법Bit line self-aligned contact formation method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2a도 내지 제2c도는 본 발명의 일실시예에 따른 비트라인 자기 정렬형 콘택 형성 공정도.2A through 2C are bit line self-aligned contact formation process diagrams according to an embodiment of the present invention.

Claims (2)

워드리인용 전도막 및 제1식각장벽물질을 차례로 형성한 후 패터닝하여 워드라인을 디파인(define)하는 단계; 소오드/드레인 이온주입을 위해 워드라인 측벽에 스페이서를 형성한 단계; 상기 패터닝된 워드라인 측벽에 소오스/드레인 형성을 위한 이온주입을 실시하는 단계; 소오스/드레인 이온주입을 실시한후 상기 스페이서를 제거하는 단계; 전체구조 상부에 제2시각장벽물질 및 평탄화 절연막을 차례로 형성하는 단계; 비트라인 콘택 마스크를 사용하여 상기 평탄화 절연막을 식각하고 제2시각장벽물질 비등방성 전면식각하는 단계를 포함하여 이루어지는 것을 특징으로 하는 비트라인 자기정렬콘택 형성방법.Defining a word line by sequentially forming a conductive layer for the word line and a first etching barrier material and then patterning the word line; Forming spacers on the sidewalls of the wordlines for source / drain ion implantation; Performing ion implantation on the patterned word line sidewalls to form a source / drain; Removing the spacers after performing source / drain ion implantation; Sequentially forming a second visual barrier material and a planarization insulating layer on the entire structure; And etching the planarization insulating layer using a bit line contact mask and performing anisotropic front etching of the second visual barrier material. 제1항에 있어서, 상기 제1 및 제2식각장벽물질은 워드라인용 전도막 및 평탄화 절연막과 식각비가 큰 물질인 것을 특징으로 하는 비트라인 자기정렬콘택 형성방법.The method of claim 1, wherein the first and second etching barrier materials are formed of a material having a high etching ratio with the conductive film for the word line and the planarization insulating film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950008280A 1995-04-10 1995-04-10 Bit line self-aligned contact formation method KR960039145A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950008280A KR960039145A (en) 1995-04-10 1995-04-10 Bit line self-aligned contact formation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950008280A KR960039145A (en) 1995-04-10 1995-04-10 Bit line self-aligned contact formation method

Publications (1)

Publication Number Publication Date
KR960039145A true KR960039145A (en) 1996-11-21

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950008280A KR960039145A (en) 1995-04-10 1995-04-10 Bit line self-aligned contact formation method

Country Status (1)

Country Link
KR (1) KR960039145A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100560294B1 (en) * 1998-12-29 2006-06-13 주식회사 하이닉스반도체 Self-aligned contact formation method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100560294B1 (en) * 1998-12-29 2006-06-13 주식회사 하이닉스반도체 Self-aligned contact formation method of semiconductor device

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