KR970013314A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents

Capacitor Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR970013314A
KR970013314A KR1019950026712A KR19950026712A KR970013314A KR 970013314 A KR970013314 A KR 970013314A KR 1019950026712 A KR1019950026712 A KR 1019950026712A KR 19950026712 A KR19950026712 A KR 19950026712A KR 970013314 A KR970013314 A KR 970013314A
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KR
South Korea
Prior art keywords
insulating film
conductive layer
forming
insulating
storage pattern
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KR1019950026712A
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Korean (ko)
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KR0147660B1 (en
Inventor
장규환
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김광호
삼성전자 주식회사
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Priority to KR1019950026712A priority Critical patent/KR0147660B1/en
Publication of KR970013314A publication Critical patent/KR970013314A/en
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Publication of KR0147660B1 publication Critical patent/KR0147660B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

다마신 공정을 이용한 반도체장치의 커패시터 제조방법이 개시되어 있다. 반도체기판 상에 제1 절연막을 형성한 후, 제1 절연막을 소정깊이로 식각하여 스토리지 패턴을 형성한다. 스토리지 패턴을 통해 노출된 제1 절연막 부위를 식각하여 스토리지 패턴의 폭보다 좁은 폭을 갖고 기판의 소정부위를 노출시키는 콘택홀을 형성한다. 결과물 상에 제1 도전층 및 제2 절연막을 차례로 형성한다. 화학기계폴리싱 방법으로 제2 절연막 및 제1 도전층을 폴리싱한 후, 제2 절연막을 제거하여 커패시터 스토리지 전극을 형성한다. 다마신 공정에 의해 커패시터 스토리지전극을 용이하게 패터닝할 수 있다.A method of manufacturing a capacitor of a semiconductor device using a damascene process is disclosed. After forming the first insulating film on the semiconductor substrate, the first insulating film is etched to a predetermined depth to form a storage pattern. The first insulating layer portion exposed through the storage pattern is etched to form a contact hole having a width narrower than that of the storage pattern and exposing a predetermined portion of the substrate. The first conductive layer and the second insulating film are sequentially formed on the resultant. After polishing the second insulating film and the first conductive layer by a chemical mechanical polishing method, the second insulating film is removed to form a capacitor storage electrode. The capacitor storage electrode can be easily patterned by the damascene process.

Description

반체장치의 커패시터 제조방법Capacitor Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1a도 내지 제1f도는 본 발명이 제1 실시예에 의해 반도체장치의 커패시터 제조방법을 설명하기 위한 단면도들.1A to 1F are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the first embodiment of the present invention.

제2a도 내지 제2d도는 본 발명의 제2 실시예에 의한 반도체장치의 커패시터 제조방법을 설명하기 위한 단면도.2A to 2D are cross-sectional views for explaining a capacitor manufacturing method of a semiconductor device according to a second embodiment of the present invention.

Claims (5)

반도체기판상에 제1 절연막을 형성하는 단계 : 상기 제1 절연막을 소정깊이로 식각하여 스토리지 패턴을 형성하는 단계 : 상기 스토리지 패턴을 통해 노출된 제1 절연막 부위를 식각하여 상기 스토리지 패턴의 폭보다 좁은 폭을 갖고 상기 기판의 소정부위를 노출시키는 콘택홀을 형성하는 단계 : 상기 콘택홀이 형성된 결과물 상에 제1 도전층 및 제2 절연막을 차레로 형성하는 단계 : 화학기계폴리싱(CMP)방법으로 상기 제2 절연막 및 제1 도전층을 폴리싱하는 단계 : 및 상기 제2 절연막을 제거하여 커패시터의 스토리지전극을 형성하는 단계를 구비하는 것을 특징으로 하는 반도체장치의 커패시터 제조방법.Forming a first insulating film on a semiconductor substrate: Etching the first insulating film to a predetermined depth to form a storage pattern: Etching the first insulating film portion exposed through the storage pattern narrower than the width of the storage pattern Forming a contact hole having a width and exposing a predetermined portion of the substrate; forming a first conductive layer and a second insulating layer on a resultant product in which the contact hole is formed: by chemical mechanical polishing (CMP) method Polishing the second insulating film and the first conductive layer; and removing the second insulating film to form a storage electrode of the capacitor. 제1항에 있어서, 상기 제2 절연막을 구성하는 물질로 상기 제1 도전층을 구성하는 물질과는 식각유리 다른 물질을 사용하는 것을 특징으로 하는 반도체장치의 커패시터 제조방법.The method of claim 1, wherein a material constituting the second insulating layer is formed of a material different from that of the material constituting the first conductive layer. 제1항에 있어서, 상기 제1 절연막을 커패시터 스토리지전극의 적층 높이만큼 식각하여 상기 스토리지 패턴을 형성하는 것을 특징으로 하는 반도체장치의 커패시터 제조방법.The method of claim 1, wherein the first insulating layer is etched by the stack height of the capacitor storage electrode to form the storage pattern. 제1항에 있어서, CMP 방법으로 상기 제2 절연막 및 제1 도전층을 식각하는 단계 전에, 상기 제2 절연막을 이방성 식각하여 상기 제1 도전층의 단차부에 제2 절연막으로 이루어진 스페이서를 형성하는 단계 : 및 상기 스페이서가 형성된 결과물 상에 제2 도전층 및 제3 절연막을 차례로 형성하는 단계를 더 구비하는 것을 특징으로 하는 반도체장치의 커패시터 제조방법.The method of claim 1, wherein before the etching of the second insulating film and the first conductive layer by a CMP method, the second insulating film is anisotropically etched to form a spacer made of a second insulating film on the stepped portion of the first conductive layer. And forming a second conductive layer and a third insulating film in sequence on the resultant product on which the spacers are formed. 제4항에 있어서, 상기 스페이서, 제2 도전층 및 제3 절연막을 형성하는 단계들을 1회 이상 반복하는 것을 특징으로 하는 반도체장치의 커패시터 제조방법.The method of claim 4, wherein the forming of the spacer, the second conductive layer, and the third insulating layer is repeated one or more times.
KR1019950026712A 1995-08-26 1995-08-26 Manufacturing method of semiconductor capacitor KR0147660B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950026712A KR0147660B1 (en) 1995-08-26 1995-08-26 Manufacturing method of semiconductor capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950026712A KR0147660B1 (en) 1995-08-26 1995-08-26 Manufacturing method of semiconductor capacitor

Publications (2)

Publication Number Publication Date
KR970013314A true KR970013314A (en) 1997-03-29
KR0147660B1 KR0147660B1 (en) 1998-08-01

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100564064B1 (en) * 1997-06-03 2006-07-25 프리스케일 세미컨덕터, 인크. Dual-Layer Integrated Circuit Structure and Formation with Optionally Placed Low-K Dielectric Isolation
KR100833394B1 (en) * 2002-07-05 2008-05-28 매그나칩 반도체 유한회사 Method of forming capacitor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100564064B1 (en) * 1997-06-03 2006-07-25 프리스케일 세미컨덕터, 인크. Dual-Layer Integrated Circuit Structure and Formation with Optionally Placed Low-K Dielectric Isolation
KR100833394B1 (en) * 2002-07-05 2008-05-28 매그나칩 반도체 유한회사 Method of forming capacitor

Also Published As

Publication number Publication date
KR0147660B1 (en) 1998-08-01

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