KR960019540A

KR960019540A - Fine Pattern Formation Method in Manufacturing Semiconductor Device

Info

Publication number: KR960019540A
Application number: KR1019940031598A
Authority: KR
Inventors: 성진모
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1994-11-28
Filing date: 1994-11-28
Publication date: 1996-06-17

Abstract

본 발명은 반도체 소자 제조시 패턴의 크기를 미세하게 형성하는 미세패턴 형성방법에 관한 것으로, 스페이서를 이용한 마스크층으로 패턴 형성하고자 하는 층의 상부에 트랜치를 형성하는 단계; 상기 트랜치를 패턴형성층과 식각선택비가 다른 종류의 층으로 매립하는 단계; 상기 트랜치 매립층을 마스크로 하부의 상기 패턴형성층을 식각하는 단계를 포함하여 이루어짐으로써 고성능의 노광기를 사용하지 않고도 미세선폭의 패턴을 형성할 수 있다.The present invention relates to a fine pattern forming method for finely forming a pattern size when manufacturing a semiconductor device, the method comprising: forming a trench on a layer to be patterned with a mask layer using a spacer; Filling the trench with a layer having a different etching selectivity from the pattern forming layer; Etching the lower portion of the pattern forming layer using the trench buried layer as a mask to form a pattern having a fine line width without using a high-performance exposure machine.

Description

Fine Pattern Formation Method in Manufacturing Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1E도는 본 발명의 일실시예에 따른 미세패턴 형성 공정 단면도.1E is a cross-sectional view of a micropattern forming process according to an embodiment of the present invention.

Claims

Forming a trench on the layer to be patterned with a mask layer using a spacer; Filling the trench with a layer having a different etching selectivity from the pattern forming layer; And etching the pattern forming layer under the trench using the trench buried layer as a mask.

The method of claim 1, wherein the mask layer using the spacer comprises: forming a mask layer on the upper portion of the layer to be patterned to have a line width larger than the size of the pattern actually formed; And forming a spacer on the sidewalls of the mask layer.

The method of claim 1, wherein the filling of the trench comprises: forming a planarization layer on the entire upper surface of the pattern forming layer; And etching the planarization layer to expose the pattern forming layer under the semiconductor device.

The method of claim 2, wherein the pattern forming layer is a polysilicon layer for a gate.

The method of claim 4, wherein the mask layer is an oxide layer.

The method of claim 5, wherein the planarization layer is a BPSG layer.

※ Note: The disclosure is based on the initial application.