KR940004836A - Contact hole formation method of semiconductor device - Google Patents

Contact hole formation method of semiconductor device Download PDF

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Publication number
KR940004836A
KR940004836A KR1019920015520A KR920015520A KR940004836A KR 940004836 A KR940004836 A KR 940004836A KR 1019920015520 A KR1019920015520 A KR 1019920015520A KR 920015520 A KR920015520 A KR 920015520A KR 940004836 A KR940004836 A KR 940004836A
Authority
KR
South Korea
Prior art keywords
insulating layer
forming
contact hole
pattern
layer
Prior art date
Application number
KR1019920015520A
Other languages
Korean (ko)
Inventor
이헌철
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019920015520A priority Critical patent/KR940004836A/en
Publication of KR940004836A publication Critical patent/KR940004836A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 고집적 반도체 소자의 콘택홀 형성방법에 관한 것으로, 선폭이 최소화된 콘택홀을 형성하기 위해 폴리 실리콘층 패턴 상부에 형성되는 절연막 패턴과 절연막 스페이서를 제거하여 폴리실리콘층 패턴 하부의 절연막을 식각하는 플라즈마 식각공정에서 절연막 스페이서에 의한 플라즈마 스캐터링이 발생하지 않도록 하여 안정된 콘택홀을 형성하는 기술이다.The present invention relates to a method for forming a contact hole of a highly integrated semiconductor device, and to remove the insulating film pattern and insulating film spacer formed on the polysilicon layer pattern to form a contact hole with a minimum line width, the insulating film under the polysilicon layer pattern is etched. In the plasma etching process, plasma scattering by the insulating film spacers does not occur, thereby forming a stable contact hole.

Description

반도체소자의 콘택홀 형성방법Contact hole formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2C도는 본 발명에 의해 콘택홀을 형성하는 단계를 도시한 단면도.2A to 2C are cross-sectional views showing steps of forming contact holes according to the present invention.

Claims (1)

실리콘 기판 상부에 워드라인을 형성하고, 워드라인 상부에 제1절연막, 평탄화용 제2절연막을 형성하고, 제2절연막 상부에 폴리실리콘층을 형성한 다음, 워드라인과 워드라인 사이에 미세 선폭의 콘택홀 형성하는 방법에 있어서, 폴리실리콘층 상부에 제3절연막을 형성하고 감광막 패턴을 마스크층으로 사용하여 예정된 콘택영역의 제3절연막을 제거하여 제3절연막 패턴을 형성하는 단계와, 제3절연막 패턴의 측벽에 절연막 스페이서를 형성하고, 제3절연막 패턴과 절연막 스페이서를 마스크층으로 사용하여 노출된 폴리실리콘층을 식각하여 폴리실리콘층 패턴을 형성하는 단계와, 습식식각공정으로 절연막 스페이서와 제3절연막 패턴을 제거하는 단계와, 폴리실리콘층 패턴을 마스크층으로 사용하여 노출된 제2절연막과 제1절연막을 식각하여 콘택홀을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 콘택홀 형성방법.A word line is formed on the silicon substrate, a first insulating layer and a planarization second insulating layer are formed on the word line, a polysilicon layer is formed on the second insulating layer, and a fine line width is formed between the word line and the word line. A method of forming a contact hole, the method comprising: forming a third insulating layer on a polysilicon layer and removing the third insulating layer in a predetermined contact region using a photoresist pattern as a mask layer, and forming a third insulating layer pattern; Forming an insulating layer spacer on the sidewalls of the pattern, etching the exposed polysilicon layer using the third insulating layer pattern and the insulating layer spacer as a mask layer, and forming a polysilicon layer pattern by a wet etching process; Removing the insulating layer pattern and etching the exposed second insulating layer and the first insulating layer using the polysilicon layer pattern as a mask layer; The method of forming contact holes of a semiconductor device, characterized in that comprising the step of forming.
KR1019920015520A 1992-08-28 1992-08-28 Contact hole formation method of semiconductor device KR940004836A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920015520A KR940004836A (en) 1992-08-28 1992-08-28 Contact hole formation method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920015520A KR940004836A (en) 1992-08-28 1992-08-28 Contact hole formation method of semiconductor device

Publications (1)

Publication Number Publication Date
KR940004836A true KR940004836A (en) 1994-03-16

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ID=67147909

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920015520A KR940004836A (en) 1992-08-28 1992-08-28 Contact hole formation method of semiconductor device

Country Status (1)

Country Link
KR (1) KR940004836A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100843903B1 (en) * 2007-03-15 2008-07-03 주식회사 하이닉스반도체 Method for manufacturing of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100843903B1 (en) * 2007-03-15 2008-07-03 주식회사 하이닉스반도체 Method for manufacturing of semiconductor device

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