KR960026568A - Device isolation insulating film manufacturing method of semiconductor device - Google Patents

Device isolation insulating film manufacturing method of semiconductor device Download PDF

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Publication number
KR960026568A
KR960026568A KR1019940037488A KR19940037488A KR960026568A KR 960026568 A KR960026568 A KR 960026568A KR 1019940037488 A KR1019940037488 A KR 1019940037488A KR 19940037488 A KR19940037488 A KR 19940037488A KR 960026568 A KR960026568 A KR 960026568A
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KR
South Korea
Prior art keywords
insulating film
semiconductor device
conductive layer
photoresist pattern
insulating layer
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KR1019940037488A
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Korean (ko)
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KR0146257B1 (en
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이일호
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김주용
현대전자산업 주식회사
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Publication of KR960026568A publication Critical patent/KR960026568A/en
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Publication of KR0146257B1 publication Critical patent/KR0146257B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 반도체소자의 제조방법에 관한 것으로, 반도체기판 상부에 절연막을 형성하고 상기 반도체기판의 비활성영역에만 감광막패턴을 형성한 다음, 상기 감광막패턴을 이용한 식각공정으로 상기 절연막을 식각하고 상기 감광막패턴을 제거한 다음, 전체표면상부에 상기 절연막의 두께보다 두껍게 도전층을 형성하고 에치백공정으로 상기 도전층을 식각하여 상기 절연막과 같은 높이로 평탄화시킴으로써 버즈빅이 발생되지 않아 트랜지스터의 특성을 향상시키고, 후공정에서 발생되는 넛칭을 방지할 수 있으며 공정을 단축시켜 반도체소자의 신뢰성 및 수율을 향상시키고 반도체소자의 생산성을 향상시키는 기술이다.The present invention relates to a method of manufacturing a semiconductor device, wherein an insulating film is formed on a semiconductor substrate, a photoresist pattern is formed only in an inactive region of the semiconductor substrate, and then the insulating film is etched by an etching process using the photoresist pattern and the photoresist pattern After removing the oxide, the conductive layer is formed over the entire surface of the insulating layer to be thicker than the thickness of the insulating layer, and the conductive layer is etched by the etch back process to planarize the same height as the insulating layer, thereby improving the characteristics of the transistor. It is a technology that can prevent the quenching generated in the post process and shorten the process to improve the reliability and yield of the semiconductor device and improve the productivity of the semiconductor device.

Description

반도체소자의 소자분리절연막 제조방법Device isolation insulating film manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1D는 종래기술에 따른 반도체소자의 소자분리절연막 제조공정을 도시한 단면도.1D is a sectional view showing a device isolation insulating film manufacturing process of a semiconductor device according to the prior art.

Claims (5)

반도체기판 상부에 절연막을 형성하는 공정과, 상기 절연막 상부에 감광막패턴을 형성하는 공정과, 상기 감광막패턴을 마스크로하여 상기 절연막을 식각하는 공정과, 상기 감광막패턴을 제거하는 공정과, 전체표면상부에 도전층을 형성하는 공정과, 상기 도전층을 식각함으로써 상기 절연막과 같은 높이로 형성하여 평탄화하는 공정을 포함하는 반도체 소자의 소자분리절연막 제조방법.Forming an insulating film on the semiconductor substrate, forming a photoresist pattern on the insulating film, etching the insulating film by using the photoresist pattern as a mask, removing the photoresist pattern, and overlying the entire surface Forming a conductive layer on the substrate; and forming the conductive layer at the same height as the insulating layer by etching the conductive layer to planarize the insulating layer. 제1항에 있어서, 상기 절연막은 실리콘산화막이 사용되는 것을 특징으로 하는 반도체소자의 소자분리절연막 제조방법.The method of claim 1, wherein a silicon oxide film is used as the insulating film. 제1항에 있어서, 상기 감광막패턴은 상기 반도체기판의 비활성영역에만 형성된 것을 특징으로 하는 반도체소자의 소자분리절연막 제조방법.The method of claim 1, wherein the photosensitive film pattern is formed only on an inactive region of the semiconductor substrate. 제1항에 있어서, 상기 도전층은 상기 절연막보다 두껍게 형성되는 것을 특징으로 하는 반도체소자의 소자 분리절연막 제조방법.The method of claim 1, wherein the conductive layer is formed thicker than the insulating layer. 제1항에 있어서, 상기 도전층은 에치백공정으로 식각되어 상기 절연막과 평탄화되는 것을 특징으로 하는 반도체소자의 소자분리절연막 제조방법.The method of claim 1, wherein the conductive layer is etched by an etch back process to planarize with the insulating layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940037488A 1994-12-27 1994-12-27 Method for manufacturing the insulation film of semiconductor device KR0146257B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940037488A KR0146257B1 (en) 1994-12-27 1994-12-27 Method for manufacturing the insulation film of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940037488A KR0146257B1 (en) 1994-12-27 1994-12-27 Method for manufacturing the insulation film of semiconductor device

Publications (2)

Publication Number Publication Date
KR960026568A true KR960026568A (en) 1996-07-22
KR0146257B1 KR0146257B1 (en) 1998-11-02

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KR1019940037488A KR0146257B1 (en) 1994-12-27 1994-12-27 Method for manufacturing the insulation film of semiconductor device

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