KR960026568A - Device isolation insulating film manufacturing method of semiconductor device - Google Patents
Device isolation insulating film manufacturing method of semiconductor device Download PDFInfo
- Publication number
- KR960026568A KR960026568A KR1019940037488A KR19940037488A KR960026568A KR 960026568 A KR960026568 A KR 960026568A KR 1019940037488 A KR1019940037488 A KR 1019940037488A KR 19940037488 A KR19940037488 A KR 19940037488A KR 960026568 A KR960026568 A KR 960026568A
- Authority
- KR
- South Korea
- Prior art keywords
- insulating film
- semiconductor device
- conductive layer
- photoresist pattern
- insulating layer
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 title abstract description 3
- 238000002955 isolation Methods 0.000 title description 2
- 238000000034 method Methods 0.000 claims abstract 9
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract 6
- 239000000758 substrate Substances 0.000 claims abstract 5
- 238000005530 etching Methods 0.000 claims abstract 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 238000010791 quenching Methods 0.000 abstract 1
- 230000000171 quenching effect Effects 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 반도체기판 상부에 절연막을 형성하고 상기 반도체기판의 비활성영역에만 감광막패턴을 형성한 다음, 상기 감광막패턴을 이용한 식각공정으로 상기 절연막을 식각하고 상기 감광막패턴을 제거한 다음, 전체표면상부에 상기 절연막의 두께보다 두껍게 도전층을 형성하고 에치백공정으로 상기 도전층을 식각하여 상기 절연막과 같은 높이로 평탄화시킴으로써 버즈빅이 발생되지 않아 트랜지스터의 특성을 향상시키고, 후공정에서 발생되는 넛칭을 방지할 수 있으며 공정을 단축시켜 반도체소자의 신뢰성 및 수율을 향상시키고 반도체소자의 생산성을 향상시키는 기술이다.The present invention relates to a method of manufacturing a semiconductor device, wherein an insulating film is formed on a semiconductor substrate, a photoresist pattern is formed only in an inactive region of the semiconductor substrate, and then the insulating film is etched by an etching process using the photoresist pattern and the photoresist pattern After removing the oxide, the conductive layer is formed over the entire surface of the insulating layer to be thicker than the thickness of the insulating layer, and the conductive layer is etched by the etch back process to planarize the same height as the insulating layer, thereby improving the characteristics of the transistor. It is a technology that can prevent the quenching generated in the post process and shorten the process to improve the reliability and yield of the semiconductor device and improve the productivity of the semiconductor device.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1D는 종래기술에 따른 반도체소자의 소자분리절연막 제조공정을 도시한 단면도.1D is a sectional view showing a device isolation insulating film manufacturing process of a semiconductor device according to the prior art.
Claims (5)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940037488A KR0146257B1 (en) | 1994-12-27 | 1994-12-27 | Method for manufacturing the insulation film of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940037488A KR0146257B1 (en) | 1994-12-27 | 1994-12-27 | Method for manufacturing the insulation film of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
KR960026568A true KR960026568A (en) | 1996-07-22 |
KR0146257B1 KR0146257B1 (en) | 1998-11-02 |
Family
ID=19403984
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940037488A KR0146257B1 (en) | 1994-12-27 | 1994-12-27 | Method for manufacturing the insulation film of semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0146257B1 (en) |
-
1994
- 1994-12-27 KR KR1019940037488A patent/KR0146257B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR0146257B1 (en) | 1998-11-02 |
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E701 | Decision to grant or registration of patent right | ||
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FPAY | Annual fee payment |
Payment date: 20090427 Year of fee payment: 12 |
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LAPS | Lapse due to unpaid annual fee |