KR950021130A

KR950021130A - Method for manufacturing contact hole of semiconductor device

Info

Publication number: KR950021130A
Application number: KR1019930031877A
Authority: KR
Inventors: 최양규
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1993-12-31
Filing date: 1993-12-31
Publication date: 1995-07-26

Abstract

본 발명은 반도체 소자의 콘택홀 제조방법에 관한 것으로서, 도전층 패턴으로 된 하부도전층상에 절연층을 형성한 후, 상기 절연층상에 상기 절연층과는 식각선택비차가 있는 물질로 식각정지층을 형성하고, 상기 식각정지층에서 콘택홀로 예정된 부분을 포함하는 큰 범위를 제거하여 식각정지층 패턴을 형성된다. 그 다음 상기 식각정지층 패턴의 측벽에 상기 식각정지층 및 절연층과는 습식 식각선택비차가 있는 물질로 스페이서를 형성한 후, 상기 스페이서를 마스크로 상기 절연층을 이방성식각하여 소정두께 제거하고, 상기 스페이서를 제거한 후, 다시 남아있는 절연층을 경사식각 방법으로 제거하여 콘택홀을 형성하였으므로, 상기 스페이서 및 식각 정지층에 의해 상기 절연층이 별도의 손상없이 제거되어 콘택홀 측벽의 첩점이 45°정도의 경사각을 갖는 매끄러운 구조로 형성되어 후속적층막의 단차피복성이 향상되고, 인접한 도전선과의 단략을 방지하여 반도체 소자의 신뢰성 및 공정수율이 향상된다.The present invention relates to a method for manufacturing a contact hole in a semiconductor device, wherein after forming an insulating layer on a lower conductive layer formed of a conductive layer pattern, an etch stop layer is formed of a material having an etching selectivity difference with the insulating layer on the insulating layer. And a large range including a portion defined as a contact hole in the etch stop layer is formed to form an etch stop layer pattern. Next, a spacer is formed on a sidewall of the etch stop layer pattern with a wet etching selectivity difference between the etch stop layer and the insulating layer, and then the anisotropic etching of the spacer is performed using the spacer to remove a predetermined thickness. After removing the spacer, the remaining insulating layer was removed by the inclined etching method to form a contact hole. The insulating layer was removed without any damage by the spacer and the etch stop layer, so that the contact point of the contact hole sidewall was 45 °. It is formed in a smooth structure having a degree of inclination angle, thereby improving the step coverage of the subsequent laminated film, and preventing shortening with adjacent conductive lines, thereby improving reliability and process yield of the semiconductor device.

Description

Method for manufacturing contact hole of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 (A)~(C)는 본 발명에 따른 반도체 소자의 콘택홀 제조공정도.1 (A) to (C) is a manufacturing process diagram of a contact hole of a semiconductor device according to the present invention.

Claims

Forming an insulating layer of a predetermined material on the lower conductive line, forming an etch stop layer of a material having an etching selectivity difference from the insulating layer on the insulating layer, and exposing a portion of the insulating layer to be a contact hole. Forming an etch stop layer pattern by patterning the etch stop layer so as to form a spacer; forming a spacer on a sidewall of the etch stop layer pattern with a material having a wet etching selectivity difference between the etch stop layer and the insulating layer; And a primary etching step of removing a predetermined thickness of the insulating layer exposed by the spacer by an anisotropic etching method, a step of removing the spacer, and a lower conductive layer using the remaining insulating layer as the mask. Is removed by the inclined etching method so as to form a contact hole that is smoothly inclined at the upper and lower points formed in the primary etching process. A contact hole manufacturing method of a semiconductor device having a tablet.

The method of claim 1, wherein the insulating layer is formed of an oxide film, the etch stop layer is formed of a polysilicon layer, and the spacer is formed of a nitride film.

※ Note: The disclosure is based on the initial application.