KR970053372A - Device Separation Method of Semiconductor Device - Google Patents

Device Separation Method of Semiconductor Device Download PDF

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Publication number
KR970053372A
KR970053372A KR1019950046995A KR19950046995A KR970053372A KR 970053372 A KR970053372 A KR 970053372A KR 1019950046995 A KR1019950046995 A KR 1019950046995A KR 19950046995 A KR19950046995 A KR 19950046995A KR 970053372 A KR970053372 A KR 970053372A
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KR
South Korea
Prior art keywords
pattern
forming
amorphous silicon
layer
film
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KR1019950046995A
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Korean (ko)
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이동덕
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김주용
현대전자산업 주식회사
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Priority to KR1019950046995A priority Critical patent/KR970053372A/en
Publication of KR970053372A publication Critical patent/KR970053372A/en

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Abstract

본 발명은 반도체소자의 소자분리막 제조방법에 관한 것으로, 본 발명은 LOCOS를 응용한 공정 중 질화막스페이서를 이용하여 홈을 형성하는 소자분리막 제조방법에 있어서, 반도체기판 상부에 패드산화막과, 제1질화막을 중착하고, 상기 제1질화막의 상부에 비정질실리콘층를 형성하고, 상기 비정질실리콘층의 상부에 소자분리영역을 형성하기 위한 감광막패턴을 형성하고, 상기 감광막패턴을 사용하여 비정질실리콘패턴과, 제1질화막 패턴 및 패드산화막패턴을 형성하고, 상기 구조의 전 표면에 제2질화막을 형성하고, 상기 제2질화막을 식각하영스페이서를 형성하고, 상기 스페이서를 마스크로 상기 반도체기판을 식각하여 홈을 형성하고, 상기 비정질 실리콘패턴을 제거하고, 상기 홈 부위의 반도체기판을 열산화하여 소자분리막을 형성하고, 상기 제1질화막패턴, 스페이서 및 패드산화막패턴을 제거하므로써, 상기 비정질실리콘층이 질화막패턴과 스페이서 형성시에 식각장벽으로 작용하여 버즈빅의 발생을 방지하고, 중합체류 물질의 제거가 쉽다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation film manufacturing method of a semiconductor device. The present invention relates to a device isolation film manufacturing method for forming grooves using a nitride film spacer during a LOCOS application process, wherein the pad oxide film and the first nitride film are formed on a semiconductor substrate. And a photosensitive film pattern for forming an amorphous silicon layer on top of the first nitride film, and forming an isolation region on the amorphous silicon layer, and using the photosensitive film pattern, an amorphous silicon pattern and a first Forming a nitride layer pattern and a pad oxide layer pattern, forming a second nitride layer on the entire surface of the structure, forming an etch spacer for the second nitride layer, etching the semiconductor substrate with the spacer as a mask to form a groove, Removing the amorphous silicon pattern and thermally oxidizing the semiconductor substrate at the groove to form an isolation layer; By removing the nitride film pattern, the spacer, and the pad oxide film pattern, the amorphous silicon layer acts as an etch barrier at the time of forming the nitride film pattern and the spacer, thereby preventing the occurrence of buzz and easily removing the polymer material.

Description

반도체소자의 소자분리막 제조방법Device Separation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2D도는 본 발명의 실시예에 따른 반도체소자의 소자분리막 제조 공정도.2A through 2D are diagrams illustrating a process of fabricating an isolation layer of a semiconductor device in accordance with an embodiment of the present invention.

Claims (10)

반도체기판 상부레 패드산화막과, 제1질화막을 중착하는 단계와, 상기 제1질화막의 상부에 비정질실리콘층을 형성하는 단계와, 상기 비정질실리콘층의 상부에 소자분리영역을 형성하기 위한 감광막패턴을 형성하는 단계와, 상기 감광막패턴을 사용하여 비정질실리콘패턴과, 제1질화막패턴 및 패드산화막패턴을 형성하는 단계와, 상기 감광막패턴을 제거하는 단계와, 상기 구조의 전 표면에 제2질화막을 형성하는 단계와, 상기 제2질화막을 식각하여 스페이서를 형성하는 단계와, 상기 스페이서를 마스크로 상기 반도체기판을 식각하여 홈을 형성하는 단계와, 상기 비정질실리콘패턴을 제거하는 단계와, 상기 홈 부위의 반도체기판을 열산화하여 소자분리막을 형성하는 단계와, 상기 제1질화막패턴, 스페이서 및 패드산화막패턴을 제거하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 소자분리막 제조방법.Depositing a pad oxide film and a first nitride film on a semiconductor substrate, forming an amorphous silicon layer on the first nitride film, and forming a photoresist layer on the amorphous silicon layer. Forming an amorphous silicon pattern, a first nitride film pattern and a pad oxide film pattern using the photoresist pattern, removing the photoresist pattern, and forming a second nitride film on the entire surface of the structure. Forming a spacer; forming a spacer by etching the second nitride layer; forming a groove by etching the semiconductor substrate using the spacer as a mask; removing the amorphous silicon pattern; Thermally oxidizing the semiconductor substrate to form an isolation layer, and removing the first nitride layer pattern, the spacer, and the pad oxide layer pattern. A device isolation film manufacturing method for a semiconductor device, characterized in that the. 제1항에 있어서, 상기 패드산화막은 50 내지 150Å으로 형성하는 것을 특징으로 하는 반도체소자의 소자분리막 제조방법.The method of claim 1, wherein the pad oxide layer is formed to have a thickness of 50 to 150 GPa. 제1항에 있어서, 상기 제1질화막은 1500 내지 2500Å으로 형성하는 것을 특징으로 하는 반도체소자의 소자분리막 제조방법.The method of claim 1, wherein the first nitride film is formed to have a thickness of 1500 to 2500 kV. 제1항에 있어서,상기 비정질실리콘층은 200 내지 700Å으로 형성하는 것을 특징으로 하는 반도체소자의 소자분리막 제조방법.The method of claim 1, wherein the amorphous silicon layer is formed at 200 to 700 GPa. 제1항에 있어서, 상기 비정질실리콘패턴과, 제1질화막패턴을 형성할 때, 플라즈마 건식식각을 이용하는 것을 특징으로 하는 반도체소자의 소자분리막 제조방법.2. The method of claim 1, wherein plasma dry etching is used to form the amorphous silicon pattern and the first nitride film pattern. 제1항에 있어서, 상기 제2질화막은 100 내지 700Å으로 형성하는 것을 특징으로 하는 반도체소자의 소자분리막 제조방법.The method of claim 1, wherein the second nitride film is formed to have a thickness of 100 to 700 GPa. 제1항에 있어서, 상기 스페이서를 형성할 때, 플라즈마 건식식각을 이용하는 것을 특징으로 하는 반도체소자의 소자분리막 제조방법.2. The method of claim 1, wherein plasma dry etching is used to form the spacers. 제1항에 있어서, 상기 홈을 형성할 때 반도체기판을 200 내지 1000Å 식각하는 것을 특징으로 하는 반도체소자의 소자분리막 제조방법.The method of claim 1, wherein the semiconductor substrate is etched by 200 to 1000 때 when the groove is formed. 제1항에 있어서, 비정질실리콘층이 충분히 얇게 중착될 경우 상기 홈을 형성하는 공정이 생략되는 것을 특징으로 하는 반도체소자의 소자분리막 제조방법.The method of claim 1, wherein the step of forming the groove is omitted when the amorphous silicon layer is sufficiently thin. 제1항에 있어서, 상기 비정질실리콘층의 상부에 ARC막 또는 산화질화막을 형성하는 단계와, 상기 비정질실리콘층의 상부에 ARC막패턴 또는 산화질화막패턴을 형성하는 단계를 추가로 포함하는 것을 특징으로 하는 반도체소자의 소자분리막 제조방법.The method of claim 1, further comprising: forming an ARC film or an oxynitride film on the amorphous silicon layer, and forming an ARC film pattern or an oxynitride film pattern on the amorphous silicon layer. A device isolation film manufacturing method of a semiconductor device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950046995A 1995-12-06 1995-12-06 Device Separation Method of Semiconductor Device KR970053372A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100459693B1 (en) * 1998-03-09 2005-01-15 삼성전자주식회사 Trench isolation method of semiconductor device to prevent gate oxide layer from being deteriorated

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100459693B1 (en) * 1998-03-09 2005-01-15 삼성전자주식회사 Trench isolation method of semiconductor device to prevent gate oxide layer from being deteriorated

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