KR950011172B1 - Method of patterning triple layer photoresist - Google Patents

Method of patterning triple layer photoresist Download PDF

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KR950011172B1
KR950011172B1 KR1019920023046A KR920023046A KR950011172B1 KR 950011172 B1 KR950011172 B1 KR 950011172B1 KR 1019920023046 A KR1019920023046 A KR 1019920023046A KR 920023046 A KR920023046 A KR 920023046A KR 950011172 B1 KR950011172 B1 KR 950011172B1
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South Korea
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film
etching
layer
pattern
photosensitive film
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KR1019920023046A
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Korean (ko)
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KR940016629A (en
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이헌철
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현대전자산업주식회사
김주용
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor

Abstract

The method comprises the steps of coating a bottom photosensitive film; forming a silicon dispersion area through a silicon process under use of a mask pattern; forming an upper photosensitive film by coating a middle SOG film and the upper photosensitive film; etching a thick part in the bottom photosensitive film by etching the middle SOG film through a dry etching process and by etching the bottom photosensitive film through an oxide plasma; etching the silicon dispersion area; and forming a pattern by etching the bottom photosensitive film.

Description

삼층감광막 패턴 형성방법Three-layer photoresist pattern formation method

제 1 도는 삼층감광막 패턴 형성시 단자(topology)에 의하여 하층감광막(Bottom restist)의 두께가 상이한 것을 나타낸 단면도.1 is a cross-sectional view showing that the thickness of the bottom rest film is different depending on the topology when the three-layer film pattern is formed.

제 2a 도 내지 제 2e 도는 본 발명의 공정방법에 의하여 삼층감광막 패턴을 형성한 단면도.2A to 2E are cross-sectional views of a three-layer photosensitive film pattern formed by the process method of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘 기판 2 : 폴리실리콘 패턴1: silicon substrate 2: polysilicon pattern

3 : 패턴이 형성될 막 4 : 하층감광막(bottom resist)3: film on which pattern is to be formed 4: bottom photoresist (bottom resist)

5 : 중간층 SOG(spin-on-glass) 6 : 상층감광막(Top trsist)5: middle layer spin-on-glass 6: top photoresist (top trsist)

7 : 실리콘 확산영역 8 : 실리콘 산화막(sio2)7 silicon diffusion region 8 silicon oxide film (sio 2 )

9 : 마스크(Mask) 10 : 자외선9: mask 10: ultraviolet light

본 발명은 반도체소자의 삼층감광막 패턴 형성방법에 관한 것으로, 특히 삼층감광막 공정에서 단차에 의하여 발생하는 하층감광막(bottom resist)의 두께 차이를 실리레이션(silylation) 공정을 도입하여 감소시키는 삼층감광막 패턴 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a three-layer photoresist pattern of a semiconductor device, and in particular, to form a three-layer photoresist pattern for reducing a thickness difference of a bottom resist caused by a step in a three-layer photoresist process. It is about a method.

반도체 소자의 패턴 형성을 위하여 사용되고 있는 삼층감광막 공정은 단위(cell) 면적의 감소에 따른 단차에 의하여 하층감광막의 두께 차이가 증가되고 있으며 하층감광막의 패턴 형성을 위하여 식각할때 가장 두꺼운 부분을 기준으로 식각하게 되므로 과도식각(overetch)으로 인하여 단차가 높은부분(하층감광막의 두께가 낮은부분)과 단차가 낮은부분(하층감광막의 두께가 두꺼운부분)에서 동시에 선폭을 제어하는 어려움이 있다.In the three-layer photoresist process used for pattern formation of semiconductor devices, the difference in thickness of the lower photoresist layer is increased due to the step difference due to the decrease of the cell area, and based on the thickest part when etching for the pattern formation of the lower photoresist layer. Because of etching, due to overetching, there is a difficulty in controlling the line width at the same time in the high step portion (low thickness layer) and the low step portion (thick layer thickness).

따라서, 본 발명에서는 단차가 높은부분에 하층감광막을 도포한후 마스크를 이용하여 실리레이션(silylaton) 공정을 도입하여 부분적으로 실리레이션함으로써 과도식각에 의한 하층감광막의 패턴불량을 방지하는데 그 목적이 있다.Therefore, in the present invention, the lower photoresist film is applied to a portion having a high step, and then a silicide is introduced by using a mask to partially silicify to prevent a pattern defect of the lower photoresist film due to excessive etching. .

이하, 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail.

제 1 도는 실리콘 기판(1)에 폴리실리콘 패턴(2)를 형성하고, 전체적으로 패턴이 형성될 막(4)을 증착한후, 하층감광막(5), 중간층 SOG(6), 및 상층감광막(7)을 형성한 단면도로서, 단차가 높은부분(a)은 하층감광막(5)의 두께가 낮으며 단차가 낮은부분(b)은 상대적으로 하층감광막의 두께가 두꺼워짐을 나타내고 있다.1 shows a polysilicon pattern 2 formed on a silicon substrate 1, and after depositing a film 4 on which a pattern is to be formed as a whole, a lower photosensitive film 5, an intermediate layer SOG 6, and an upper photosensitive film 7 ), The portion having a high step (a) has a low thickness of the lower photosensitive film 5, and the portion having a low step has a relatively thick thickness of the lower photosensitive film.

제 2a 도 내지 도 2e 도는 본 발명의 삼층감광막 형성방법에 의하여 형성된 패턴의 단면도로서, 제 2a 도는 실리콘 기판(1) 상부에 폴리실리콘 패턴(2)을 형성하고, 그 상부에 패턴이 형성될 층(4) 예를들어 도전층이나 절연막을 적층한후 하층감광막(5)을 도포하고 마스크(10)를 이용하여 단차가 높은부분(a), 즉 하층감광막(5)의 두께가 얇은 부분만 실리레이션 공정을 실시하여 실리콘 확산영역(8)을 형성한 단면도이다.2A to 2E are cross-sectional views of a pattern formed by the method of forming a three-layer photosensitive film of the present invention. FIG. 2A is a layer on which a polysilicon pattern 2 is formed on a silicon substrate 1 and a pattern is formed thereon. (4) For example, after laminating a conductive layer or an insulating film, the lower photosensitive film 5 is applied and only a portion of the high step (a), that is, the thin portion of the lower photosensitive film 5 is applied using the mask 10. It is sectional drawing which carried out the formation process and formed the silicon | silicone diffusion region 8.

제 2b 도는 실리레이션 공정을 진행한 상부에 중간층 SOG(6)막과 상층감광막(7)을 도포한후 노광 및 현상공정을 실시하여 상층감광막 패턴을 형성한 단면도이다.FIG. 2B is a cross-sectional view of the upper photosensitive film pattern formed by applying an intermediate layer SOG 6 film and an upper photosensitive film 7 to the upper part where the silicide process is performed, followed by an exposure and development process.

제 2c 도는 상층감광막(7)을 마스크하여 중간층 SOG(6)을 건식식각방법으로 식각한 단면도이다.2C is a cross-sectional view of the intermediate layer SOG 6 etched by the dry etching method by masking the upper photosensitive film 7.

제 2d 도는 산소플라즈마를 이용하여 하층감광막(5)을 부분적으로 건식식각한 단면도이며, 단차가 높은부분과 낮은부분에서의 하층감광막의 두께가 같은 부분까지 식각하며, 실리콘 확산영역(8)은 산소플라즈마에 의하여 실리콘산화막(9)을 형성하여 하층감광막이 식각되지 않으며 단차가 낮은부분, 즉 하층감광막의 두께가 두꺼운 부분만 식각이 진행된다.FIG. 2D is a cross-sectional view partially dry-etched the lower layer photoresist film 5 using an oxygen plasma, and etches the portion of the lower layer photoresist film at the same level as the high step and the lower part to the same thickness. The silicon oxide film 9 is formed by plasma, so that the lower photoresist film is not etched, and only the portion where the step difference is low, that is, the thick portion of the lower photoresist film, is etched.

제 2e 도는 Cx, Fy계의 플라즈마를 이용하여 단차가 낮은부분의 실리콘산화막(9)을 식각하여 제거하고 다시 산소플라즈마를 이용하여 하층감광막(5)을 식각하여 패턴을 형성한 단면도이다.FIG. 2E is a cross-sectional view of the silicon oxide film 9 having a low level difference removed using C x and F y plasmas, and the lower layer photosensitive film 5 is etched using oxygen plasma to form a pattern.

본 발명에 의하면 삼층감광막 패턴 형성공정시 단차가 높은부분, 즉 하층감광막위 두께가 낮은부분에만 실리레이션 공정을 부분적으로 도입함으로써 단차에 의하여 발생하는 하층감광막의 두께 차이를 감소시켜 단차가 높은부분과 단차가 낮은부분을 동시에 과도식각(overetch)을 가능하게 하여 선폭제어를 용이하게 할 수 있을뿐 아니라 하층에 대한 식각손상(damage)등을 방지할 수 있다.According to the present invention, in the three-layer photoresist pattern forming process, the silicide process is partially introduced only in a portion having a high step, that is, a portion having a low thickness on the lower photoresist film, thereby reducing the difference in thickness of the lower photoresist film generated by the step, and thus the step having high It is possible to overetch the low step at the same time to facilitate the line width control and to prevent the etching damage to the lower layer.

Claims (1)

실리콘기판 상부에 도전층 및 절연층에 의해 단차를 갖는 패턴을 형성될 막 상부에 하층감광막, 중간층 SOG, 상층감광막을 도포하는 삼층감광막 패턴 형성방법에 있어서, 하층감광막을 도포하고 마스크 패턴을 이용하여 단차가 높은부분만 실리레이션 공정을 실시하여 실리콘 확산영역을 형성하는 단계와, 그 상부에 중간층 SOG막과 상층감광막을 도포하고 상층감광막 패턴을 형성하는 단계와, 중간층 SOG막을 건식식각방법으로 식각하고 산소플라즈마를 이용하여 하층감광막의 일정부분을 식각하되 실리콘 확산영역의 단차가 높은부분을 식각되지 않고 단차가 낮은부분, 즉 하층감광막의 두께가 두꺼운 부분만 식각하는 단계와, Cx, Fy플라즈마를 이용하여 단차가 높은부분의 실리콘 확산영역의 산화막을 식각하는 단계와, 다시 산소플라즈마를 이용하여 하층감광막을 식각하여 패턴을 형성하는 단계로 이루어진 반도체 소자의 삼층감광막 패턴 형성방법.In the method of forming a three-layer photoresist pattern in which a lower photoresist film, an intermediate layer SOG, and an upper photoresist film are applied over a film on which a pattern having a step is formed by a conductive layer and an insulating layer on a silicon substrate, a lower photoresist film is applied and a mask pattern is used. Forming a silicon diffusion region by performing a silicide process only on a portion having a high step, applying an intermediate SOG film and an upper photosensitive film on the upper part thereof, forming an upper photosensitive film pattern, and etching the intermediate SOG film by dry etching. Etching a portion of the lower photoresist layer using an oxygen plasma, but not etching a portion having a high step difference in the silicon diffusion region, but etching only a portion having a low step thickness, that is, a thick portion of the lower photoresist film, and C x , F y plasma Etching the oxide film in the silicon diffusion region of the high step portion by using the step, and again using the oxygen plasma W three-layer photosensitive film pattern forming method of the semiconductor device by etching a lower layer made of a photosensitive film to form a pattern.
KR1019920023046A 1992-12-02 1992-12-02 Method of patterning triple layer photoresist KR950011172B1 (en)

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KR1019920023046A KR950011172B1 (en) 1992-12-02 1992-12-02 Method of patterning triple layer photoresist

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KR950011172B1 true KR950011172B1 (en) 1995-09-28

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KR100427720B1 (en) * 2002-07-18 2004-04-28 주식회사 하이닉스반도체 A method for forming a metal line of semiconductor device

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