KR100338091B1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR100338091B1 KR100338091B1 KR1019950041446A KR19950041446A KR100338091B1 KR 100338091 B1 KR100338091 B1 KR 100338091B1 KR 1019950041446 A KR1019950041446 A KR 1019950041446A KR 19950041446 A KR19950041446 A KR 19950041446A KR 100338091 B1 KR100338091 B1 KR 100338091B1
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- film
- contact hole
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- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 229920005591 polysilicon Polymers 0.000 claims abstract description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 11
- 239000010703 silicon Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000001312 dry etching Methods 0.000 claims abstract description 10
- 238000001039 wet etching Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims description 17
- 239000002184 metal Substances 0.000 abstract description 9
- 239000010408 film Substances 0.000 description 58
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 10
- 239000005380 borophosphosilicate glass Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 9
- 239000010409 thin film Substances 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 콘택 홀 형성 공정시에 콘택 홀 측벽의 경사를 완만하게 형성하도록 한 반도체 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a slope of a contact hole sidewall is formed smoothly during a contact hole forming step.
일반적으로 반도체 소자의 콘택 홀 형성 공정에 있어서, 콘택홀을 형성하기 위해, 실리콘 기판상에 임의의 박막을 증착하여, 콘택 마스크를 이용한 건식 및 습식 식각 공정을 실시한다. 이러한 종래의 공정을 제 1A 및 1B 도를 통해 설명하면 다음과 같다.In general, in the process of forming a contact hole in a semiconductor device, an arbitrary thin film is deposited on a silicon substrate to form a contact hole, and dry and wet etching processes using a contact mask are performed. This conventional process will be described with reference to FIGS. 1A and 1B as follows.
제 1A 도와 관련하여, 실리콘기판상(1)에 산화막(5)이 증착되고, 전체 상부에 감광막(4)이 얇게 도포(Coating)된 후 상기 감광막(4)이 마스크를 통한 노광에 의해 패터닝 된다. 상기 패터닝된 감광막(4)을 마스크로 이용하여 등방성 습식 식각 공정으로 산화막(5)을 일정한 비율로 소정 깊이 식각한 후, 상기 산화막(5)을 건식 식각하여 콘택홀(7)을 형성시킨다. 이와 같은 식각 공정은 수직 방향과 수평 방향의 식각 속도의 차이에 따라 콘택홀(7) 측면부(A)에 급격한 경사가 형성되어 금속(9)을 증착시 콘택홀(7)하부에 보이드(8)가 생성되어 금속(9)의 스텝 커버리지(Step Coverage)를 저하시키는 단점이 있다.In connection with the first A diagram, an oxide film 5 is deposited on the silicon substrate 1, the photoresist film 4 is coated thinly on the whole, and then the photoresist film 4 is patterned by exposure through a mask. . Using the patterned photoresist film 4 as a mask, the oxide film 5 is etched at a predetermined depth by an isotropic wet etching process, and then the oxide film 5 is dry-etched to form a contact hole 7. In such an etching process, a sharp inclination is formed in the side surface portion A of the contact hole 7 according to the difference in the etching speed in the vertical direction and the horizontal direction, so that when the metal 9 is deposited, the void 8 is formed under the contact hole 7. Is generated to lower the step coverage of the metal 9.
제 1B 도와 관련하여, 실리콘기판상(1)에 산화막 및 폴리 실리콘이 증착되고, 제 1 차 신화막(5A) 및 폴리 실리콘층(6)이 형성된다. 전체 상부에 감광막(4)이 얇게 도포(Coating)된 후 감광막(4)이 마스크를 통한 노광에 의해 패터닝된다. 상기 패터닝된 감광막(4)을 마스크로 이용하여 폴리 실리콘층(6)을 패터닝 하고, 전체 상부면에 제 2 차 산화막(5B)을 증착한 후 등방성 습식 식각공정으로 제 2 차 산화막(5B)은 일정한 비율로 소정 깊이 식각된다. 상기 제 1 차 및 제 2 차산화막(5A 및 5B)에 마스크를 이용한 건식 식각으로 콘택홀(7)이 형성된다. 이러한 식각 공정시 수직 방향과 수평 방향의 식각 속도의 차이에 따라 콘택홀 측면부가 과도한 식각이 되는 경우, 폴리 실리콘층(6)이 노출될 수 있으며, 또한 금속(9)을 증착시 콘택홀(7)하부에 보이드(8)가 생성되어 금속(9)의 스텝 커버리지를 저하시키며 접합영역과 금속(9)과의 접촉시 접촉저항(Contact Resistance)을 증가시켜 소자의 전기적 특성을 저하시키는 단점이 있다.In connection with the first B diagram, an oxide film and polysilicon are deposited on the silicon substrate 1, and the primary thin film 5A and the polysilicon layer 6 are formed. After the photoresist film 4 is coated thinly on the whole, the photoresist film 4 is patterned by exposure through a mask. The polysilicon layer 6 is patterned by using the patterned photoresist film 4 as a mask, the secondary oxide film 5B is deposited on the entire upper surface, and the secondary oxide film 5B is then subjected to an isotropic wet etching process. A predetermined depth is etched at a constant rate. Contact holes 7 are formed in the first and second secondary oxide films 5A and 5B by dry etching using a mask. In this etching process, when the contact hole side portion is excessively etched due to the difference in the etching speed in the vertical direction and the horizontal direction, the polysilicon layer 6 may be exposed, and the contact hole 7 may be exposed when the metal 9 is deposited. Voids 8 are formed on the bottom to reduce the step coverage of the metal 9 and to increase the contact resistance during contact between the junction region and the metal 9, thereby degrading the electrical characteristics of the device. .
따라서, 본 발명은 콘택 홀을 형성하는데 있어서, 콘택 홀 측벽의 경사를 완만하게 형성하여 금속의 스텝 커버리지를 개선할 수 있는 반도체 소자 제조 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving the step coverage of a metal by gently forming the slope of the contact hole sidewall in forming the contact hole.
상기한 목적을 달성하기 위한 본 발명은 실리콘기판상에 BPSG막 및 TEOS막을 증착하고, 패터닝 된 감광막을 마스크로 이용하여 등방성 습식 식각공정으로 TEOS막 및 BPSG막을 일정한 비율로 소정 깊이 식각하는 단계와, 상기 노출된 잔류 BPSG막을 건식 식각하여, 콘택홀을 형성하는 것을 특징을 특징으로 한다.The present invention for achieving the above object is a step of depositing a BPSG film and TEOS film on a silicon substrate, using a patterned photosensitive film as a mask to etch a predetermined depth of the TEOS film and BPSG film in a constant ratio by an isotropic wet etching process, And dry etching the exposed residual BPSG film to form a contact hole.
또한, 본 발명은 실리콘기판상에 산화막 및 폴리 실리콘을 순차적으로 증착하고, 패터닝 된 감광막을 마스크로 이용하여 건식 식각공정으로 폴리 실리콘층을 식각 하는 단계와, 상기 감광막을 제거한 후, 산화막을 등방성 습식 식각 공정으로 일정한 비율로 소정 깊이 식각하는 단계와, 상기 건식 식각 공정으로 산화막을 식각하여 콘택홀을 형성하는 것을 특징으로 한다.The present invention also sequentially deposits an oxide film and polysilicon on a silicon substrate, etching the polysilicon layer by a dry etching process using the patterned photosensitive film as a mask, and removing the photosensitive film, and then isotropically wets the oxide film. Etching a predetermined depth at a predetermined ratio in the etching process, and forming a contact hole by etching the oxide film by the dry etching process.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제 2A 내지 2D도는 본 발명의 제 1 실시예에 따른 반도체 소자 제조 방법을설명하기 위한 단면도이다.2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
제 2A 도와 관련하여, 실리콘기판상(1)에 BPSG막(2) 및 TEOS막(3)이 7 : 3의 두께의 비율로 증착되고, 전체 상부에 감광막(4)이 얇게 도포(Coating)된후 상기 감광막(4)이 마스크를 통한 노광에 의해 패터닝 된다.In relation to the second A diagram, after the BPSG film 2 and the TEOS film 3 are deposited on the silicon substrate 1 in a ratio of a thickness of 7: 3, the photoresist film 4 is coated thinly on the whole. The photosensitive film 4 is patterned by exposure through a mask.
제 2B 도와 관련하여, 상기 패터닝된 감광막(4)이 마스크로 이용되어 등방성 습식 식각공정으로 상기 TEOS막(3)이 일정한 비율로 소정 깊이 식각된다.In connection with the second B diagram, the patterned photoresist film 4 is used as a mask so that the TEOS film 3 is etched to a predetermined depth by an isotropic wet etching process.
제 2C 도와 관련하여, 상기 TEOS막(3)이 일정한 비율로 소정 깊이 식각이 된 후 상기 TEOS막(3) 하부에 형성된 BPSG막(2)이 식각이 된다. 상기 BPSG 막(2)은 TEOS막(3) 보다 동일 시간에 식각되는 속도가 늦게 된다. 이로 인하여 상기 BPSG막(2) 및 TEOS막(3)의 식각된 부분은 식각 속도의 차이로 인해 완만한 경사의 형태로 형성된다.In relation to the second C diagram, after the TEOS film 3 is etched at a predetermined depth by a predetermined ratio, the BPSG film 2 formed under the TEOS film 3 is etched. The BPSG film 2 is slower than the TEOS film 3 to be etched at the same time. As a result, the etched portions of the BPSG film 2 and the TEOS film 3 are formed in the form of a gentle slope due to the difference in etching speed.
제 2D 도와 관련하여, 상기 패터닝된 감광막(4)이 마스크로 이용되어 TEOS막(3) 하부에 형성된 BPSG막(2)이 건식 식각된다. 상기 건식 식각된 BPSG 막(2)에 콘택홀(7)이 형성된다.Regarding the 2D diagram, the patterned photoresist film 4 is used as a mask so that the BPSG film 2 formed under the TEOS film 3 is dry etched. A contact hole 7 is formed in the dry etched BPSG film 2.
제 3A 내지 3C도는 본 발명의 제 2 실시예에 따른 반도체 소자 제조 방법을 설명하기 위한 단면도이다.3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
제 3A 도와 관련하여, 실리콘기판상(1)에 산화막(5)이 증착되고, 상기 산화막(5)상에 폴리 실리콘이 800℃이상의 온도에서 1000Å 내지 2000Å의 두께로 증착된다. 상기 폴리 실리콘층(6)상에 감광막(4)이 얇게 도포(Coating)되고, 상기 감광막(4)이 마스크를 통한 노광에 의해 패터닝 된다. 상기 폴리 실리콘층(6)과산화막(5)의 계면 원자는 온도에 의해 강하게 결합된다.In connection with the third A diagram, an oxide film 5 is deposited on the silicon substrate 1, and polysilicon is deposited on the oxide film 5 at a thickness of 1000 kPa to 2000 kPa at a temperature of 800 deg. The photosensitive film 4 is coated on the polysilicon layer 6 in a thin coating, and the photosensitive film 4 is patterned by exposure through a mask. The interfacial atoms of the polysilicon layer 6 and the oxide film 5 are strongly bonded by temperature.
제 3B 도와 관련하여, 상기 패터닝된 감광막(4)이 마스크로 이용되어 긴식 식각공정에 의해 폴리 실리콘층(6)이 식각 된다. 상기 감광막(4)이 제거된 된 후, 산화막(5)이 등방성 습식 식각 공정으로 산화막이 일정한 비율로 소정 깊이 식각된다. 상기 산화막(5)은 폴리 실리콘층(6)과의 원자 결합이 강하므로 식각시 속도면에서 수직 방향(a)의 식각 속도가 수평 방향(b)의 식각 속도 보다 빠르므로 수직 방향(a)의 식각이 더 커지게 되므로서 하부층의 노출을 방지하게 된다.In connection with the third B diagram, the patterned photoresist film 4 is used as a mask to etch the polysilicon layer 6 by a long etching process. After the photosensitive film 4 is removed, the oxide film 5 is etched to a predetermined depth at a constant rate by an isotropic wet etching process. Since the oxide film 5 has a strong atomic bond with the polysilicon layer 6, the etching speed of the vertical direction (a) is faster than the etching speed of the horizontal direction (b) in terms of speed during etching. The etching becomes larger, which prevents the underlying layer from being exposed.
제 3C 도와 관련하여, 상기 폴리 실리콘층(6)이 마스크로 이용되어 건식 식각 공정에 의해 산확막(5)이 식각된다. 상기 산화막(5)에 콘택홀(7)이 형성된 후, 상기 폴리 실리콘층(6)은 제거된다.With respect to the third C diagram, the diffusion layer 5 is etched by the dry etching process using the polysilicon layer 6 as a mask. After the contact hole 7 is formed in the oxide film 5, the polysilicon layer 6 is removed.
상술한 바와 같이 본 발명에 의하면 실리콘 기판상에 형성된 산화막에 콘택홀을 형성하기 위한 식각 공정시 식각 속도의 차이를 이용하여 콘택홀의 측면부의 경사를 완만하게 형성하고, 측면부의 과도한 식각을 방지하여 금속 스텝 커버리지 및 소자의 전기적 특성을 향상시킬 수 있는 탁월한 효과가 있다.As described above, according to the present invention, in the etching process for forming the contact hole in the oxide film formed on the silicon substrate, the inclination of the side part of the contact hole is gently formed by using the difference in the etching rate, and the excessive side part of the metal is prevented from being etched. There is an excellent effect to improve the step coverage and the electrical characteristics of the device.
제 1A 및 1B 도는 종래의 반도체 소자 제조 방법을 설명하기 위한 단면도.1A and 1B are cross-sectional views illustrating a conventional semiconductor device manufacturing method.
제 2A 내지 2D 도는 본 발명의 제 1 실시예에 따른 반도체 소자 제조방법을 설명하기 위한 단면도.2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
제 3A 내지 3C 도는 본 발명의 제 2 실시예에 따른 반도체 소자 제조방법을 설명하기 위한 단면도.3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 : 실리콘 기판 2 : BPSG 막1: silicon substrate 2: BPSG film
3 : TEOS 막 4 : 감광막3: TEOS film 4: photosensitive film
5 : 산화막 5A : 제 1 차 산화막5: oxide film 5A: primary oxide film
5B : 제 2 차 산화막 6 : 폴리 실리콘층5B: secondary oxide film 6: polysilicon layer
7 : 콘택홀 8 : 보이드(Void)7: contact hole 8: void
9 : 금속9: metal
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950041446A KR100338091B1 (en) | 1995-11-15 | 1995-11-15 | Method for manufacturing semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019950041446A KR100338091B1 (en) | 1995-11-15 | 1995-11-15 | Method for manufacturing semiconductor device |
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| Publication Number | Publication Date |
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| KR970030382A KR970030382A (en) | 1997-06-26 |
| KR100338091B1 true KR100338091B1 (en) | 2002-11-04 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0536652A (en) * | 1991-07-29 | 1993-02-12 | Oki Electric Ind Co Ltd | Through hole forming method |
| JPH0745551A (en) * | 1993-07-27 | 1995-02-14 | Matsushita Electron Corp | Forming method of contact hole |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0536652A (en) * | 1991-07-29 | 1993-02-12 | Oki Electric Ind Co Ltd | Through hole forming method |
| JPH0745551A (en) * | 1993-07-27 | 1995-02-14 | Matsushita Electron Corp | Forming method of contact hole |
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