KR980012266A - Device isolation method of semiconductor device - Google Patents

Abstract

A device isolation method for a novel semiconductor device is disclosed. A buffer layer, an etching stop layer, and a photoresist are sequentially formed on the semiconductor substrate. After patterning the photoresist, the substrate is etched using the resist as an etching mask to form a trench. The trenches are filled with an insulating film and polished by a CMP method to realize primary planarization. And the insulating film is etched by a dry etching method using the etching stop layer as an etching end point to realize secondary planarization. The etch stop layer and the buffer layer are removed. It is possible to solve the dishing phenomenon and the nonuniformity of the polishing amount, which have been problematic when using only the CMP method.

Description

Device isolation method of semiconductor device

The present invention relates to a device isolation method of a semiconductor device and more particularly to a trench device isolation process for realizing planarization using chemical mechanical polishing (hereinafter referred to as "CMP"), dishing phenomenon and a problem of nonuniformity of polishing amount.

In a semiconductor circuit, it is necessary to electrically isolate various elements such as transistors, diodes, and resistors formed on a semiconductor substrate. As a device isolation method, LOCAL Oxidation of Silicon (LOCOS) is most commonly used. However, as the semiconductor device is highly integrated, the isolation region between the devices has been reduced. As a result, the LOCOS method has a problem of Bird's beak due to lateral oxidation, crystal defects of the substrate silicon due to the buffer layer stress caused by the thermal process, The problem of redistribution of impurities implanted for blocking has been a difficult point in the trend of electrical characteristics and high integration of semiconductor devices.

As an alternative to the LOCOS method, a method of isolating a trench device, which breaks an element isolation region and fills an insulating material such as a chemical vapor deposition (hereinafter referred to as "CVD") oxide film, has been spotlighted. The trench isolation method can roughly be divided into a step of forming a trench by etching a semiconductor substrate, a step of filling the trench with a CVD oxide film, and a step of realizing planarization, and each step has inherent problems. That is, when an insulating film such as a CVD oxide film is buried in the trench, the profile of the buried oxide film is uneven in a wide trench pattern, leading to unstable device isolation characteristics and a partial structural step.

On the other hand, the process for realizing the planarization was changed from the conventional dry etching method to the CMP method, and the process simplification and planarization ability were greatly improved. The CMP method is considered to be ideal as a trench filling and etching method because it removes an insulating film for buried trenches formed on a semiconductor substrate (wafer) in the lateral direction. However, if the substrate (wafer) before the CMP process has a poor flatness, Even after this, the center of the wide trench area is shaped like a dish, resulting in a dishing phenomenon of the pie, and the flatness is lowered. In addition, since the material used as the CMP blocking layer has a large difference in polishing rate from the CVD oxide film as the trench filling material, the termination of the CMP process is searched depending on the time, and the polishing amount becomes nonuniform, There is a great difference in sex.

In order to minimize the dishing phenomenon and the thickness nonuniformity after CMP, the thickness step before CMP should be minimized. Many methods have been proposed for this, and IBM has proposed a method of applying a flat photoresist (PR) and etching back it before performing the CMP process. In addition, the present applicant (inventor: Tae Soo Park) filed a Korean patent application No. 94-14743 for a method of forming a device isolation region using the LOCOS method and the trench method together to minimize the initial step before the CMP process, . However, the above-described methods are not only complicated but also cause process variations according to process variables during various processes, resulting in uniformity.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a semiconductor device capable of solving the problems of dishing phenomenon and polishing amount nonuniformity after CMP by using a dry etching method, Separating method.

1 to 6 are cross-sectional views for explaining a device isolation method of a semiconductor device according to the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

10: semiconductor substrate 12: buffer layer

14: etch stop layer 15: photoresist

16: Trench 18: CVD oxide film

According to an aspect of the present invention, there is provided a method of isolating a semiconductor device, the method comprising: sequentially forming a buffer layer, an etching stop layer, and a photoresist on a semiconductor substrate; Patterning the photoresist and etching the substrate using the photoresist as an etching mask to form a trench; Filling the trench with an insulating film and polishing the trench by a CMP method to realize a first planarization; Etching the insulating layer using a dry etching method using the etching stop layer as an etching end point to realize a second planarization; And removing the etch stop layer and the buffer layer.

According to a preferred embodiment of the present invention, there is further provided a step of forming an oxide film on the sidewall of the trench by performing an oxidation process after forming the trench.

The insulating film for filling the trench is preferably formed by depositing a CVD oxide film to a thickness of 500 Å or less.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 6 are cross-sectional views for explaining a device isolation method of a semiconductor device according to the present invention.

Figure 1 shows the steps of forming the buffer layer 12 and the etch stop layer 14. Specifically, an oxide-based film is deposited as the buffer layer 12 on the semiconductor substrate 10, for example, a silicon substrate. The buffer layer 12 acts as a stress buffer between the film to be formed thereon and the substrate 10. Then, an etch stop layer 14 is formed on the buffer layer 12 to a thickness of 500 Å or less. Here, the etch stop layer 14 serves as an etch stop for the subsequent planarization dry etching process. In the prior art, the etch stop layer 14 is thickly deposited to define an active region and to use it as a mask for trench etching. However, in the present invention, the definition of an active region and the use of a trench etch mask as a photoresist to be formed thereon Therefore, the etch stop layer 14 can be formed very thin. When the etch stop layer 14 is formed thin, the aspect ratio is reduced when the trench is buried in the CVD oxide film in the subsequent process, so that the buried characteristics are improved and the initial step before the CMP process is reduced.

Next, on the etch stop layer 14, the photoresist 15 to be used as a mask for defining the active region and etching the trench is applied.

Referring to FIG. 2, an active region is defined by exposing and developing the photoresist 15 to form a photoresist pattern 15a. Subsequently, the trench 16 is formed by etching a predetermined region of the exposed substrate 10 using the photoresist pattern 15a as an etching mask. In the conventional method, a trench etching mask layer and a photoresist are coated on a substrate, the photoresist is patterned, and the mask layer is etched using the photoresist. Then, the photoresist is removed, The trenches are formed by etching. On the other hand, in the present invention, by using a photoresist directly as a mask for trench etching, the process can be simplified, and a large amount of polymer is generated when the trench is etched to lie on each trench, which can contribute to improve the characteristics of the transistor . Further, when the trench is buried in the CVD oxide film in the subsequent process, the buried capability of the CVD oxide film in the wide trench region is improved, and voids or seams that may occur during burial can be removed.

Referring to FIG. 3, after the photoresist pattern 15a is removed, a thermal oxidation process is performed to form an oxide film 17 on the sidewalls of the trench 16. Then, an insulating film such as a CVD oxide film 18 is deposited on the entire surface of the resultant to such a thickness that the trench 16 can be sufficiently filled.

Referring to FIG. 4, the CVD oxide film 18 is polished by a CMP method to achieve primary planarization. At this time, the end point of the CMP process is located at a certain point on the etch stop layer 14, and the CMP process is performed by designating the time.

Referring to FIG. 5, the CVD oxide film 18 is etched by a dry etching method to accurately etch the etch stop layer 14, thereby realizing secondary planarization. At this time, the end point detection of the dry etching process is performed in the etch stop layer 14 already deposited. This is performed using an end point detection (hereinafter referred to as "EPD") rather than a simple time etching. You can find the etch endpoint.

Referring to FIG. 6, the etch stop layer 14 and the buffer layer 12 are removed by a wet etching method, thereby completing the trench element isolation region 20.

As described above, according to the present invention, the planarization of the trench filling material is realized by using the CMP process for time-etching and the dry etching process using the EPD method together. Therefore, it is possible to solve the problem of non-uniformity of the dishing phenomenon and the amount of polishing, which has been a problem when using only the conventional CMP process, and to control the thickness of the device isolation region accurately. In addition, by controlling the thickness of the element isolation region accurately, it is possible to improve uniformity of device characteristics.

It is apparent that the present invention is not limited to the above-described embodiment, and can be similarly implemented by other persons skilled in the art with other modifications.

Claims (1)

Forming a buffer layer, an etching stop layer and a photoresist on the semiconductor substrate in order; Patterning the photoresist and etching the substrate using the photoresist as an etching mask to form a trench; Filling the trench with an insulating film and polishing the trench by a CMP method to realize a first planarization; Etching the insulating layer using a dry etching method using the etching stop layer as an etching end point to realize a second planarization; And removing the etch stop layer and the buffer layer. ※ Note: It is disclosed by the contents of the first application.