KR20040036757A - Isolation method of semiconductor device using shallow trench isolation process - Google Patents

Isolation method of semiconductor device using shallow trench isolation process Download PDF

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KR20040036757A
KR20040036757A KR1020020065083A KR20020065083A KR20040036757A KR 20040036757 A KR20040036757 A KR 20040036757A KR 1020020065083 A KR1020020065083 A KR 1020020065083A KR 20020065083 A KR20020065083 A KR 20020065083A KR 20040036757 A KR20040036757 A KR 20040036757A
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film
oxide film
pattern
layer
oxide
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KR1020020065083A
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Korean (ko)
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KR100451518B1 (en
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윤일영
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step

Abstract

PURPOSE: A method for isolating a semiconductor device by an STI(shallow trench isolation) process is provided to form a uniform isolation layer regardless of a pattern density by additionally performing a CMP(chemical mechanical polishing) process and an etch-back process on a photoresist layer and by controlling an oxide layer dishing in a pattern rare region. CONSTITUTION: An etch barrier pattern(24) composed of a pad oxide layer(22) and a pad nitride layer(23) is formed on a silicon substrate(21) designed to have a pattern dense region and a pattern rare region. The exposed substrate is etched by using the etch barrier pattern so as to form trenches(25a,25b) having different widths in a pattern rare region such that the widths are wide. An oxide layer is deposited on the resultant structure to fill the trenches. The oxide layer is covered with a photoresist layer. A CMP process is performed on the photoresist layer until the oxide layer is exposed. A partial thickness of the photoresist layer and the oxide layer is etched back to completely eliminate the photoresist layer remaining on the oxide layer on the trench with a wide width. A CMP process is performed on the oxide layer until the pad nitride layer of the etch barrier is exposed.

Description

얕은 트렌치 소자분리 공정을 이용한 반도체 소자의 소자분리방법{ISOLATION METHOD OF SEMICONDUCTOR DEVICE USING SHALLOW TRENCH ISOLATION PROCESS}Device isolation method of semiconductor device using shallow trench isolation process {ISOLATION METHOD OF SEMICONDUCTOR DEVICE USING SHALLOW TRENCH ISOLATION PROCESS}

본 발명은 얕은 트렌치 소자분리(Shallow Trench Isolation) 공정을 이용한 반도체 소자의 소자분리방법에 관한 것으로, 보다 상세하게는, 패턴 밀도 차이에 의해 소자분리막의 두께 차이가 발생되는 것을 방지하기 위한 방법에 관한 것이다.The present invention relates to a device isolation method of a semiconductor device using a shallow trench isolation process, and more particularly, to a method for preventing the thickness difference of the device isolation film caused by the pattern density difference. will be.

반도체 소자를 제조함에 있어서, 소자와 소자 사이의 전기적 분리를 위해 소자분리막을 형성하고 있으며, 이러한 소자분리막을 형성하기 위해 로코스(LOCOS) 및 STI(Shallow Trench Isolation) 공정이 이용되고 있다.In the manufacture of semiconductor devices, device isolation layers are formed for electrical separation between devices, and LOCOS and Shallow Trench Isolation (STI) processes are used to form such device isolation layers.

그런데, 로코스 공정에 의한 소자분리막은 그 상단 코너부에 새부리 형상의 버즈-빅(bird's-beak)이 발생되는 것과 관련해서 소자 형성 면적을 줄이는 단점을 갖는 바, 집적도 측면을 고려할 때, 그 이용에 한계를 갖게 되었다.However, the device isolation film by the LOCOS process has the disadvantage of reducing the device formation area with respect to the occurrence of bird's-beak having a beak shape at the upper corner thereof. Has become a limitation.

따라서, 현재 대부분의 반도체 소자는 작은 폭으로 형성 가능한 STI 공정을 이용해서 소자분리막을 형성하고 있다.Therefore, at present, most semiconductor devices form a device isolation film using an STI process that can be formed in a small width.

이와 같은 STI 공정을 이용한 반도체 소자의 소자분리방법은 다음과 같은 공정 순으로 진행된다.The device isolation method of the semiconductor device using the STI process proceeds in the following order.

먼저, 실리콘 기판 상에 패드산화막과 패드질화막을 차례로 형성한 다음, 소자분리 영역에 해당하는 기판 부분이 노출되도록 상기 패드질화막과 패드산화막을 패터닝하고, 이어서, 노출된 기판 부분을 식각하여 트렌치를 형성한다.First, a pad oxide film and a pad nitride film are sequentially formed on a silicon substrate, and then the pad nitride film and the pad oxide film are patterned to expose the substrate portion corresponding to the device isolation region, and then the exposed substrate portion is etched to form a trench. do.

그런다음, 식각 데미지의 회복시키기 위해 희생 산화 공정을 수행한 후, 열산화 공정을 통해 월 산화막(wall oxide)을 형성한다.Then, after the sacrificial oxidation process is performed to recover the etch damage, a wall oxide is formed through the thermal oxidation process.

다음으로, 트렌치를 완전 매립하도록 기판의 전 영역 상에 HDP(High Density Plasma)-산화막을 증착한 후, 패드질화막이 노출될 때까지 상기 HDP-산화막을 화학적기계연마(Chemical Mechanical Polishing : 이하, CMP)하고, 그리고나서, 트렌치 식각시의 식각 장벽으로 이용된 패드질화막을 제거하여 기판의 적소에 소자들간을 분리시키는 소자분리막들을 형성한다.Next, after depositing the HDP (High Density Plasma) -oxide film on the entire area of the substrate to completely fill the trench, the chemical mechanical polishing (hereinafter referred to as CMP) until the pad nitride film is exposed. Then, the pad nitride film used as an etch barrier during the trench etching is removed to form device isolation films that separate the devices in place on the substrate.

그러나, 종래의 STI 공정을 이용한 소자분리방법에 따르면, 도 1a 및 도 1b에 도시된 바와 같이, 패턴 밀도가 서로 상이한 영역들 각각에 소자분리막(5a, 5b)을 형성할 경우, 패턴 밀도 차이에 의해 패턴 밀도가 밀한 지역과 소한 지역 사이에서 소자분리막(5a, 5b)의 두께 차이가 발생하게 되고, 이로 인해, 소자 특성이 저하된다.However, according to the conventional device isolation method using the STI process, as shown in FIGS. 1A and 1B, when the device isolation layers 5a and 5b are formed in regions having different pattern densities, the pattern density difference is different. As a result, a difference in thickness of the device isolation films 5a and 5b occurs between a region where the pattern density is dense and a region where the pattern density is small, thereby degrading device characteristics.

즉, HDP-산화막(4)의 CMP를 통해 패턴 밀도가 밀한 지역과 소한 지역 각각에 동시에 소자분리막(5a, 5b)을 형성하는 경우, 패턴 밀도가 소한 지역에서의 HDP-산화막(4)의 연마 속도는 패턴 밀도가 밀한 지역에서 그것 보다 빠르기 때문에 패턴 밀도가 소한 지역에서 산화막의 디싱(dishing) 현상이 일어나며, 이에 따라, 패턴 밀도가 소한 지역의 소자분리막(5b)은 밀한 지역의 소자분리막(5a)에 비해 상대적으로 낮은 두께를 갖게 된다. 이 결과, 소자분리막들(5a, 5b)은 패턴 밀도에 따라 영역 별로 서로 상이한 두께를 갖게 되며, 그래서, 소자 특성이 저하된다.That is, when the device isolation films 5a and 5b are simultaneously formed in the areas with dense and small pattern densities through the CMP of the HDP-oxide film 4, the polishing of the HDP-oxide film 4 in the areas with small pattern densities is performed. Since the speed is faster than that in the area where the pattern density is dense, dishing of the oxide film occurs in the area where the pattern density is small, so that the device isolation film 5b in the area where the pattern density is small is the element isolation film 5a in the area where the pattern density is small. It has a relatively low thickness compared to). As a result, the device isolation films 5a and 5b have different thicknesses for each region according to the pattern density, so that device characteristics are degraded.

도 1a 및 도 1b에서, 미설명된 도면부호 1은 실리콘 기판, 2는 패드산화막, 그리고, 3은 패드질화막을 각각 나타낸다.1A and 1B, reference numeral 1 denotes a silicon substrate, 2 a pad oxide film, and 3 a pad nitride film, respectively.

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 패턴 밀도에 상관없이 균일한 두께의 소자분리막들을 얻을 수 있는 반도체 소자의 소자분리방법에 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a device separation method of a semiconductor device capable of obtaining device isolation films having a uniform thickness regardless of the pattern density.

도 1a 및 도 1b는 종래 기술에 따른 반도체 소자의 소자분리방법을 설명하기 위한 단면도.1A and 1B are cross-sectional views illustrating a device isolation method of a semiconductor device according to the prior art.

도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 소자분리방법을 설명하기 위한 공정별 단면도.2A through 2E are cross-sectional views of processes for describing device isolation methods of semiconductor devices according to some embodiments of the present inventive concept.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

21 : 실리콘 기판 22 : 패드산화막21 silicon substrate 22 pad oxide film

23 : 패드질화막 24 : 식각 장벽 패턴23: pad nitride film 24: etching barrier pattern

25a,25b : 트렌치 26 : HDP-산화막25a, 25b: trench 26: HDP-oxide

27 : 감광막 28a,28b : 소자분리막27: photosensitive film 28a, 28b: device isolation film

상기와 같은 목적을 달성하기 위하여, 본 발명은, 패턴 밀도가 밀한 지역과소한 지역을 갖도록 설계된 실리콘 기판 상에 패드산화막과 패드질화막의 적층으로 이루어진 식각 장벽 패턴을 형성하는 단계; 상기 식각 장벽 패턴을 이용해서 노출된 기판 부분을 식각하여 패턴 밀도 소한 지역에서 상대적으로 넓은 폭을 갖는 상이한 폭의 트렌치들을 형성하는 단계; 상기 트렌치들을 매립하도록 기판 결과물 상에 산화막을 증착하는 단계; 상기 산화막 상에 감광막을 도포하는 단계; 상기 산화막이 노출될 때까지 상기 감광막을 CMP하는 단계; 상기 넓은 폭을 갖는 트렌치 상의 산화막 부분 상에 잔류된 감광막이 완전 제거되도록 상기 감광막과 상기 산화막의 표면 일부 두께를 에치-백하는 단계; 및 상기 식각 장벽의 패드질화막이 노출될 때까지 상기 산화막을 CMP하는 단계를 포함하는 반도체 소자의 소자분리방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of forming an etch barrier pattern consisting of a stack of pad oxide film and pad nitride film on a silicon substrate designed to have a pattern density and a small area; Etching portions of the exposed substrate using the etch barrier pattern to form trenches of different widths having a relatively wide width in a pattern density region; Depositing an oxide film on a substrate output to bury the trenches; Coating a photosensitive film on the oxide film; CMPing the photosensitive film until the oxide film is exposed; Etching back the thickness of the photoresist film and a portion of the surface of the oxide film so that the photoresist film remaining on the oxide film portion on the wide trench is completely removed; And CMPing the oxide layer until the pad nitride layer of the etch barrier is exposed.

여기서, 상기 감광막은 5000∼10000Å의 두께로 도포한다.Here, the said photosensitive film is apply | coated with the thickness of 5000-10000 kPa.

상기 감광막과 산화막 표면 일부를 에치-백하는 단계는 감광막 대 산화막의 식각 선택비를 1:1 로 하는 조건으로 수행하며, 또한, 상기 패드질화막 상의 산화막이 500Å 이하의 두께가 잔류되도록 하는 조건으로 수행한다.Etching-back the photoresist and a portion of the oxide film may be performed under a condition in which an etching selectivity ratio of the photoresist to the oxide film is 1: 1, and the oxide film on the pad nitride film may have a thickness of 500 kPa or less. do.

본 발명에 따르면, 감광막의 CMP 및 에치-백 통해 패턴 밀도가 소한 지역에서의 산화막 디싱을 억제시킬 수 있으며, 따라서, 소자 특성 저하를 방지할 수 있으며, 특히, STI 공정의 신뢰성을 확보할 수 있다.According to the present invention, oxide film dishing in a region having a small pattern density can be suppressed through CMP and etch-back of the photoresist film, thereby preventing deterioration of device characteristics, and in particular, securing the reliability of the STI process. .

(실시예)(Example)

이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 소자분리방법을 설명하기 위한 공정별 단면도이다.2A through 2E are cross-sectional views of processes for describing device isolation methods of semiconductor devices according to some embodiments of the inventive concept.

도 2a를 참조하면, 패턴 밀도가 밀한 지역과 소한 지역을 갖도록 설계된 실리콘 기판(21) 상에 각각 50∼150Å 및 1000∼1500Å 두께의 패드산화막(22)과 패드질화막(23)을 차례로 형성한 후, 이들을 패터닝하여 상기 기판(21)의 패턴 밀도가 밀한 지역 및 소한 지역 각각에 후속의 트렌치 식각시에 식각 장벽으로 사용될 식각 장벽 패턴(24)을 형성한다.Referring to FIG. 2A, after the pad oxide layer 22 and the pad nitride layer 23 each having a thickness of 50 to 150 GPa and 1000 to 1500 GPa are sequentially formed on the silicon substrate 21 designed to have a dense region and a small region of pattern density, respectively. These are then patterned to form an etch barrier pattern 24 to be used as an etch barrier in subsequent trench etching in areas where the pattern density of the substrate 21 is dense and in a small area.

그런다음, 식각 장벽 패턴(24)을 이용해서 노출된 기판 부분을 3000∼4000Å의 깊이로 식각하고, 이를 통해, 서로 다른 폭의 제1 및 제2트렌치(25a, 25b)를 형성한다. 여기서, 상기 제2트렌치(25b)는 패턴 밀도가 소한 지역에 형성된 것이며, 아울러, 패턴 밀도가 밀한 지역에 형성된 제1트렌치(25a) 보다 상대적으로 큰 폭을 갖도록 형성된다.Then, the exposed portion of the substrate is etched using the etching barrier pattern 24 to a depth of 3000 to 4000 microns, thereby forming the first and second trenches 25a and 25b having different widths. Here, the second trench 25b is formed in a region where the pattern density is small, and is formed to have a relatively larger width than the first trench 25a formed in the region where the pattern density is dense.

계속해서, 상기 트렌치들(25a, 25b)을 매립하도록 기판 결과물 상에 매립용 산화막으로서 HDP-산화막 또는 HLD-산화막, 바람직하게는 HDP-산화막(26)을 증착한다. 여기서, 상기 HDP-산화막(26)은 하지층의 표면을 따라 증착되므로, 패턴 밀도가 밀한 지역에서의 증착 높이가 패턴 밀도가 소한 지역에서의 그것 보다 높다. 보다 정확하게, 상기 HDP-산화막(26)은 상대적으로 좁은 폭의 제1트렌치(25a) 상의 증착 높이가 상대적으로 넓은 폭을 갖는 제2트렌치(25b) 상에서의 그것 보다 높다. 또한, 상기 HDP-산화막(26)의 증착 두께는 넓은 폭을 갖는 제2트렌치(25b) 상에서의 증착 두께가 식각 장벽 패턴(24)의 패드질화막(23)의 표면과 유사하거나 조금높게 되도록 한다. 예컨데, 트렌치의 깊이가 3500Å이고, 패드질화막(23)의 두께가 1500Å인 경우, HDP-산화막(26)의 증착 두께는 5000Å 이상이 되도록 한다.Subsequently, an HDP oxide film or an HLD oxide film, preferably an HDP oxide film 26, is deposited on the substrate resultant to fill the trenches 25a and 25b. Here, since the HDP-oxide film 26 is deposited along the surface of the underlying layer, the deposition height in the area where the pattern density is dense is higher than that in the area where the pattern density is small. More precisely, the HDP-oxide layer 26 has a higher deposition height on the relatively narrow first trench 25a than that on the second trench 25b having a relatively wide width. In addition, the deposition thickness of the HDP-oxide layer 26 causes the deposition thickness on the second trench 25b having a wide width to be similar to or slightly higher than the surface of the pad nitride layer 23 of the etch barrier pattern 24. For example, when the trench depth is 3500 mm 3 and the thickness of the pad nitride film 23 is 1500 mm 3, the deposition thickness of the HDP-oxide film 26 is set to 5000 mm 3 or more.

도 2b를 참조하면, HDP-산화막(26) 상에 5000∼10000Å의 두께로 감광막(27)을 도포한다. 상기 감광막(27)은 글로벌 평탄화를 얻기 위해 도포해 주는 것으로, 연마 속도가 빨라 두껍게 도포하여도 CMP 시간이 짧으며, 특히, 산화막과의 선택비가 매우 높다.Referring to FIG. 2B, a photosensitive film 27 is applied on the HDP oxide film 26 to a thickness of 5000 to 10000 kPa. The photosensitive film 27 is coated to obtain global planarization, and the CMP time is short even when a thicker coating is applied due to a higher polishing rate. In particular, the selectivity with respect to the oxide film is very high.

도 2c를 참조하면, HDP-산화막(26)이 노출될 때까지 상기 감광막(27)을 CMP한다. 이때, 상기 감광막(27)의 CMP는 감광막과 산화막간의 마찰 정도의 차이를 이용한 커런트 종점검출(Current End Point Detection) 방식으로 중단한다.Referring to FIG. 2C, the photosensitive film 27 is CMP until the HDP-oxide film 26 is exposed. At this time, the CMP of the photoresist layer 27 is stopped by the current end point detection method using the difference in the degree of friction between the photoresist and the oxide film.

도 2d를 참조하면, 감광막(27)과 HDP-산화막(26)의 표면 일부 두께를 에치-백(Etch-Back)한다. 이때, 상기 감광막(27)과 HDP-산화막(26)의 에치-백은 감광막과 산화막간의 식각 선택비를 1:1로 하는 조건으로 수행하며, 특히, 식각 장벽 패턴(24)의 패드질화막(23) 상에 잔류되는 HDP-산화막의 두께가 50Å 이하가 되는 조건으로 수행한다. 상기 에치-백의 결과, 감광막(27)은 대부분 제거되며, 단지, 상대적으로 넓은 폭으로 형성된 제2트렌치(25b) 상의 HDP-산화막 부분 상에만 미소하게 잔류된다.Referring to FIG. 2D, the thicknesses of the surface portions of the photoresist layer 27 and the HDP oxide layer 26 are etched back. At this time, the etch-back of the photoresist 27 and the HDP-oxide 26 is performed under the condition that the etching selectivity between the photoresist and the oxide is 1: 1. In particular, the pad nitride layer 23 of the etching barrier pattern 24 is formed. The thickness of the HDP oxide film remaining on the N-) film is 50 Å or less. As a result of the etch-back, the photoresist film 27 is mostly removed, and only slightly remains on the HDP-oxide film portion on the second trench 25b formed in a relatively wide width.

도 2e를 참조하면, 식각 장벽 패턴(24)의 패드질화막(23)이 노출될 때까지 잔류된 감광막과 HDP-산화막을 CMP하고, 이 결과로서, 기판(21)의 패턴 밀도가 서로 상이한 지역 각각에 서로 다른 폭을 갖는 트렌치형의 소자분리막들(28a, 28b)을 형성한다. 이때, 상기 CMP는 가능한 누르는 압력은 작고, 회전속도는 빠르게 하여글로벌 평탄화가 이루어지도록 한다. 예컨데, 누르는 압력은 4psi, 그리고, 회전속도는 50rpm 이상으로 한다.Referring to FIG. 2E, the remaining photoresist film and the HDP-oxide film are CMP until the pad nitride film 23 of the etching barrier pattern 24 is exposed, and as a result, each of the regions having different pattern densities of the substrate 21 from each other. Trench type isolation layers 28a and 28b having different widths are formed on the substrate. At this time, the CMP is as low as possible the pressing pressure, the rotational speed is fast to achieve the global flattening. For example, the pressing pressure is 4 psi and the rotation speed is 50 rpm or more.

여기서, 상기 소자분리막들(28a, 28b)은 감광막의 CMP 및 에치-백의 추가 수행으로 인해 패턴 밀도 차이, 즉, 상대적으로 넓은 폭의 제2트렌치에 형성된 것이 상대적으로 낮은 두께를 갖게 되는 현상은 억제된다.In this case, the device isolation layers 28a and 28b have a pattern density difference due to additional CMP and etch-back of the photoresist layer, that is, a phenomenon in which the second trenches having a relatively wide width have a relatively low thickness is suppressed. do.

결국, 본 발명의 방법은 감광막의 CMP 및 에치-백의 추가 수행을 통해서 패턴 밀도에 무관하게 균일한 두께를 갖는 소자분리막들을 동시에 형성할 수 있으며, STI 공정의 신뢰성을 확보할 수 있다.As a result, the method of the present invention can simultaneously form device isolation films having a uniform thickness irrespective of the pattern density by further performing CMP and etch-back of the photoresist film, thereby ensuring reliability of the STI process.

이상에서와 같이, 본 발명은 감광막의 CMP 및 에치-백의 추가 수행을 통해서 패턴 밀도가 소한 지역에서의 산화막 디싱을 억제시킬 수 있다. 따라서, 패턴 밀도에 상관없이 소자분리막의 균일한 형성이 가능하므로, STI 공정의 신뢰성을 확보할 수 있음은 물론 궁극적으로는 소자 특성을 향상시킬 수 있다.As described above, the present invention can suppress oxide film dishing in a region having a small pattern density by further performing CMP and etch-back of the photosensitive film. Therefore, since the device isolation film may be uniformly formed regardless of the pattern density, the reliability of the STI process may be secured and ultimately, the device characteristics may be improved.

기타, 본 발명은 그 요지가 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (5)

패턴 밀도가 밀한 지역과 소한 지역을 갖도록 설계된 실리콘 기판 상에 패드산화막과 패드질화막의 적층으로 이루어진 식각 장벽 패턴을 형성하는 단계;Forming an etch barrier pattern comprising a stack of pad oxide films and pad nitride films on a silicon substrate designed to have a dense and a small pattern density region; 상기 식각 장벽 패턴을 이용해서 노출된 기판 부분을 식각하여 패턴 밀도 소한 지역에서 상대적으로 넓은 폭을 갖는 상이한 폭의 트렌치들을 형성하는 단계;Etching portions of the exposed substrate using the etch barrier pattern to form trenches of different widths having a relatively wide width in a pattern density region; 상기 트렌치들을 매립하도록 기판 결과물 상에 산화막을 증착하는 단계;Depositing an oxide film on a substrate output to bury the trenches; 상기 산화막 상에 감광막을 도포하는 단계;Coating a photosensitive film on the oxide film; 상기 산화막이 노출될 때까지 상기 감광막을 CMP하는 단계;CMPing the photosensitive film until the oxide film is exposed; 상기 넓은 폭을 갖는 트렌치 상의 산화막 부분 상에 잔류된 감광막이 완전 제거되도록 상기 감광막과 상기 산화막의 표면 일부 두께를 에치-백하는 단계; 및Etching back the thickness of the photoresist film and a portion of the surface of the oxide film so that the photoresist film remaining on the oxide film portion on the wide trench is completely removed; And 상기 식각 장벽의 패드질화막이 노출될 때까지 상기 산화막을 CMP하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 소자분리방법.CMPing the oxide layer until the pad nitride layer of the etch barrier is exposed. 제 1 항에 있어서, 상기 감광막은 5000∼10000Å의 두께로 도포하는 것을 특징으로 하는 반도체 소자의 소자분리방법.The method of claim 1, wherein the photosensitive film is coated with a thickness of 5000 to 10000 GPa. 제 1 항에 있어서, 상기 감광막과 산화막 표면 일부를 에치-백하는 단계는The method of claim 1, wherein the etching of the surface of the photoresist and the oxide layer is performed. 감광막 대 산화막의 식각 선택비를 1:1 로 하는 조건으로 수행하는 것을 특징으로 하는 반도체 소자의 소자분리방법.A device isolation method for a semiconductor device, characterized in that the etching selectivity of the photosensitive film to the oxide film is carried out under a condition of 1: 1. 제 1 항 또는 제 3 항에 있어서, 상기 감광막과 산화막 표면 일부를 에치-백하는 단계는, 상기 패드질화막 상의 산화막이 500Å 이하의 두께가 잔류되도록 하는 조건으로 수행하는 것을 특징으로 하는 반도체 소자의 소자분리방법.4. The device of claim 1 or 3, wherein the etching of the surface of the photoresist and the oxide film is performed under conditions such that an oxide film on the pad nitride film has a thickness of 500 kPa or less. Separation Method. 제 1 항에 있어서, 상기 산화막을 CMP하는 단계는The method of claim 1, wherein the step of CMP the oxide film 누르는 압력을 4psi, 회전속도를 50rpm 이상으로 하여 수행하는 것을 특징으로 하는 반도체 소자의 소자분리방법.Pressing pressure of 4psi, the rotation speed of 50rpm or more device separation method characterized in that performed.
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CN102412140A (en) * 2010-09-17 2012-04-11 台湾积体电路制造股份有限公司 Non-uniformity reduction in semiconductor planarization
US10147636B2 (en) 2016-06-27 2018-12-04 Vanguard International Semiconductor Corporation Methods for fabricating trench isolation structure
KR20180020771A (en) * 2016-08-19 2018-02-28 뱅가드 인터내셔널 세미컨덕터 코포레이션 Methods for fabricating trench isolation structure
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