KR100843903B1 - Method for manufacturing of semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to enhance the yield and process margin and to reduce the manufacturing cost by removing a bit line tungsten hard mask layer without residues. An interlayer dielectric(12,16) including a bit line is formed on a semiconductor substrate(10) including a cell region(C) and a peripheral region(P). A storage electrode contact hole is formed by selectively etching the interlayer dielectric. A conductive layer(38) for storage electrode contact is formed on the upper surface of the semiconductor substrate. The bit line is exposed by performing a first planarization process on the conductive layer of the peripheral circuit region. A storage electrode contact plug is formed by performing a second planarization process on the conductive layer of the cell region.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}

1 is a photograph for explaining the problem of the manufacturing method of a semiconductor device according to the prior art.

2A to 2F illustrate a method of manufacturing a semiconductor device according to the present invention.

Figure 3 is a photograph showing a method of manufacturing a semiconductor device according to the present invention.

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a storage electrode contact plug of a semiconductor device.

As semiconductor devices have been highly integrated, hole type storage electrode contact plugs are formed using immersion lithography equipment in devices of 60 nm or less. The storage electrode contact plug of the hole type is formed by filling a polysilicon layer in the storage electrode contact hole after forming a storage electrode contact hole exposing a lower pattern between the bit lines, that is, the landing plug, in the state where the bit line is formed.

However, since the hole type storage electrode contact plug has a narrow upper area, the overlap margin with the storage electrode formed in a subsequent process is insufficient. Accordingly, there is a problem in that another storage electrode contact plug must be formed between the storage electrode contact plug and the storage electrode. In addition, the immersion lithography equipment used to form the hole type has a problem in that mass productivity is lowered due to an increase in maintenance cost as an expensive equipment.

In order to solve this problem, a storage electrode contact plug is formed in a line type. The line-type storage electrode contact plug forms a bit line, forms an interlayer insulating layer covering the bit line, and then etches the remaining interlayer insulating layer, leaving only a portion to separate the storage electrode contact plug. Is using.

However, in the line type storage electrode contact plug forming process, the gap between the bit lines is gradually narrowed, so that the upper part of the bit lines is lost due to insufficient etching margin. As a result, a SAC defect occurs between the storage electrode contact plug and the bit line, resulting in deterioration of device characteristics.

In order to solve this problem, a bit mask hard mask layer is formed on the bit line in a multilayer manner. That is, it is formed of a triple structure of a nitride film, an amorphous carbon (armophous-Carbon) layer, and a tungsten (W) layer. Among them, the tungsten (W) layer is excellent as an etching barrier but must be removed because it is the same material as the metal wiring. Should be.

1 is a photograph illustrating a problem of a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1, since the peripheral circuit area is not dense as compared to the cell area when the line type storage electrode contact plug is formed, dishing is performed on the peripheral circuit area during the cleaning process to remove the tungsten (W) layer. (dishing) phenomenon occurs. In this state, a planarization process for separating between the storage electrode contact plugs is performed, and thus a polysilicon film is not completely removed and a residue A remains in the peripheral circuit region.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a method of manufacturing a semiconductor device capable of removing a bit line tungsten hard mask layer without residue in a peripheral circuit area when forming a line type storage electrode contact plug. The purpose is to provide.

Method for manufacturing a semiconductor device according to the present invention for achieving the above object,

Forming an interlayer insulating film including a bit line on the semiconductor substrate in which the cell region and the peripheral circuit region are divided;

Selectively etching the interlayer insulating film to form a storage electrode contact hole, and forming a storage electrode contact conductive film over the entire surface;

Exposing the bit line by performing a first planarization process on the conductive film for the storage electrode contact in the peripheral circuit region;

Forming a storage electrode contact plug by performing a second planarization process on the conductive film for the storage electrode contact in the cell region

Characterized in that it comprises a.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F show a method of manufacturing a semiconductor device according to the present invention, (i) is a cross-sectional view, and (ii) is a plan view along the cut line B-B 'of (i).

Referring to FIG. 2A, a first interlayer insulating layer 12 is formed on a semiconductor substrate 10 on which a predetermined substructure is provided and where the cell region C and the peripheral circuit region P are divided.

Next, a first photoresist layer (not shown) is formed on the first interlayer insulating layer 12, and the first photoresist layer is exposed and developed with a landing plug contact mask (not shown) to form a first photoresist layer pattern.

Next, the first interlayer dielectric layer is etched using the first photoresist pattern as a mask to form a landing plug contact hole (not shown).

Next, after removing the first photoresist pattern, a landing film 14 is formed by filling a conductive film in the landing plug contact hole.

Next, a second interlayer insulating film 16 is formed on the entire surface of the semiconductor substrate 10 including the landing plug 14.

Next, a barrier metal layer (not shown), a bit line tungsten layer (not shown), a first bit line hard mask layer (not shown), and a second bit line hard mask layer are formed on the second interlayer insulating layer 16. Not shown) and a third bit line hard mask layer (not shown) are sequentially formed.

In this case, the barrier metal layer is formed of Ti / TiN to a thickness of 100 ~ 1000Å, the bit line tungsten layer is formed to a thickness of 300 ~ 1000Å, the first bitline hard mask layer is a nitride film of 1000 ~ 2500Å It is preferable to form in thickness.

The second bit line hard mask layer may have a tungsten layer having a thickness of 500-1500 GPa, and the third bit line hard mask layer may have an amorphous carbon (armophous-Carbon) layer having a thickness of 1000-2000 GPa. desirable.

Next, an anti-reflection film (not shown) and a second photoresist film are formed on the third bit line hard mask layer.

At this time, the anti-reflection film is preferably formed of a silicon oxynitride (SiON) film with a thickness of 300 ~ 1000Å.

Next, the second photoresist film is exposed and developed with a mask defining a bit line to form a second photoresist pattern.

Next, the anti-reflection film, the third, second and first bit line hard mask layers, the bit line tungsten layer and the barrier metal layer are etched using the second photoresist pattern as a mask (not shown). , A third bit line hard mask layer pattern (not shown), a second bit line hard mask layer pattern 24, a first bit line hard mask layer pattern 22, a bit line tungsten layer pattern 20, and a barrier metal layer The pattern 18 is formed.

In this case, the first, second and third bit line hard mask layer etching process is performed in a mixed gas atmosphere of CF4, CHF3, O2 and Ar under a power of 300 ~ 1000W, pressure of 20 ~ 70mT, the bitline tungsten The layer etching process is preferably performed in a mixed gas atmosphere of SF6, BCL3, N2 and Cl2 under a power of 300 to 1000 W and a pressure of 20 to 70 mT.

Next, the second photoresist pattern and the anti-reflection film pattern are removed.

Next, a nitride film (not shown) is formed along the surface of the pattern, and a bit line spacer 26 is formed on the sidewall of the pattern by performing a spacer process including etching and cleaning.

At this time, the bit line spacer 26 is preferably formed to a thickness of 50 ~ 150Å.

Next, a third interlayer insulating film 28 is formed over the entire surface.

In this case, the third interlayer insulating film 28 preferably forms a SOD (Spin On Dielectric) film with a thickness of 4000 to 10000 GPa.

 Next, a planarization process is performed until the second bit line hard mask layer pattern 24 is exposed to planarize the upper portion of the third interlayer insulating layer 28.

Referring to FIG. 2B, a storage electrode contact hard mask layer (not shown) and a third photosensitive layer (not shown) are formed on the third interlayer insulating layer 28.

In this case, the storage electrode contact hard mask layer is preferably formed of an amorphous carbon (armophous-Carbon) layer.

Next, the third photoresist layer is exposed and developed with a line type storage electrode contact mask to form a third photoresist pattern 30.

Subsequently, the storage electrode contact hard mask layer and the third interlayer insulating layer 28 of the cell region C are etched with a predetermined depth by using the third photoresist pattern 30 as a mask to form a storage electrode contact hard mask layer pattern ( Not shown) and the first contact hole 32 is formed.

At this time, the etching process of the third interlayer insulating film 28 is preferably performed in a mixed gas atmosphere of C4F8, C5F8, C4F6, CH2F2, Ar, O2, Co, and N2 under a power of 1000 to 2000 W and a pressure of 15 to 50 mT. .

And it is preferable that the said predetermined depth is 1000-2000 micrometers.

Then, the wet cleaning process is performed to increase the upper line width CD of the first contact hole 32.

Referring to FIG. 2C, the third interlayer insulating layer 28 and the second interlayer insulating layer under the first contact hole 32 are masked using the third photoresist layer pattern 30 and the storage electrode contact hard mask layer pattern. The storage electrode contact hole is completed by etching the 16 to form the second contact hole 34 exposing the landing plug 14.

At this time, the etching process of the third interlayer insulating film 28 and the second interlayer insulating film 16 under the first contact hole 32 is performed at a power of 1000 to 2000 W and a pressure of 15 to 50 mT, C4F8, C5F8, C4F6, and CH2F2. Preference is given to performing in a mixed gas atmosphere of, Ar, O 2, Co and N 2.

Next, the third photoresist pattern and the storage electrode contact hard mask layer pattern are removed.

Referring to FIG. 2D, a low pressure (LP) nitride film (not shown) is formed on the entire surface.

At this time, the LP (low pressure) nitride film is preferably formed to a thickness of 100 ~ 300 100.

Next, a spacer process including an etching and a cleaning process for the LP nitride layer is performed to form storage electrode contact spacers 36 on sidewalls of the first contact hole 32 and the second contact hole 34.

In this case, the LP nitride film etching process is preferably performed in a mixed gas atmosphere of CF4, CHF3, O2 and Ar under a power of 300 ~ 1000W, pressure of 10 ~ 30mT.

Next, the second bit line hard mask layer pattern 24 is removed by a wet cleaning process.

Here, the wet cleaning process is preferably performed using a BOE solution in which sulfuric acid (H 2 SO 4) and hydrogen peroxide solution (H 2 O 2) are mixed.

At this time, a step caused by dishing occurs in the third interlayer insulating film 28 in the peripheral circuit region P.

Referring to FIG. 2E, the conductive film 38 for the storage electrode contact is formed on the entire surface.

In this case, the storage electrode contact conductive film 38 is preferably formed of polysilicon having a thickness of 1500 ~ 3000Å.

Next, a fourth photoresist layer (not shown) is formed on the conductive layer 38 for the storage electrode contact, and the fourth photoresist layer is exposed and developed with a cell blocking mask to form a fourth photoresist pattern 40.

Next, a first planarization process is performed on the conductive layer 38 for the storage electrode contact in the peripheral circuit region P using the fourth photoresist pattern 40 as a mask.

In this case, the first planarization process may be performed by an etch back method, and the etching target of the storage electrode contact conductive layer 38 may be 1000 to 1500 ns.

The first planarization process may be performed by adjusting a process recipe so that an etching selectivity between the storage electrode contact conductive layer 38 and the first hard mask layer pattern 22 is 1: 1. As a result, the step difference between the third interlayer dielectric layer 28 in the peripheral circuit region P is eliminated.

Next, the fourth photoresist pattern 40 is removed.

Referring to FIG. 2F, the storage electrode contact plug 42 is insulated by performing a second planarization process on the storage electrode contact conductive layer 38 in the cell region C to insulate the storage electrode contact conductive layer 38. To complete.

3 is a photograph showing a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 3, it can be seen that the residue of the conductive electrode for the storage electrode contact, ie, polysilicon, is removed from the peripheral circuit region.

As described above, in the method of manufacturing a semiconductor device according to the present invention, a step of first leveling is performed only in the peripheral circuit region by a step caused by a dishing phenomenon occurring in the peripheral circuit region when the line type storage electrode contact plug is formed. After the removal, the second planarization process for separating the storage electrode contact plug may be performed to remove the polysilicon residue in the peripheral circuit region without damaging the bit line of the cell region.

As described above, in the method of manufacturing a semiconductor device according to the present invention, when forming a line type storage electrode contact plug, the first planarization process may be performed on a peripheral circuit area to remove a step, and then the storage electrode contact plug may be separated. By performing the second planarization process, the bit line tungsten hard mask layer can be removed without residue, thereby improving device yield, process margin, and cost reduction.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (11)

Forming an interlayer insulating film including bit lines on the semiconductor substrate, wherein the cell region and the peripheral circuit region are separated; Selectively etching the interlayer insulating layer to form a storage electrode contact hole, and forming a storage electrode contact conductive layer over the entire surface of the interlayer insulating layer; Exposing the bit line by performing a first planarization process on the conductive film for the storage electrode contact in the peripheral circuit region; And Forming a storage electrode contact plug by performing a second planarization process on the conductive film for the storage electrode contact in the cell region Method of manufacturing a semiconductor device comprising a. The method of claim 1, wherein the bit line has a stacked structure of a bit line metal layer, a first bit line hard mask layer, and a second bit line hard mask layer. The method of claim 2, wherein the first bit line hard mask layer is formed of a nitride film having a thickness of 1000 ~ 2500Å, the second bit line hard mask layer is formed of a tungsten layer of 500 ~ 1500Å thickness Method of manufacturing a semiconductor device. 3. The method of claim 2, further comprising removing the second bit line hard mask layer by performing a wet cleaning process before forming the conductive layer for the storage electrode contact. 4. The method of claim 4, wherein the etching selectivity between the conductive layer for the storage electrode contact and the first bit line hard mask layer is 1: 1 in the first planarization process. The method of claim 1, wherein the interlayer insulating layer is formed of a spin on dielectric (SOD) layer with a thickness of 4000 to 10000 GPa. The method of claim 1, wherein the forming of the storage electrode contact hole is performed. Forming a first contact hole by etching the interlayer insulating layer a predetermined depth by a photolithography process using a storage electrode contact mask; Performing a wet cleaning process on the first contact hole to increase an upper line width of the first contact hole; And Etching a lower portion of the first contact hole by a photolithography process using the storage electrode contact mask to form a second contact hole Method of manufacturing a semiconductor device comprising a. The method of manufacturing a semiconductor device according to claim 7, wherein said predetermined depth is 1000 to 2000 microns. The method of claim 7, wherein the etching process in the first contact hole and the second contact hole forming step is C4F8, C5F8, C4F6, CH2F2, Ar, O2, Co under a power of 1000 ~ 2000W, pressure of 15 ~ 50mT, respectively And N2 in a mixed gas atmosphere. The method of claim 1, wherein the storage electrode contact conductive film is formed of polysilicon having a thickness of 1500 to 3000 GPa. The method of claim 1, wherein an etching target of the conductive layer for the storage electrode contact in the first planarization process is 1000 to 1500 ns.

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