KR970052420A - Method of forming contact window of semiconductor device - Google Patents

Method of forming contact window of semiconductor device Download PDF

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Publication number
KR970052420A
KR970052420A KR1019950064435A KR19950064435A KR970052420A KR 970052420 A KR970052420 A KR 970052420A KR 1019950064435 A KR1019950064435 A KR 1019950064435A KR 19950064435 A KR19950064435 A KR 19950064435A KR 970052420 A KR970052420 A KR 970052420A
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KR
South Korea
Prior art keywords
layer
dry etching
insulating layer
etching
silicide
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KR1019950064435A
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Korean (ko)
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KR0172774B1 (en
Inventor
김인철
김천수
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김주용
현대전자산업 주식회사
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Priority to KR1019950064435A priority Critical patent/KR0172774B1/en
Publication of KR970052420A publication Critical patent/KR970052420A/en
Application granted granted Critical
Publication of KR0172774B1 publication Critical patent/KR0172774B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 절연막을 선택식각하여 상기 절연막 하부의 전도층의 소정부위가 노출되도록 하는 반도체 소자의 접촉창 형성방법에 있어서, 상기 절연막 상부에 실리사이드막을 형성하는 제1단계;접촉창 마스크를 이용하여 상기 실리사이드막을 선택식각하여 상기 절연막의 소정 부위를 노출시키는 제2단계;패터닝된 상기 실리사이드막 측벽 하부로 언더컷이 발생하도록 노출된 상기 절연막을 등방성 부분 건식식각하는 제3단계;잔류하는 상기 절연막을 비등방성 건식식각하는 제4단계;상기 실리사이드막을 제거하는 제5단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a contact window of a semiconductor device by selectively etching an insulating layer to expose a predetermined portion of a conductive layer under the insulating layer, the method comprising: forming a silicide layer on the insulating layer; A second step of selectively etching a silicide film to expose a predetermined portion of the insulating film; a third step of isotropically dry etching the exposed insulating film so that an undercut occurs under the patterned silicide film sidewall; Dry etching a fourth step; characterized in that it comprises a fifth step of removing the silicide film.

Description

반도체 소자의 접촉창 형성방법Method of forming contact window of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2a도 내지 제2e도는 본 발명의 일실시예에 따른 반도체 소자의 접촉창 형성 공정도.2a to 2e is a process window forming process of a semiconductor device according to an embodiment of the present invention.

Claims (7)

절연막을 선택식각하여 상기 절연막 하부의 전도층의 소정부위가 노출되도록 하는 반도체 소자의 접촉창 형성방법에 있어서, 상기 절연막 상부에 실리사이드막을 형성하는 제1단계; 접촉창 마스크를 이용하여 상기 실리사이드막을 선택식각하여 상기 절연막의 소정부위를 노출시키는 제2단계; 패터닝된 상기 실리사이드막 측벽 하부로 언더컷이 발생하도록 노출된 상기 절연막을 등방성 부분 건식식각하는 제3단계; 잔류하는 상기 절연막을 비등방성 건식식각하는 제4단계; 상기 실리사이드막을 제거하는 제5단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 접촉창 형성방법.A method of forming a contact window in a semiconductor device to selectively expose an insulating layer to expose a predetermined portion of a conductive layer under the insulating layer, the method comprising: forming a silicide layer on the insulating layer; Selectively etching the silicide layer using a contact window mask to expose a predetermined portion of the insulating layer; An isotropic partial dry etching of the exposed insulating film to undercut the patterned silicide film sidewalls; A fourth step of anisotropic dry etching the remaining insulating film; And a fifth step of removing the silicide layer. 제1항에 있어서, 상기 실리사이드막은 텅스텐 실리사이드막 또는 티타늄 실리사이드막 중 하나인 것을 특징으로 하는 반도체 소자의 접촉창 형성방법.The method of claim 1, wherein the silicide layer is one of a tungsten silicide layer or a titanium silicide layer. 제1항에 있어서, 상기 제3단계는 CF2+ O2플라즈마에 의한 등방성 건식식각으로 이루어지는 것을 특징으로 하는 반도체 소자의 접촉창 형성방법.The method of claim 1, wherein the third step comprises isotropic dry etching using CF 2 + O 2 plasma. 제1항에 있어서, 상기 제4단계는 CF4+ CHF3+ Ar 플라즈마에 의한 비등방성 건식식각으로 이루어지는 것을 특징으로 하는 반도체 소자의 접촉창 형성방법.The method of claim 1, wherein the fourth step comprises anisotropic dry etching using CF 4 + CHF 3 + Ar plasma. 제1항에 있어서, 상기 제5단계는 SF6+ He 또는 SF6+ Ar 플라즈마 중 하나를 사용하여 이루어지는 것을 특징으로 하는 반도체 소자의 접촉창 형성방법.The method of claim 1, wherein the fifth step is performed using one of SF 6 + He or SF 6 + Ar plasma. 제1항에 있어서, 상기 제2단계에서 상기 선택식각은 상기 절연막이 부분식각되도록 과도식각하여 이루어지는 것을 특징으로 하는 반도체 소자의 접촉창 형성방법.The method of claim 1, wherein in the second step, the selective etching is performed by over-etching the insulating layer partially. 제4항에 있어서, 상기 등방성 건식식각은 뱃치형 감광막 제거장치에서 이루어지는 것을 특징으로 하는 반도체 소자의 접촉창 형성방법.The method of claim 4, wherein the isotropic dry etching is performed in a batch type photosensitive film removing apparatus. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950064435A 1995-12-29 1995-12-29 Methd of forming contact hole of semiconductor device KR0172774B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950064435A KR0172774B1 (en) 1995-12-29 1995-12-29 Methd of forming contact hole of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950064435A KR0172774B1 (en) 1995-12-29 1995-12-29 Methd of forming contact hole of semiconductor device

Publications (2)

Publication Number Publication Date
KR970052420A true KR970052420A (en) 1997-07-29
KR0172774B1 KR0172774B1 (en) 1999-03-30

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KR1019950064435A KR0172774B1 (en) 1995-12-29 1995-12-29 Methd of forming contact hole of semiconductor device

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KR0172774B1 (en) 1999-03-30

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