KR970018216A - Planarization Method of Semiconductor Device - Google Patents

Planarization Method of Semiconductor Device Download PDF

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Publication number
KR970018216A
KR970018216A KR1019950031794A KR19950031794A KR970018216A KR 970018216 A KR970018216 A KR 970018216A KR 1019950031794 A KR1019950031794 A KR 1019950031794A KR 19950031794 A KR19950031794 A KR 19950031794A KR 970018216 A KR970018216 A KR 970018216A
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KR
South Korea
Prior art keywords
film
insulating film
planarization
semiconductor substrate
semiconductor device
Prior art date
Application number
KR1019950031794A
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Korean (ko)
Inventor
김재우
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950031794A priority Critical patent/KR970018216A/en
Publication of KR970018216A publication Critical patent/KR970018216A/en

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Abstract

본 발명은 평탄화를 위해 플로우 공정을 수행함으로써 발생되는 종래의 평탄화 기술의 문제점을 해결하기 위한 것으로, 플로우 공정대신 포토레지스트(4)나 SOG(5)를 도포하여 에치 백함으로써 금속 콘택을 위한 사진식각 공정에서 패턴의 형성 및 임계 치수의 조정이 용이하고, 고단차로 인한 과식각을 방지할 수 있으며, 단차로 인간 잔류물의 발생을 최대로 줄일 수 있게 된다.The present invention is to solve the problem of the conventional planarization technology caused by performing a flow process for planarization, and instead of the flow process by applying a photoresist (4) or SOG (5) to etch back the photo etch for metal contact It is easy to form patterns and adjust critical dimensions in the process, to prevent over-etching due to high steps, and to minimize the generation of human residues by steps.

Description

반도체 장치의 평탄화 방법Planarization Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2C도는 본 발명의 바람직한 일 실시예에 따른 평탄화 방법을 설명하기 위한 도면,2A to 2C are views for explaining a planarization method according to an embodiment of the present invention,

제3A도 및 제3B도는 본 발명의 바람직한 다른 실시예에 따른 평탄화 방법을 설명하기 위한 도면.3A and 3B are views for explaining a planarization method according to another preferred embodiment of the present invention.

Claims (5)

하부 배선이 형성되어 있는 반도체 기판 위에 상기 상부 배선과 상부 배선 간의 전기적 절연을 위한 절연막(2)을 상기 하부 배선 위에 적층하 공정과, 상기 절연막(2) 위에 평탄화용 막을 적층하는 공정과, 상기 절연막(2)의 상부 표면이 노출될 때까지 상기 반도체 기판을 에치-백하는 공정과, 상기 절연막(2)의 상기 상부 표면이 노출된 후 상기 절연막/상기 평탄화용 막의 식각 선택비가 적어도 1 이상이 되도록 하여 상기 반도체 기판을 식각하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 평탄화 방법.Stacking an insulating film 2 for electrical insulation between the upper wiring and the upper wiring on the lower wiring on the semiconductor substrate on which the lower wiring is formed, laminating a planarization film on the insulating film 2, and the insulating film Etching back the semiconductor substrate until the upper surface of (2) is exposed; and after the upper surface of the insulating film 2 is exposed, the etching selectivity of the insulating film / the planarization film is at least one or more. And etching the semiconductor substrate. 제1항에 있어서, 상기 평탄화용 막은 포토레지스트 막(4)인 것을 특징으로 하는 반도체 장치의 평탄화 방법.A method according to claim 1, wherein the planarization film is a photoresist film (4). 제1항에 있어서, 상기 평탄화용 막은 SOG막(5)인 것을 특징으로 하는 반도체 장치의 평탄화 방법.2. The method of claim 1, wherein the planarization film is an SOG film (5). 제1항 내지 제3항 중 어느 한 항에 있어서, 상기 절연막(2)은 BPSG 또는 OSG 중 하나인 것을 특징으로 하는 반도체 장치의 평탄화 방법.A method according to any one of the preceding claims, wherein the insulating film (2) is one of BPSG or OSG. 제2항에 있어서, 상기 포토레지스트 막(4)은 O2플라즈마 에싱으로 식각되는 것을 특징으로 하는 반도체 장치의 평탄화 방법.3. The method of claim 2, wherein the photoresist film is etched by O 2 plasma ashing. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950031794A 1995-09-26 1995-09-26 Planarization Method of Semiconductor Device KR970018216A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950031794A KR970018216A (en) 1995-09-26 1995-09-26 Planarization Method of Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950031794A KR970018216A (en) 1995-09-26 1995-09-26 Planarization Method of Semiconductor Device

Publications (1)

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KR970018216A true KR970018216A (en) 1997-04-30

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KR1019950031794A KR970018216A (en) 1995-09-26 1995-09-26 Planarization Method of Semiconductor Device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100737379B1 (en) * 2005-12-06 2007-07-09 한국전자통신연구원 Method of planarization for semiconductor substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100737379B1 (en) * 2005-12-06 2007-07-09 한국전자통신연구원 Method of planarization for semiconductor substrate

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