KR970067640A - Method for forming a metal layer of a semiconductor - Google Patents

Method for forming a metal layer of a semiconductor Download PDF

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Publication number
KR970067640A
KR970067640A KR1019960007103A KR19960007103A KR970067640A KR 970067640 A KR970067640 A KR 970067640A KR 1019960007103 A KR1019960007103 A KR 1019960007103A KR 19960007103 A KR19960007103 A KR 19960007103A KR 970067640 A KR970067640 A KR 970067640A
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KR
South Korea
Prior art keywords
metal
forming
metal layer
contact hole
layer
Prior art date
Application number
KR1019960007103A
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Korean (ko)
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KR100187686B1 (en
Inventor
권창헌
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960007103A priority Critical patent/KR100187686B1/en
Publication of KR970067640A publication Critical patent/KR970067640A/en
Application granted granted Critical
Publication of KR100187686B1 publication Critical patent/KR100187686B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 반도체 소자의 금속층 형성 방법에 관한 것으로, 콘택 홀에서 금속의 층덮힘을 향상시키기 위하여 콘택 홀의 상부 모서리부를 제외한 측벽 및 하부에 금속 이온을 주입하여 시드층을 형성한 후 금속을 매립시킴으로써 금속의 층덮힘이 향상된다. 따라서 보이드의 발생이 방지되고 금속층의 접속 불량 및 단선이 방지되어 소자의 전기적 특성 및 신뢰성이 향상될 수 있는 반도체 소자의 금속층 형성 방법에 관한 것이다.The present invention relates to a method for forming a metal layer of a semiconductor device, in which a metal layer is formed by implanting metal ions into sidewalls and a lower portion of a contact hole except for the upper edge portion of the contact hole, Is improved. To a method of forming a metal layer of a semiconductor device capable of preventing occurrence of voids and preventing connection failure and disconnection of a metal layer to improve electrical characteristics and reliability of the device.

Description

반도체 소자의 금속층 형성 방법Method for forming a metal layer of a semiconductor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제3A 내지 제3D도는 본 발명에 따른 반도체 소자의 금속층 형성방법을 설명하기 위한 소자의 단면도.3A to 3D are cross-sectional views of a device for explaining a method of forming a metal layer of a semiconductor device according to the present invention.

Claims (3)

반도체 소자의 금속층 형성 방법에 있어서, 접합부가 형성된 실리콘 기판상에 절연층 및 감광막을 순차적으로 형성한 후 상기 감광막을 패터닝하는 단계와, 상기 단계로부터 상기 패터닝된 감광막을 마스크로 이용한 식각 공정으로 노출된 부분의 상기 절연층을 식각하여 상기 접합부가 노출되도록 콘택 홀을 형성하는 단계와, 상기 단계로부터 상기 콘택 홀의 상부 모서리부를 제외한 측벽 및 하부에 시드층이 형성되도록 금속 이온을 주입하는 단계와, 상기 단계로부터 상기 감광막을 제거한 후 상기 콘택홀이 매립되도록 전체 상부면에 금속을 증착하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 금속층 형성 방법.A method of forming a metal layer of a semiconductor device, the method comprising: sequentially forming an insulating layer and a photoresist layer on a silicon substrate having a junction formed thereon; patterning the photoresist layer; and exposing the photoresist layer to an etching process using the patterned photoresist layer as a mask Etching the insulating layer to form a contact hole to expose the junction; implanting metal ions so that a seed layer is formed on a side wall and a lower side of the contact hole excluding the upper edge of the contact hole; Depositing a metal on the entire upper surface so as to fill the contact hole after removing the photoresist film from the metal film. 제1항에 있어서, 상기 금속 이온은 알루미늄 이온인 것을 특징으로 하는 반도체 소자의 금속층 형성 방법.The method for forming a metal layer of a semiconductor device according to claim 1, wherein the metal ion is an aluminum ion. 제1항에 있어서, 상기 금속은 알루미늄인 것을 특징으로 하는 반도체 소자의 금속층 형성 방법.The method according to claim 1, wherein the metal is aluminum. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960007103A 1996-03-16 1996-03-16 Metal layer forming method of semiconductor device KR100187686B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960007103A KR100187686B1 (en) 1996-03-16 1996-03-16 Metal layer forming method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960007103A KR100187686B1 (en) 1996-03-16 1996-03-16 Metal layer forming method of semiconductor device

Publications (2)

Publication Number Publication Date
KR970067640A true KR970067640A (en) 1997-10-13
KR100187686B1 KR100187686B1 (en) 1999-06-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960007103A KR100187686B1 (en) 1996-03-16 1996-03-16 Metal layer forming method of semiconductor device

Country Status (1)

Country Link
KR (1) KR100187686B1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100387257B1 (en) * 1999-12-28 2003-06-11 주식회사 하이닉스반도체 Method of forming a metal line in a semiconductor device
KR100451766B1 (en) * 2001-12-22 2004-10-08 주식회사 하이닉스반도체 Method for forming interconnect structures of semiconductor device
KR100585063B1 (en) * 1999-06-15 2006-05-30 삼성전자주식회사 Method for forming a metal layer by a selective electroplating
KR100783274B1 (en) * 2006-11-29 2007-12-06 동부일렉트로닉스 주식회사 Method of manufacturing semiconductor device
KR100825648B1 (en) * 2006-11-29 2008-04-25 동부일렉트로닉스 주식회사 Semiconductor device and method of manufacturing the same

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100429177B1 (en) * 1997-06-30 2004-06-16 주식회사 하이닉스반도체 Line manufacturing method of semiconductor device
KR19990057279A (en) * 1997-12-29 1999-07-15 김영환 Barrier layer formation method of contact hole using ion implantation

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100585063B1 (en) * 1999-06-15 2006-05-30 삼성전자주식회사 Method for forming a metal layer by a selective electroplating
KR100387257B1 (en) * 1999-12-28 2003-06-11 주식회사 하이닉스반도체 Method of forming a metal line in a semiconductor device
KR100451766B1 (en) * 2001-12-22 2004-10-08 주식회사 하이닉스반도체 Method for forming interconnect structures of semiconductor device
KR100783274B1 (en) * 2006-11-29 2007-12-06 동부일렉트로닉스 주식회사 Method of manufacturing semiconductor device
KR100825648B1 (en) * 2006-11-29 2008-04-25 동부일렉트로닉스 주식회사 Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
KR100187686B1 (en) 1999-06-01

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