KR100451766B1 - Method for forming interconnect structures of semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming a metal wiring of a semiconductor device that can improve the reliability by improving the buried characteristics of the metal wiring, comprising the steps of: forming via holes and trenches in the interlayer insulating film on the lower metal wiring; barrier metal layer, catalytic metal layer on the front surface Selectively removing the catalyst metal layer by using a plasma etching process such that the catalyst metal layer remains only inside the via hole and the trench; using the catalyst metal layer serving as a catalyst for the initial stage of the electroless reaction. Filling the metal material within.

Description

METHODS FOR FORMING INTERCONNECT STRUCTURES OF SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to metal wiring of semiconductor devices, and more particularly to a method for forming metal wiring of semiconductor devices suitable for improving the reliability of metal wiring.

Recent semiconductor integrated circuits typically include a multilayer structure separated by an insulating layer, such as silicon dioxide (SiO ₂ ) or silica, for isolation.

In addition, as the degree of integration of semiconductor devices increases, the thickness of the insulating layer is limited to 1 um, and the diameter of the plug is required to be greater than or equal to 5: 1, so the diameter of the plug is 0.25 um to 0.18 um or less. It is decreasing.

Therefore, the properties of the material forming the metal wiring are important. As the plug becomes smaller, the material forming the metal wiring should have a smaller specific resistance for speed performance.

Generally, metals widely used as metal wirings of semiconductor devices include aluminum (Al), aluminum alloys, and tungsten (W).

However, these metals are difficult to be applied to highly integrated semiconductor devices due to the low melting point and high resistivity as the semiconductor devices are highly integrated.

Therefore, as an alternative material of the metal wiring, copper (Cu), gold (Au), silver (Ag), cobalt (Co), chromium (Cr), nickel (Ni), and the like, which have excellent conductivity, are among the materials. Copper and copper alloys, which are low in reliability, excellent in electron migration (EM) and stress migration (SM), and inexpensive to produce, are widely applied.

The method of forming a plug and a metal wiring using copper may be performed by electroplating, physical vapor deposition (PVD), chemical vapor deposition (CVD), or electroless plating (Electroless Plating). Etc.

However, the physical vapor deposition method has a disadvantage in that the step coverage is poor, and the chemical vapor deposition method has a low reliability of electron transfer and a slow deposition rate.

Therefore, a copper seed layer is first formed in the via holes and the trenches, and then a process of filling the via holes and the trenches by copper electroplating is mainly used.

Hereinafter, a method for forming metal wirings of a semiconductor device according to the prior art will be described with reference to the accompanying drawings.

1A to 1F are cross-sectional views illustrating a method of forming metal wirings of a conventional semiconductor device.

In the conventional method of forming metal wirings of a semiconductor device, as shown in FIG. 1A, a lower metal wiring forming trench is formed in an insulating layer 1 on a semiconductor substrate (not shown), and a metal material is embedded in the trench. The lower metal wiring 2 is formed.

Subsequently, a silicon nitride material (SiN) is deposited on the lower metal wire 2 to form a first capping layer 3, and silicon dioxide (SiO ₂ ) is formed on the first capping layer 3. ) Or a low-k material to form an intermetal dielectric 4.

The interlayer insulating layer 4 is selectively etched to form via holes and upper metal wiring trenches.

The etching of the interlayer insulating film 4 is performed by an insulating film etching process including plasma etching.

In addition, techniques for etching silicon dioxide and organic materials may utilize buffered hydrogen fluoride and compounds such as acetone or EKC.

As shown in FIG. 1B, after removing a polymer remaining in the via hole through a cleaning process, the barrier metal layer 5 is formed on the exposed entire surface.

Here, the barrier metal layer 5 is formed by depositing any one of titanium (Ti), titanium nitride layer (TiN), tantalum (Ta), and tantalum nitride layer (TaN) by physical vapor deposition.

The barrier metal layer 5 is formed to a thickness of about 25 to 400 kPa, preferably about 100 kPa.

Currently, a method of depositing TaN, WC, WN, TiSiN, etc. by chemical vapor deposition (CVD) with excellent step coverage is being developed.

Subsequently, as shown in FIG. 1C, a copper seed layer 6 is deposited over the barrier metal layer 5 to provide good adhesion to the metal material filled in the via holes and trenches.

Here, the copper seed layer 6 is formed by depositing to a thickness of 200 to 1000Å by physical vapor deposition or chemical vapor deposition.

As shown in FIG. 1D, copper is electroplated on the copper seed layer 6 to deposit a copper layer 6a to a thickness sufficient to completely fill the via holes and trenches.

Here, as the electrolyte, copper sulfate (CuSO ₄ ) 5H ₂ O, H ₂ SO ₄ and the like are mixed and used at a predetermined concentration. The copper (Cu) concentration is about 17 g / L, CuSO ₄ is about 67 g / L, H ₂ SO ₄ is used at about 170g / L, the electrolyte is supplied at room temperature of about 25 ℃.

In the specific process of electrolytic plating, first, a substrate on which the copper seed layer 6 is formed is loaded into a chamber to be electroplated, and then the substrate is immersed in the electrolyte solution.

At this time, a part of the copper seed layer 6 is dissolved by the sulfuric acid solution (H ₂ SO ₄ ) contained in the electrolytic solution, in which a part where the seed layer is missing occurs.

The copper layer 6a is formed to a thickness such that the via hole is filled by applying a current.

At this time, in the portion where the copper seed layer 6 is removed by sulfuric acid in the state where no current flows, no copper film is deposited and a cavity is formed in the via hole.

Therefore, not only the electrical characteristics but also the reliability of the device is caused.

As shown in Fig. 1E, the copper layer 6a is planarized by Chemical Mechanical Polishing (CMP) method, and the planarization of the copper layer 6a, barrier metal layer 5, and interlayer insulating film 4 is performed during planarization. Some are removed from the top of the structure to form plugs and top metal wiring.

The surface cleaning process removes surface defects and impurity particles caused by chemical mechanical polishing.

In addition, as shown in FIG. 1F, a nitride material is deposited on the surfaces of the interlayer insulating film 4 and the upper metal wiring to form a second capping layer 7.

However, the metal wiring formation method of the conventional semiconductor device as described above has the following problems.

When the barrier metal layer is formed by physical vapor deposition in a pattern having a high step ratio and narrow via holes and trenches, and then the metal material is embedded by electroplating, defects in the copper seed layer serving as an electrically conductive layer for electroplating Poor embedding of the metal wiring filled in the via hole and the trench occurs.

As a result, a cavity is formed in the metal wiring, which increases resistance of the metal wiring and causes a short circuit of the plug.

In addition, since the metal wiring is formed in the upper portion of the region without the via hole and the trench pattern, the dishing phenomenon of the metal wiring and the erosion of the low dielectric constant insulation pattern in an excessive CMP process for removing the metal wiring formed on the upper portion of the structure errosion).

The present invention is to solve the problem of the conventional method of forming a metal wiring of the semiconductor device, the metal of the semiconductor device that can improve the buried characteristics by selectively filling the metal material only in the via hole and the trench using an electroless plating method It is an object of the present invention to provide a wiring forming method.

1A to 1F are cross-sectional views illustrating a method of forming metal wirings of a conventional semiconductor device.

2A to 2F are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention.

Explanation of symbols for the main parts of the drawings

21: insulating layer 22: lower metal wiring

23 diffusion barrier film 24 first interlayer insulating film

25: first hard mask 26: second interlayer insulating film

27: second hard mask 28: barrier metal layer

29 catalyst metal layer 30 copper film

31: protective film

Method for forming a metal wiring of the semiconductor device according to the present invention for achieving the above object comprises the steps of: forming a via hole and a trench in the interlayer insulating film on the lower metal wiring; forming a barrier metal layer, a catalyst metal layer on the front in sequence; the catalyst metal layer Selectively removing the catalyst metal layer using a plasma etching process so as to remain only in the via hole and the trench; filling a metal material in the via hole and the trench using the catalyst metal layer serving as a catalyst for the initial electroless reaction; Characterized in that.

Hereinafter, a method of forming metal wirings of a semiconductor device of the present invention will be described with reference to the accompanying drawings.

2A to 2F are cross-sectional views for explaining a method for forming metal wirings of a semiconductor device according to the present invention.

As shown in FIG. 2A, a trench for forming a lower metal wiring is formed in an insulating layer 21 on a semiconductor substrate (not shown), and a metal material such as copper (Cu), tungsten (W), and aluminum is formed in the trench. Any one of Al is buried to form the lower metal wiring 22.

Next, the diffusion barrier 23, the first interlayer insulating layer 24, the first hard mask 25, the second interlayer insulating layer 26, and the second hard mask 27 are sequentially formed on the lower metal wiring 22. Form.

In this case, the first and second interlayer insulating films 24 and 26 may be coated with a polymer-based low-k material in a spin-on manner, or may be an oxide film containing methyl or etch or a low density. An oxide film is deposited by chemical vapor deposition, and its thickness is formed in the range of 3000 to 10000 kPa.

In addition, the second hard mask 27 is formed by depositing a silicon nitride film or a silicon nitride oxide film containing nitrogen by chemical vapor deposition to prevent copper diffusion.

The via blocking layer 23, the first interlayer insulating layer 24, and the first hard mask 25 may be selectively removed to form a via hole to expose the lower metal wiring 22, and the second interlayer insulating layer ( 26) and the second hard mask 27 are selectively removed to form an upper metal wiring trench.

Here, the process of forming the via hole and the upper metal wiring trench is formed using a single damascene or a dual damascene method, wherein the first and second interlayer insulating films 24 and 26 are etched. Silver is formed by an insulating film etching process including plasma etching, and techniques for etching silicon dioxide and organic materials may use a buffered hydrogen fluoride and a compound such as acetone or EKC.

Subsequently, polymers remaining in the via holes are removed through a cleaning process. When the lower metal wires 22 are formed of tungsten or aluminum, an RF plasma cleaning method using a high frequency power source is performed. If the wiring 22 is copper, the exposed lower metal wiring 22 surface inside the via hole is cleaned by using a reactive cleaning method.

In addition, a barrier metal layer 28 is formed on the entire surface including the via hole and the inside of the trench. At this time, the barrier metal layer 28 is deposited to a thickness of 100 μs or more so that the sidewalls of the via holes have a thickness of 10 μs or more.

Here, the barrier metal layer 28 is deposited by any one of TiNx, Ta, TaNx, TaCx, WxN, TiSiNx, WSiNx using a physical vapor deposition method, or a combination of the metal materials in the ionized physical vapor deposition method ( Deposition is performed using ionized PVD), chemical vapor deposition, or atomic layer deposition (ALD).

As shown in FIG. 2B, a catalyst metal layer 29 serving as a catalyst of a copper ion reduction reaction is formed on the entire surface of the barrier metal layer 28 in order to proceed with electroless plating of copper.

The catalyst metal layer 29 is formed by uniformly depositing palladium (Pd) by sputtering or growing fine particles in an activation bath containing a surface activation solution.

Here, the surface activation solution generally used is the composition of PdCl ₂ (0.2g) + HF (50: 1) (250mL) + HCl (1mL) + Acetic acid (Glacial Acetic acid) (500mL) + H ₂ O (245mL) Using a mixed solution of acetic acid, the acetic acid improves the hydrophilicity of the barrier metal layer 28 to improve the deposition state of palladium (Pd) in the surface activation solution.

However, in the case of the barrier metal layer 28 using TiN, acetic acid is not necessary because TiN has high hydrophilicity.

In the case of forming the catalyst metal layer 29, particles are grown in a surface activation solution in which PdCl ₂ is dissolved such that the concentration of Pd ²⁺ ions is 10 ⁻⁴ to 10 M for 1 to 200 sec.

Next, as illustrated in FIG. 2C, the catalyst metal layer 29 deposited on the second hard mask 27 is selectively removed so that the catalyst metal layer 29 remains only in the via hole and the trench using a plasma etching method. .

At this time, plasma etching using any one of nitrogen, oxygen, hydrogen, O ₃ , NH ₃ or a mixed gas as a source is possible, and proceeds to a single step or a multi-step process.

As shown in FIG. 2D, the copper film 30 is selectively grown only in the via hole and the trench in which the catalyst metal layer 29 is deposited using an electroless plating process.

Here, the copper film 30 is grown in an electroless plating solution at 20 to 100 ° C. The electroless plating solution is CuSO ₄ for supplying a copper cation, formalin for supplying electrons (HCHO), and for extending the life of the solution. It consists of a lotel salt etc. which are added, and pH adjustment solution, surfactant (Surfactant), etc. are added.

The catalyst metal layer 29 serves as a catalyst metal in the early stage of the electroless reaction. Since the reduction reaction of copper ions proceeds only at the site where the catalyst metal layer 29 exists, the copper film 30 is selectively selected only in the via hole and the trench. To grow.

At this time, there is an incubation time, which is because the catalyst metal layer 29 and the barrier metal layer 28 have a lower electrical conductivity than copper, and thus the plating rate is slow. When the via hole and the inner surface of the trench are covered with copper, copper itself Serves as a catalyst to fill the via holes and trenches at high plating rates.

This incubation time depends on the degree of deposition of the catalytic metal layer 29.

Thereafter, as shown in FIG. 2E, the crystal structure of the copper film 30 is stabilized by heat treatment in an in-situ process in a hydrogen reducing atmosphere at a temperature of room temperature to 350 ° C. FIG.

In this case, the hydrogen is used in a reducing atmosphere of hydrogen gas mixture, such as using only the H _{2, or, H 2 + Ar (0~95%} ) or _{H 2 + N 2 (0~95%} ).

Then, the entire surface of the second hard mask 27 is planarized by chemical mechanical polishing (CMP) to remove the barrier metal layer 28 from the upper portion of the structure, and the plug and the upper metal wiring in the via hole and the trench, respectively. To form.

Subsequently, as shown in FIG. 2F, surface defects and impurity particles caused by chemical mechanical polishing are removed through a surface cleaning process, and a copper native oxide film (not shown) formed on the surface of the copper film 30 is shown. After the reduction, the silicon oxide or nitride is deposited on the entire surface including the copper film 30 without being exposed to air to form a passivation 31.

Here, the protective film 31 is formed in order to prevent leakage between the wirings caused by diffusion of copper atoms in the upper metal wirings into the upper interlayer insulating film (not shown).

The metal wiring forming method of the semiconductor device of the present invention as described above has the following effects.

First, by selectively filling copper only in via-holes and trenches using an electroless plating method, metal films can be embedded in small-sized via-holes.

Therefore, there is an effect that can prevent defects and short circuits inside the plug and improve the reliability of the metal wiring.

Second, by selectively forming a metal film only in the via hole and the trench, it is possible to prevent pattern erosion of the copper film and the low dielectric constant insulating film due to the CMP process.

Third, since the deposition of the existing copper seed layer is not required, the process can be simplified, and the production cost can be minimized since the use of a separate copper buried equipment is unnecessary.

Claims (8)

Forming via holes and trenches in the interlayer insulating film on the lower metal interconnection; Sequentially forming a barrier metal layer and a catalyst metal layer on a front surface thereof; Selectively removing the catalyst metal layer using a plasma etching process such that the catalyst metal layer remains only in the via hole and the trench; And filling a metal material into the via hole and the trench by using the catalyst metal layer serving as a catalyst for the initial stage of the electroless reaction. The method of claim 1, The barrier metal layer is formed by depositing a thickness of 100 Å or more to form a thickness of 10 Å or more on the sidewall of the via hole. The method of claim 1, The barrier metal layer may be formed by depositing any one of TiNx, Ta, TaNx, TaCx, WxN, TiSiNx, WSiNx by physical vapor deposition, or a mixture thereof by ionized physical vapor deposition (Ionized PVD), chemical vapor deposition (CVD), or atomic vapor deposition. A metal wiring forming method for a semiconductor device, characterized in that formed by depositing with (ALD). The method of claim 1, The catalyst metal layer is formed by sputtering, or formed by growing in a surface activation solution. The method of claim 4, wherein The surface activation solution is a metal wiring forming method of a semiconductor device, characterized in that the solution of PdCl ₂ dissolved so that the concentration of Pd ^{2 +} ions is 10 ^-4 ~ 10M. The method of claim 1, Selectively removing the catalyst metal layer is performed by plasma etching using any one of nitrogen, oxygen, hydrogen, O ₃ and NH ₃ or a mixture thereof as a source. The method of claim 1, The filling of the metal material in the via hole and the trench may include filling and growing metal particles in an electroless plating solution. The method of claim 1, After the metal material is filled in the via hole and the trench, the metal wiring of the semiconductor device further comprising a heat treatment in a hydrogen reduction atmosphere using any one of H ₂ , H ₂ + Ar, H ₂ + N ₂ . Formation method.