KR100720401B1 - Method for Forming Cu lines in Semiconductor Device - Google Patents

Method for Forming Cu lines in Semiconductor Device Download PDF

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KR100720401B1
KR100720401B1 KR1020010030846A KR20010030846A KR100720401B1 KR 100720401 B1 KR100720401 B1 KR 100720401B1 KR 1020010030846 A KR1020010030846 A KR 1020010030846A KR 20010030846 A KR20010030846 A KR 20010030846A KR 100720401 B1 KR100720401 B1 KR 100720401B1
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copper
interlayer insulating
insulating film
forming
deposited
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KR20020092003A (en
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이병주
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure

Abstract

본 발명은 무전해 도금법을 이용하여 매립특성을 향상시키고 결함없는 구리 매립을 가능하게 한 반도체 소자의 구리 배선 형성 방법에 관한 것으로, 하부 금속 배선이 형성된 기판 상에 층간 절연막을 증착하는 단계와, 상기 층간 절연막을 선택적으로 제거하여 비아 및 트렌치를 형성하는 단계와, 상기 비아 및 트렌치를 포함한 층간 절연막 상에 배리어 금속막을 형성하는 단계와, 상기 비아 및 트렌치를 매립하도록 배리어 금속막이 증착된 전면에 충분히 구리를 증착하는 단계와, 상기 층간 절연막 상부 표면을 엔드 포인트로 하여 평탄화하는 단계와, 상기 평탄화된 층간 절연막 및 매립된 트렌치 표면에 캡핑층을 증착하는 단계를 포함하여 이루어짐을 특징으로 한다.The present invention relates to a method for forming a copper wiring of a semiconductor device which improves a buried property by using an electroless plating method and enables defect-free copper filling, comprising the steps of: depositing an interlayer insulating film on a substrate on which a lower metal wiring is formed; Selectively removing the interlayer insulating film to form vias and trenches, forming a barrier metal film on the interlayer insulating film including the vias and trenches, and having sufficient copper on the entire surface where the barrier metal film is deposited to fill the vias and trenches And depositing a capping layer on the planarized interlayer insulating film and the buried trench surface.

듀얼 다머신(Dual Damascene), EM(ElectroMigration), SM(StressMigration)Dual Damascene, ElectroMigration (EM), Stress Migration (SM)

Description

반도체 소자의 구리 배선 형성 방법 {Method for Forming Cu lines in Semiconductor Device}{Method for Forming Cu lines in Semiconductor Device}

도 1a 내지 도 1e는 본 발명의 반도체 소자의 구리 배선 형성 방법을 나타낸 공정 단면도1A to 1E are cross-sectional views illustrating a method of forming a copper wiring of a semiconductor device of the present invention.

도면의 주요 부분에 대한 부호 설명Explanation of symbols for the main parts of the drawings

11 : 기판 12 : 하부 금속 배선11 substrate 12 lower metal wiring

13 : 제 1 캡핑층 14 : 층간 절연막13 first capping layer 14 interlayer insulating film

15 : 비아 16 : 트렌치15: Via 16: Trench

17 : 배리어 금속막 18 : 구리층17 barrier metal film 18 copper layer

18a : 구리 금속 배선 19 : 제 2 캡핑층18a: copper metal wiring 19: second capping layer

본 발명은 듀얼 다머신 공정을 이용한 반도체 소자의 금속 배선 형성 방법에 관한 것으로 특히, 무전해 도금법을 이용하여 매립 특성을 향상시키고, 결함없는 구리 매립을 가능하게 한 반도체 소자의 구리 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings of semiconductor devices using a dual damascene process, and more particularly, to a method for forming copper wirings for semiconductor devices that improves buried characteristics by using electroless plating and enables defect-free copper filling. will be.

이하, 종래의 반도체 소자의 금속 배선 형성 방법을 설명하면 다음과 같다. Hereinafter, the metal wiring formation method of the conventional semiconductor element is as follows.                         

반도체 소자의 구리 배선을 형성하는 방법으로 듀얼 다머신 방법이 주로 사용되는 데, 듀얼 다머신 방법을 이용한 구리 배선 형성 공정은 다음과 같다.A dual damascene method is mainly used as a method of forming a copper wiring of a semiconductor device, and a copper wiring formation process using the dual damascene method is as follows.

하부 구리 배선이 형성된 기판 상에 제 1 캡핑층, 층간 절연막을 차례로 증착한다. A first capping layer and an interlayer insulating film are sequentially deposited on the substrate on which the lower copper wiring is formed.

상기 층간 절연막, 상기 하부 구리 배선의 소정 영역 노출시키도록 제 1 캡핑층을 선택적으로 제거하여 비아 및 트렌치를 형성한다.Vias and trenches may be formed by selectively removing the first capping layer to expose a predetermined region of the interlayer insulating layer and the lower copper wiring.

비아 및 트렌치를 포함한 기판 전면에 배리어 금속막을 증착한다. A barrier metal film is deposited over the substrate, including vias and trenches.

상기 배리어 금속막 전면에 상부 구리층을 증착한다. An upper copper layer is deposited on the entire barrier metal film.

상부 구리층을 상기 층간 절연막 상부 표면을 엔드 포인트(end point)로 하여 평탄화 공정을 진행하여 상부 구리 배선을 형성하고, 상기 평탄화 완료 후에 표면을 세정한다.The upper copper layer is subjected to a planarization process using the upper surface of the interlayer insulating film as an end point to form an upper copper wiring, and the surface is cleaned after completion of the planarization.

상기 노출된 층간 절연막 및 매립된 상부 구리 배선에 제 2 캡핑층을 증착한다. A second capping layer is deposited on the exposed interlayer insulating film and the buried upper copper wiring.

그러나, 상기와 같은 종래의 반도체 소자의 구리 배선 형성 방법은 다음과 같은 문제점이 있다.However, the copper wiring formation method of the conventional semiconductor device as described above has the following problems.

일반적으로 상부 배선으로 이용되는 구리층의 매립은 전해 도금법이 이용되는 데, 상기 전해 도금법은 초기에 배리어 금속층 상에 구리 시드(seed)층을 증착한다.In general, the embedding of the copper layer used as the upper wiring is an electrolytic plating method, which initially deposits a copper seed layer on the barrier metal layer.

이 때, 상기 구리 시드층은 이온화 물리 기상 증착법(Ionized Physical Vapor Deposition)으로 증착한다. At this time, the copper seed layer is deposited by ionized physical vapor deposition (Ionized Physical Vapor Deposition).

그런데, 집적화로 인해 비아 크기가 작아질 때, 이온화 물리 기상 증착법 중 구리 시드 층이 일부 남게 되어, 후속 구리층 매립 공정시 구리층이 플러그 내부에 채워지지 않는 문제점을 유발시킨다. However, when the via size is reduced due to the integration, a part of the copper seed layer is left in the ionization physical vapor deposition method, which causes a problem that the copper layer is not filled in the plug during the subsequent copper buried process.

또한, 이러한 매립 공정 불량은 배선 간의 도전에도 영향을 끼쳐 배선 신뢰성도 악화시키게 된다. In addition, such a buried process defect also affects the wiring-to-wire conduction, which also degrades the wiring reliability.

본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 무전해 도금법을 이용하여 매립특성을 향상시키고, 결함없는 구리 매립을 가능하게 한 반도체 소자의 구리 배선 형성 방법을 제공하는 데, 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a method for forming a copper wiring of a semiconductor device which improves embedding characteristics by using an electroless plating method and enables defect-free copper filling. .

상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 구리 배선 형성 방법은 하부 금속 배선이 형성된 기판 상에 층간 절연막을 증착하는 단계와, 상기 층간 절연막을 선택적으로 제거하여 비아 및 트렌치를 형성하는 단계와, 상기 비아 및 트렌치를 포함한 층간 절연막 상에 배리어 금속막을 형성하는 단계와, 상기 비아 및 트렌치를 매립하도록 배리어 금속막이 증착된 전면에 충분히 구리를 증착하는 단계와, 상기 층간 절연막 상부 표면을 엔드 포인트로 하여 평탄화하는 단계와, 상기 평탄화된 층간 절연막 및 매립된 트렌치 표면에 캡핑층을 증착하는 단계를 포함하여 이루어짐을 특징으로 한다.In order to achieve the above object, a method of forming a copper wiring of a semiconductor device of the present invention includes depositing an interlayer insulating film on a substrate on which a lower metal wiring is formed, and selectively removing the interlayer insulating film to form vias and trenches. Forming a barrier metal film on the interlayer insulating film including the vias and trenches, depositing sufficient copper on the entire surface where the barrier metal film is deposited so as to fill the vias and trenches; Planarization, and depositing a capping layer on the planarized interlayer insulating film and the buried trench surface.

이하, 첨부된 도면을 참조하여 본 발명의 반도체 소자의 구리 배선 형성 방법을 상세히 설명하면 다음과 같다.  Hereinafter, a copper wiring forming method of a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.                     

도 1a 내지 도 1e는 본 발명의 반도체 소자의 구리 배선 형성 방법을 나타낸 공정 단면도이다.1A to 1E are cross-sectional views illustrating a method for forming a copper wiring of the semiconductor device of the present invention.

도 1a와 같이, 하부 금속 배선(12)이 형성된 기판(11) 상에 제 1 캡핑층(13)을 증착한다. As illustrated in FIG. 1A, the first capping layer 13 is deposited on the substrate 11 on which the lower metal wiring 12 is formed.

상기 제 1 캡핑층(13) 상에 층간 절연막(14)을 증착한다.An interlayer insulating layer 14 is deposited on the first capping layer 13.

상기 층간 절연막(14) 및 제 1 캡핑층(13)을 선택적으로 제거하여 비아(15) 및 트렌치(16)를 형성한다.The interlayer insulating layer 14 and the first capping layer 13 are selectively removed to form the vias 15 and the trenches 16.

이 때, 상기 비아 형성으로 인해 상기 하부 금속 배선(12)의 소정영역이 노출되게 된다.At this time, a predetermined region of the lower metal wire 12 is exposed due to the via formation.

도 1b와 같이, 상기 비아(15) 및 트렌치(16)를 포함한 기판 전면에 배리어 금속막(17)을 증착한다.As illustrated in FIG. 1B, a barrier metal layer 17 is deposited on the entire surface of the substrate including the via 15 and the trench 16.

이 때, 상기 배리어 금속막(17)은 RF 스퍼터링(Radio Frequency sputtering) 세정 또는 수소 환원 세정 공정에 의하여 하부 금속 배선의 표면을 세정한 후, 이온화 물리 기상 증착(Ionized PVD) 공정에 의하여 배리어 금속막(17) 역할을 하는 탄탈륨 (Ta)막을 100내지 800Å의 두께로 증착한다.At this time, the barrier metal film 17 cleans the surface of the lower metal wiring by an RF sputtering or a hydrogen reduction cleaning process, followed by an ionized physical vapor deposition (Ionized PVD) process. (17) A tantalum (Ta) film serving as a film is deposited to a thickness of 100 to 800 kPa.

상기 배리어 금속막(17)을 증착시 사용하는 이온화 물리 기상 증착 방식(Ionized PVD)은 기존의 스퍼터링에 비하여 스텝 커버리지(step coverage)를 크게 향상시킨 방법이다.The ionized physical vapor deposition method (Ionized PVD) used for depositing the barrier metal layer 17 is a method of greatly improving step coverage compared to conventional sputtering.

도 1c와 같이, 상기 비아(15) 및 트렌치(16) 포함한 상기 배리어 금속막(17) 전면에 무전해 도금법을 이용하여 상부 구리층(18)을 매립하는 공정을 진행한다. As shown in FIG. 1C, the upper copper layer 18 is buried in the entire surface of the barrier metal film 17 including the via 15 and the trench 16 by using an electroless plating method.                     

상기 무전해 도금법은 다음과 같다. The electroless plating method is as follows.

상기 배리어 금속막(17) 상에 백금(Pt)층을 50 내지 200Å의 두께로 형성한다.A platinum (Pt) layer is formed on the barrier metal film 17 to a thickness of 50 to 200 GPa.

이어, 구리 무전해 도금법에 의하여, 상기 백금층을 초기 촉매로 이용하여 상부 구리층 매립 공정을 상기 배리어 금속막 (17)전면에서 진행한다.Subsequently, an upper copper layer embedding process is performed on the entire surface of the barrier metal film 17 using the platinum layer as an initial catalyst by a copper electroless plating method.

상기 상부 구리층(18) 매립 공정은 무전해 도금 용액 내에서의 구리(Cu) 이온의 환원 반응에 의하여 진행된다. The upper copper layer 18 embedding process is performed by a reduction reaction of copper (Cu) ions in the electroless plating solution.

구리 무전해 도금 용액은 황산동(금속염 : 구리 이온의 공급 역할), 포르말린(환원제 : 전자의 공급 역할), 롯셀염(착화제 : 용액의 수명 연장을 목적으로 첨가하는 용액) 등으로 구성되며, 도금 온도는 20내지 70℃이며, pH는 9.0 내지 13.0이다.The copper electroless plating solution is composed of copper sulfate (metal salt: supplying copper ions), formalin (reducing agent: supplying electrons), lotel salt (complexing agent: solution added for the purpose of extending the life of the solution). The temperature is 20 to 70 ° C. and the pH is 9.0 to 13.0.

이와 같이, 무전해 도금법을 사용하여 상부 구리층(18)을 도금한 후에는 상기 상부 구리층(18)을 200내지 400℃에서 열처리함으로써, 상부 구리층의 결정 구조를 안정화시킨다.As described above, after plating the upper copper layer 18 using the electroless plating method, the upper copper layer 18 is heat-treated at 200 to 400 ° C. to stabilize the crystal structure of the upper copper layer.

도 1d와 같이, 상기 층간 절연막(14) 표면을 엔드 포인트로 하여 구리 플러그 및 상부 구리 배선(18a)을 제외한 나머지 영역을 제거하는 평탄화 공정을 진행한다.As shown in FIG. 1D, the planarization process of removing the remaining areas except for the copper plug and the upper copper wiring 18a is performed using the surface of the interlayer insulating film 14 as an end point.

이와 같은 평탄화 공정은 표면에 결함이나 불순물 입자 등을 제거하기 위함이다.Such a planarization process is for removing defects or impurity particles on the surface.

상기 평탄화 공정을 통해 구리 플러그 및 상부 구리 배선(18a)이 형성되고, 상기 층간 절연막 표면에 있는 배리어 금속막이 제거되어, 상기 트렌치 및 비아 내부에만 배리어 금속막(17a)이 남게 된다.Through the planarization process, the copper plug and the upper copper wiring 18a are formed, and the barrier metal film on the surface of the interlayer insulating film is removed, so that the barrier metal film 17a remains only inside the trench and the via.

도 1e와 같이, 상기 상부 구리 배선(18a)을 포함한 층간 절연막(14) 전면에 제 2 캡핑층(19)을 증착한다. As illustrated in FIG. 1E, a second capping layer 19 is deposited on the entire surface of the interlayer insulating layer 14 including the upper copper interconnection 18a.

상기 제 2 캡핑층(19)은 SiN 계열의 질화막으로 PECVD(Plasma Enhanced Chemical Vapor Deposition) 공정으로 증착한다. The second capping layer 19 is deposited by a plasma enhanced chemical vapor deposition (PECVD) process using a SiN-based nitride film.

상부 구리 배선(18a) 내의 구리 원자(Cu)가 후속 공정으로 증착될 상부 층간 절연막으로 확산하여 배선 사이의 누설을 유발하는 데, 이를 막기 위해서 상기와 같은 제 2 캡핑층(19)을 증착하는 것이다.Copper atoms (Cu) in the upper copper wiring 18a diffuse into the upper interlayer insulating film to be deposited in a subsequent process, causing leakage between the wirings. In order to prevent this, the second capping layer 19 is deposited. .

상기와 같은 본 발명의 반도체 소자의 구리 배선 형성 방법은 다음과 같은 효과가 있다.The copper wiring forming method of the semiconductor device of the present invention as described above has the following effects.

첫째, 무전해 도금법에 의해서 촉매 층이 증착된 부위에만 구리 매립을 하는 결함없는 구리 매립 공정이 가능하다.First, a defect-free copper embedding process is possible in which the copper is buried only at the site where the catalyst layer is deposited by the electroless plating method.

둘째, 스텝 커버리지 특성이 좋고, 비아 매립 특성이 좋아 비아 크기가 작아짐에 따른 구리 플러그 내부의 결함 및 비아 단락을 방지할 수 있다.Second, it is possible to prevent defects and via short circuits inside the copper plug as the size of the via becomes small due to good step coverage characteristics and good via filling characteristics.

셋째, 구리 배선의 신뢰성(EM, SM등의 특성)이 안정화 될 수 있다.Third, the reliability (characteristics of EM, SM, etc.) of the copper wiring can be stabilized.

넷째, 무전해 도금법을 이용함으로써, 기존의 구리 시드(seed) 층 증착 및 구리 매립 장비의 사용이 불필요하다.Fourth, by using an electroless plating method, the use of existing copper seed layer deposition and copper embedding equipment is unnecessary.

다섯째, 집적도를 높인 보다 작은 크기의 비아에서도 무전해 도금법에 의하 여 구리 매립층을 형성할 수 있다. Fifth, even a smaller via having increased density can form a copper buried layer by electroless plating.

Claims (8)

하부 금속 배선이 형성된 기판 상에 층간 절연막을 증착하는 단계;Depositing an interlayer insulating film on a substrate on which lower metal wirings are formed; 상기 층간 절연막을 선택적으로 제거하여 비아 및 트렌치를 형성하는 단계;Selectively removing the interlayer dielectric to form vias and trenches; 상기 비아 및 트렌치를 포함한 상기 층간 절연막 상에 배리어 금속막을 100 내지 800Å의 두께로 증착하여 형성하는 단계;Depositing a barrier metal film on the interlayer insulating film including the vias and trenches to a thickness of 100 to 800 占 퐉; 상기 비아 및 트렌치를 매립하도록 상기 배리어 금속막이 증착된 전면에 충분히 구리를 증착하는 단계;Depositing sufficient copper on the entire surface where the barrier metal film is deposited so as to fill the vias and trenches; 상기 층간 절연막 상부 표면을 엔드 포인트로 하여 평탄화하는 단계;Planarizing the upper surface of the interlayer insulating film as an end point; 상기 평탄화된 층간 절연막 및 매립된 트렌치 표면에 캡핑층을 증착하는 단계를 포함하여 이루어짐을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.And depositing a capping layer on the planarized interlayer insulating film and the buried trench surface. 삭제delete 제 1항에 있어서, 상기 배리어 금속막은 Ta으로 증착함을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The method of claim 1, wherein the barrier metal film is deposited by Ta. 제 3항에 있어서, 상기 Ta는 이온화 물리 기상 증착법으로 증착함을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The method of claim 3, wherein Ta is deposited by ionization physical vapor deposition. 제 1항에 있어서, 무전해 도금법을 이용하여 구리 매립 공정을 진행함을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The method for forming a copper wiring of a semiconductor device according to claim 1, wherein the copper embedding step is performed by using an electroless plating method. 제 5항에 있어서, Pt를 초기 촉매로 사용함을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The method for forming a copper wiring of a semiconductor device according to claim 5, wherein Pt is used as an initial catalyst. 제 6항에 있어서, 상기 Pt를 이온화 물리 기상 증착법으로 증착함을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.The method of claim 6, wherein the Pt is deposited by an ionized physical vapor deposition method. 제 6항에 있어서, 상기 Pt를 50 내지 200Å의 두께의 층으로 형성함을 특징으로 하는 반도체 소자의 구리 배선 형성 방법.7. The method for forming a copper wiring of a semiconductor device according to claim 6, wherein said Pt is formed into a layer having a thickness of 50 to 200 kPa.
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