KR101107229B1 - Method of Forming Metal Interconnect of the Semiconductor Device - Google Patents
Method of Forming Metal Interconnect of the Semiconductor Device Download PDFInfo
- Publication number
- KR101107229B1 KR101107229B1 KR1020040113066A KR20040113066A KR101107229B1 KR 101107229 B1 KR101107229 B1 KR 101107229B1 KR 1020040113066 A KR1020040113066 A KR 1020040113066A KR 20040113066 A KR20040113066 A KR 20040113066A KR 101107229 B1 KR101107229 B1 KR 101107229B1
- Authority
- KR
- South Korea
- Prior art keywords
- copper
- forming
- layer
- metal wiring
- barrier
- Prior art date
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 55
- 239000002184 metal Substances 0.000 title claims abstract description 55
- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 81
- 239000010949 copper Substances 0.000 claims abstract description 81
- 229910052802 copper Inorganic materials 0.000 claims abstract description 81
- 230000004888 barrier function Effects 0.000 claims abstract description 57
- 239000010410 layer Substances 0.000 claims abstract description 51
- 238000009792 diffusion process Methods 0.000 claims abstract description 28
- 239000011229 interlayer Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims abstract description 10
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052707 ruthenium Inorganic materials 0.000 claims abstract description 8
- 238000000059 patterning Methods 0.000 claims abstract description 7
- 238000007772 electroless plating Methods 0.000 claims abstract description 6
- 239000007864 aqueous solution Substances 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 239000000243 solution Substances 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 238000009429 electrical wiring Methods 0.000 abstract 1
- 238000000231 atomic layer deposition Methods 0.000 description 5
- 230000009977 dual effect Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000005751 Copper oxide Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로서, 보다 상세하게는 반도체 기판 상부에 구리 배리어막 및 하부 구리 배선을 포함하는 절연막을 형성하는 단계; 상기 하부 구리 배선의 노출된 표면에 구리 캡핑막을 형성하는 단계; 상기 구리 캡핑막이 형성된 반도체 기판 상부에 확산방지막, 제1층간절연막, 식각방지막, 제2층간절연막 및 캡핑막의 적층 구조를 형성하는 단계; 상기 적층구조를 패터닝하여 상기 확산방지막을 노출시키는 비아홀 및 상부 금속 배선 영역을 형성하는 단계; 상기 비아홀 하부의 확산방지막 및 구리 캡핑막을 제거하여 상기 하부 구리 배선을 노출시키는 단계; 및 상기 비아홀 및 상부 금속 배선 영역을 매립하는 배리어 금속층 및 구리를 증착하여 금속 배선을 형성하는 단계를 포함하는 반도체 소자의 금속 배선 형성 방법에 관한 것이다. 본 발명의 방법을 이용하면 금속 배리어 층의 두께를 최소화하여 구리 금속 배선의 저항을 줄일 수 있고, 구리와 확산방지막 간의 전기적이동을 방지하여 금속 배선의 신뢰성을 확보할 수 있으므로, 반도체 소자의 금속 배선 공정에 유용하게 사용될 수 있다.The present invention relates to a method for forming metal wiring of a semiconductor device, and more particularly, forming an insulating film including a copper barrier layer and a lower copper wiring on a semiconductor substrate; Forming a copper capping film on an exposed surface of the lower copper wiring; Forming a stacked structure of a diffusion barrier layer, a first interlayer dielectric layer, an etch barrier layer, a second interlayer dielectric layer, and a capping layer on the semiconductor substrate on which the copper capping layer is formed; Patterning the stacked structure to form a via hole and an upper metal wiring region exposing the diffusion barrier layer; Exposing the lower copper interconnection by removing the diffusion barrier and the copper capping layer under the via hole; And depositing a barrier metal layer filling the via hole and the upper metal wiring region and copper to form a metal wiring. By using the method of the present invention, the thickness of the metal barrier layer can be minimized to reduce the resistance of the copper metal wiring, and the electrical wiring between the copper and the diffusion barrier can be prevented, thereby ensuring the reliability of the metal wiring. It can be usefully used in the process.
구리 캡핑막, 무전해 도금, 루테늄Copper Capping Film, Electroless Plating, Ruthenium
Description
도 1은 본 발명에 따른 반도체 소자의 금속 배선 형성 공정을 보여주는 모식도이다.1 is a schematic diagram showing a metal wiring formation process of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호 설명>Description of the Related Art [0002]
11 ; 확산방지막, 12 ; 층간절연막,11; Diffusion barrier, 12; Interlayer insulation film,
13,23 ; 구리 배리어(barrier) 막, 14,24 ; 구리 배선,13,23; Copper barrier films, 14,24; Copper wiring,
15,25 ; 구리 캡핑막, 16,26 ; 확산방지막,15,25; Copper capping film, 16,26; Diffusion Barrier,
17 ; 제1층간절연막, 18 ; 식각방지막,17; A first interlayer
19 ; 제2층간절연막, 20 ; 캡핑막,19; A second interlayer insulating film; Capping Film,
21 ; 비아, 22 ; 상부 금속21; Via, 22; Upper metal
본 발명은 금속 배선의 형성 방법에 관한 것으로서, 보다 상세하게는 구리 금속 배리어 막으로 루테늄(ruthenium)을 사용하고, 상기 구리 금속 표면에 구리 캡핑막을 증착하는 단계를 추가로 포함하는 것을 특징으로 하는 금속 배선 형성 방 법에 관한 것이다.The present invention relates to a method for forming a metal wiring, and more particularly, using ruthenium as a copper metal barrier film, and further comprising depositing a copper capping film on the copper metal surface. It relates to a wiring forming method.
CMOS (complementary metal oxide semiconductor) 로직 디바이스(logic device)의 속도 증가는 주로 게이트(gate) 길이의 감소에 의한 게이트 지연(delay) 시간을 줄이는 것에 의존하여 왔으나, 반도체 소자가 집적화될수록 BEOL (back end of line)의 금속화로 인한 RC (resistance capacitance) 지연이 디바이스의 속도를 좌우하게 된다. 이러한 RC 지연을 줄이기 위해 알루미늄 대신 저항이 낮은 구리를 금속으로 사용하고 유전체(dielectric)로 로우-케이(low-k) 물질을 사용하여 다마신(damascene) 방식으로 패턴을 형성한 후 CMP (chemical mechanical polishing) 공정을 통해 최종적인 금속배선을 완성하게 된다.Increasing the speed of complementary metal oxide semiconductor (CMOS) logic devices has largely relied on reducing the gate delay time due to the reduction of the gate length, but as semiconductor devices become more integrated, BEOL (back end of Resistance capacitance (RC) delay due to metallization of the line determines the speed of the device. To reduce this RC delay, a low-resistance copper instead of aluminum is used as the metal, and a low-k material is used as the dielectric to form a pattern in a damascene manner, followed by CMP (chemical mechanical). The polishing process completes the final metallization.
이와 관련하여, 종래의 구리 듀얼(dual) 다마신 공정은 CMP 공정이 진행된 구리 표면과 확산방지층과의 계면이 취약하여 접촉력 부족에 의한 금속 배선의 신뢰성이 저하된다는 문제점이 있었다. 또한, 구리가 대기중에 노출되는 시간이 길어지면 구리 산화막이 빠르게 성장하여 콘택저항이 증가되기 때문에, 종래의 구리 듀얼 다마신 공정에서는 구리 표면이 드러나는 모든 공정과 후속 공정과의 시간 관리를 필수적으로 요하게 된다. 아울러, 종래의 방식에 의하면 구리 배리어(barrier) 금속으로 PVD (physical vapor deposition)에 의한 Ta 또는 TaN을 사용하기 때문에 스텝 커버리지(step coverage)가 열악하여 구리가 IMD (inter metal dielectric)로 확산될 가능성이 높으며, 따라서 최소 100 내지 300Å 정도 두께의 배리어 막질을 필요로하기 때문에 금속 배선의 저항이 증대되는 등의 문제점이 있었다.In this regard, the conventional copper dual damascene process has a problem in that the interface between the copper surface and the diffusion barrier layer where the CMP process is performed is weak and the reliability of the metal wiring due to insufficient contact force is lowered. In addition, since the copper oxide film grows rapidly and the contact resistance is increased when the copper is exposed to the air for a long time, the conventional copper dual damascene process requires time management with all processes where the copper surface is exposed and subsequent processes. do. In addition, according to the conventional method, since Ta or TaN by physical vapor deposition (PVD) is used as the copper barrier metal, the step coverage is poor and copper may be diffused into the intermetal dielectric (IMD). This is high, and therefore, there is a problem in that the resistance of the metal wiring is increased because a barrier film quality of at least about 100 to 300 mW is required.
본 발명은 상기와 같은 종래 금속 배선 형성 방법상의 문제점을 해결하기 위하여 안출된 것으로서, CMP 완료된 구리 표면을 캡핑하여 구리의 확산 및 산화를 방지하고, 구리 배리어 금속으로 루테늄을 이용하여 구리의 확산을 방지함으로써 구리 배선의 저항을 감소시켜 RC 지연을 개선하는 단계를 포함하는 반도체 소자의 금속 배선 형성 방법을 제공하는 것을 목적으로 한다.The present invention has been made to solve the problems of the conventional metal wiring formation method as described above, to prevent the diffusion and oxidation of copper by capping the CMP completed copper surface, and to prevent the diffusion of copper using ruthenium as the copper barrier metal. It is therefore an object of the present invention to provide a method for forming a metal wiring of a semiconductor device, the method including reducing the resistance of the copper wiring to improve RC delay.
상기 목적을 달성하기 위하여, 본 발명은 반도체 기판 상부에 구리 배리어막 및 하부 구리 배선을 포함하는 절연막을 형성하는 단계; 상기 하부 구리 배선의 노출된 표면에 구리 캡핑막을 형성하는 단계; 상기 구리 캡핑막이 형성된 반도체 기판 상부에 확산방지막, 제1층간절연막, 식각방지막, 제2층간절연막 및 캡핑막의 적층 구조를 형성하는 단계; 상기 적층구조를 패터닝하여 상기 확산방지막을 노출시키는 비아홀 및 상부 금속 배선 영역을 형성하는 단계; 상기 비아홀 하부의 확산방지막 및 구리 캡핑막을 제거하여 상기 하부 구리 배선을 노출시키는 단계; 및 상기 비아홀 및 상부 금속 배선 영역을 매립하는 배리어 금속층 및 구리를 증착하여 금속 배선을 형성하는 단계를 포함하는 반도체 소자의 금속 배선 형성 방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of forming an insulating film including a copper barrier film and a lower copper wiring on the semiconductor substrate; Forming a copper capping film on an exposed surface of the lower copper wiring; Forming a stacked structure of a diffusion barrier layer, a first interlayer dielectric layer, an etch barrier layer, a second interlayer dielectric layer, and a capping layer on the semiconductor substrate on which the copper capping layer is formed; Patterning the stacked structure to form a via hole and an upper metal wiring region exposing the diffusion barrier layer; Exposing the lower copper interconnection by removing the diffusion barrier and the copper capping layer under the via hole; And depositing a barrier metal layer filling the via hole and the upper metal wiring region and copper to form a metal wiring.
이하, 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail.
본 발명의 반도체 소자의 금속 배선 형성 방법은The metal wiring formation method of the semiconductor element of this invention is
1) 반도체 기판 상부에 구리 배리어막 및 하부 구리 배선을 포함하는 절연막을 형성하는 단계; 1) forming an insulating film including a copper barrier film and a lower copper wiring on the semiconductor substrate;
2) 상기 하부 구리 배선의 노출된 표면에 구리 캡핑막을 형성하는 단계;2) forming a copper capping film on the exposed surface of the lower copper wiring;
3) 상기 구리 캡핑막이 형성된 반도체 기판 상부에 확산방지막, 제1층간절연막, 식각방지막, 제2층간절연막 및 캡핑막의 적층 구조를 형성하는 단계;3) forming a stacked structure of a diffusion barrier, a first interlayer dielectric, an etch barrier, a second interlayer dielectric and a capping layer on the semiconductor substrate on which the copper capping layer is formed;
4) 상기 적층구조를 패터닝하여 상기 확산방지막을 노출시키는 비아홀 및 상부 금속 배선 영역을 형성하는 단계;4) patterning the stacked structure to form a via hole and an upper metal wiring region exposing the diffusion barrier layer;
5) 상기 비아홀 하부의 확산방지막 및 구리 캡핑막을 제거하여 상기 하부 구리 배선을 노출시키는 단계; 및5) exposing the lower copper wiring by removing the diffusion barrier and the copper capping layer under the via hole; And
6) 상기 비아홀 및 상부 금속 배선 영역을 매립하는 배리어 금속층 및 구리를 증착하여 금속 배선을 형성하는 단계를 포함한다.6) forming a metal wiring by depositing a barrier metal layer and copper filling the via hole and the upper metal wiring region.
도 1a를 참조하면, 반도체 하부 소자 위에 확산방지막(11), 층간절연막(12)을 증착한 후 마스크와 식각을 통해 패터닝을 수행한다. 이때, 상기 확산방지막은 SiC 또는 SiN인 것이 바람직하다. 패터닝 후 ALD (atomic layer deposition) 방식을 이용하여 구리 배리어 막(13)을 증착하고 시드(seed) 구리와 전기도금에 의해 구리(14)를 증착한다. 상기 구리 배리어 막은 루테늄인 것이 바람직하지만 반드시 여기에 한정되는 것은 아니며, 상기 루테늄 막의 두께는 30Å 이하의 얇은 두께인 것이 바람직하다.Referring to FIG. 1A, after the
도 1b를 참조하면, CMP 방법으로 하부 구리 금속 배선(14)을 정의한 후 무전해 도금액을 이용하여 CoWP 또는 CoWB를 선택적으로 구리 표면에 도포하여 구리 캡핑막(15)을 형성한다. 이때, 상기 무전해 도금액은 CoCl2 수용액, H2C6H
5O7 수용액, H2WO4 수용액 및 (CH3)2NH 수용액으로 구성된 군으로부터 선택될 수 있으며, 도금조(bath)의 온도는 70 내지 75℃, pH는 9.0 내지 9.5 범위인 것이 바람직하다.Referring to FIG. 1B, after defining the lower
도 1c를 참조하면, 전체표면 상부에 확산방지막(16), 제1층간절연막(17), 식각방지막(18), 제2층간절연막(19) 및 캡핑막(20)을 순차적으로 증착한다. 이때, 상기 확산방지막, 식각방지막 및 캡핑막은 SiC 또는 SiN을 사용하는 것이 바람직하다.Referring to FIG. 1C, a
도 1d를 참조하면, 비아홀을 패터닝하여 개구부를 형성한다. 이때, 구리 캡핑막은 비아 과다 식각시 식각방지막으로 사용된다.Referring to FIG. 1D, the via holes are patterned to form openings. In this case, the copper capping layer is used as an etch stop layer when the via is excessively etched.
도 1e를 참조하면, 전체 표면에 대하여 마스크 및 식각 공정을 통해 상부 메탈 형성을 위한 듀얼 다마신 패턴을 형성하여 비아(21) 및 상부 금속(22)을 정의한다. 이때, 상기 구리 캡핑막(15)은 상부 금속을 식각할 때 상부 금속 마스크시 사용되는 BARC에 의해 보호받다가 포토레지스트막 제거 후 확산방지막(16)을 제거할 때 같이 식각되어 제거되어 버린다.Referring to FIG. 1E, the
도 1f를 참조하면, ALD (atomic layer deposition) 방식으로 배리어 금속(23), 바람직하게는 루테늄을 증착한 후 시드(seed)와 전기도금에 의해 구리를 증착하고, CMP를 통해 듀얼 다마신 금속 배선(24)을 형성한다. 이후, 도 2에서와 동일한 방법으로 무전해 도금에 의해 구리 캡핑막(25)을 형성한 후 확산방지막(26)을 증착한다.Referring to FIG. 1F, the
상기에서 살펴본 바와 같이, 본 발명의 방법을 이용하면 금속 배리어 층으로 ALD 증착 방식에 의한 루테늄을 사용함으로써 두께를 최소화하여 구리 금속 배선의 저항을 줄일 수 있고, 무전해 도금애 의한 구리 캡핑막을 형성하여 구리와 확산방지막 간의 전기적이동을 방지하여 금속 배선의 신뢰성을 확보할 수 있으며, 아울러 후속하는 비아 형성 단계에서 과다 식각에 의해 확산 방지막에 펀치쓰루(punchthrough)가 발생하여도 O2 포토레지스트 스트립에 의한 CuO의 형성이 방지되어 배선의 신뢰성을 증가시킬 수 있다.As described above, by using the method of the present invention, by using ruthenium by the ALD deposition method as the metal barrier layer, it is possible to minimize the thickness to reduce the resistance of the copper metal wiring, to form a copper capping film by electroless plating prevent electrical transfer between copper and diffusion barrier to possible to ensure the reliability of the metal wiring and, as well as also by the punch-through (punchthrough) to the film spread by means of over-etch in the subsequent via-forming step that occurs due to the O 2 photoresist strip Formation of CuO can be prevented to increase the reliability of the wiring.
Claims (9)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040113066A KR101107229B1 (en) | 2004-12-27 | 2004-12-27 | Method of Forming Metal Interconnect of the Semiconductor Device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040113066A KR101107229B1 (en) | 2004-12-27 | 2004-12-27 | Method of Forming Metal Interconnect of the Semiconductor Device |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20060074346A KR20060074346A (en) | 2006-07-03 |
KR101107229B1 true KR101107229B1 (en) | 2012-01-25 |
Family
ID=37167116
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020040113066A KR101107229B1 (en) | 2004-12-27 | 2004-12-27 | Method of Forming Metal Interconnect of the Semiconductor Device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR101107229B1 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100770533B1 (en) * | 2006-08-30 | 2007-10-25 | 동부일렉트로닉스 주식회사 | Semiconductor device and method for manufacturing the semiconductor device |
KR100737701B1 (en) | 2006-08-31 | 2007-07-10 | 동부일렉트로닉스 주식회사 | Method of manufacturing wire in a semiconductor device |
KR100850076B1 (en) * | 2006-12-21 | 2008-08-04 | 동부일렉트로닉스 주식회사 | structure of Cu metallization for retading the Cu corrosion |
US7888798B2 (en) | 2007-05-16 | 2011-02-15 | Samsung Electronics Co., Ltd. | Semiconductor devices including interlayer conductive contacts and methods of forming the same |
KR101048744B1 (en) * | 2008-09-19 | 2011-07-14 | 서울대학교산학협력단 | Cobalt Alloy-based Multilayer Diffusion Film Formation by Electroless Plating |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19990072753A (en) * | 1998-02-23 | 1999-09-27 | 가나이 쓰도무 | Semiconductor device and fabrication method thereof |
KR20020092003A (en) * | 2001-06-01 | 2002-12-11 | 주식회사 하이닉스반도체 | Method for Forming Cu lines in Semiconductor Device |
KR100545196B1 (en) * | 2002-07-26 | 2006-01-24 | 동부아남반도체 주식회사 | Method for forming metal line of semiconductor device |
-
2004
- 2004-12-27 KR KR1020040113066A patent/KR101107229B1/en active IP Right Grant
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19990072753A (en) * | 1998-02-23 | 1999-09-27 | 가나이 쓰도무 | Semiconductor device and fabrication method thereof |
KR20020092003A (en) * | 2001-06-01 | 2002-12-11 | 주식회사 하이닉스반도체 | Method for Forming Cu lines in Semiconductor Device |
KR100545196B1 (en) * | 2002-07-26 | 2006-01-24 | 동부아남반도체 주식회사 | Method for forming metal line of semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
KR20060074346A (en) | 2006-07-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6821879B2 (en) | Copper interconnect by immersion/electroless plating in dual damascene process | |
US6528884B1 (en) | Conformal atomic liner layer in an integrated circuit interconnect | |
KR100482180B1 (en) | Fabricating method of semiconductor device | |
KR100558009B1 (en) | Method of fabricating a semiconductor device forming a diffusion barrier layer selectively and a semiconductor device fabricated thereby | |
US20030008243A1 (en) | Copper electroless deposition technology for ULSI metalization | |
US20020090806A1 (en) | Copper dual damascene interconnect technology | |
US7879720B2 (en) | Methods of forming electrical interconnects using electroless plating techniques that inhibit void formation | |
EP1330842B1 (en) | Low temperature hillock suppression method in integrated circuit interconnects | |
US6469385B1 (en) | Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers | |
KR100265615B1 (en) | Manufacturing method of a metal line for a semiconductor | |
US6482755B1 (en) | HDP deposition hillock suppression method in integrated circuits | |
KR100939773B1 (en) | Metal line of semiconductor device and method for manufacturing the same | |
KR101107229B1 (en) | Method of Forming Metal Interconnect of the Semiconductor Device | |
KR100341482B1 (en) | Method for manufacturing copper interconnections | |
US6518648B1 (en) | Superconductor barrier layer for integrated circuit interconnects | |
US20020127849A1 (en) | Method of manufacturing dual damascene structure | |
KR101107746B1 (en) | method of forming a metal line in semiconductor device | |
KR20070005870A (en) | Method of forming a copper wiring in a semiconductor device | |
KR100424714B1 (en) | Method for fabricating copper interconnect in semiconductor device | |
KR100945503B1 (en) | Method for forming metal interconnection layer of semiconductor device | |
KR20070068920A (en) | Method for forming metal layer in semiconductor damascene manufacturing process | |
KR20020053610A (en) | Method of fabricating conductive lines and interconnections in semiconductor devices | |
US6979903B1 (en) | Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers | |
US6403474B1 (en) | Controlled anneal conductors for integrated circuit interconnects | |
KR101098920B1 (en) | Method for manufacturing semicondoctor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20141222 Year of fee payment: 4 |
|
FPAY | Annual fee payment |
Payment date: 20151217 Year of fee payment: 5 |
|
FPAY | Annual fee payment |
Payment date: 20161220 Year of fee payment: 6 |
|
FPAY | Annual fee payment |
Payment date: 20171218 Year of fee payment: 7 |
|
FPAY | Annual fee payment |
Payment date: 20181218 Year of fee payment: 8 |
|
FPAY | Annual fee payment |
Payment date: 20191217 Year of fee payment: 9 |