KR100623332B1 - Method for forming metal line of semiconductor device - Google Patents

Method for forming metal line of semiconductor device Download PDF

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KR100623332B1
KR100623332B1 KR1020000037275A KR20000037275A KR100623332B1 KR 100623332 B1 KR100623332 B1 KR 100623332B1 KR 1020000037275 A KR1020000037275 A KR 1020000037275A KR 20000037275 A KR20000037275 A KR 20000037275A KR 100623332 B1 KR100623332 B1 KR 100623332B1
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film
copper
layer
fsg
forming
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KR20020002911A (en
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이병주
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02131—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being halogen doped silicon oxides, e.g. FSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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Abstract

본 발명은 이중 데머신(Damascene) 공정을 이용하여 반도체소자의 금속배선을 형성하는 방법에 관한 것으로, ILD층에 비아 및 트랜치를 형성하고, ILD층 중에서 FSG막의 표면을 질화처리하여, 방습 및 구리이온의 확산을 방지하는 역할을 하는 장벽층으로서의 질화막을 형성한다. 본 발명은 질화막을 형성시켜 구리원자의 확산을 막는 베리어 특성을 높이고, FSG막의 흡습을 방지할 수 있기 때문에, 흡습 방지를 위하여 신속히 후속공정을 진행할 필요가 없고 또한 흡습으로 인하여 소자의 성능(RC 시간지연)과 신뢰성(EM,SM)이 저하되는 것을 방지할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring of a semiconductor device using a double damascene process, wherein vias and trenches are formed in an ILD layer, and a surface of an FSG film is nitrided in an ILD layer to provide moisture and copper A nitride film is formed as a barrier layer that serves to prevent diffusion of ions. In the present invention, since the barrier property to prevent diffusion of copper atoms by forming a nitride film can be improved, and the moisture absorption of the FSG film can be prevented, it is not necessary to proceed to the subsequent process quickly to prevent moisture absorption, and the performance of the device due to the moisture absorption (RC time Delay) and reliability (EM, SM) can be prevented.

금속배선, 구리배선, 데머신, 전자 빔, 질화막, ILD, FSGMetal wiring, copper wiring, demachine, electron beam, nitride film, ILD, FSG

Description

반도체소자의 금속배선 형성방법{Method for forming metal line of semiconductor device} Method for forming metal line of semiconductor device             

도 1a 및 도 1b는 본 발명에 있어서 ILD층에 비아 홀과 트렌치를 동시에 형성하는 공정을 나타낸 단면도이다.1A and 1B are cross-sectional views illustrating a process of simultaneously forming a via hole and a trench in an ILD layer in the present invention.

도 2는 도 1b의 일부 표면을 질화시키는 공정을 나타낸 단면도이다.FIG. 2 is a cross-sectional view illustrating a process of nitriding a part of the surface of FIG. 1B.

도 3은 도 2의 구조물 상부전면에 장벽층을 형성하는 공정을 나타낸 단면도이다.3 is a cross-sectional view illustrating a process of forming a barrier layer on an upper surface of the structure of FIG. 2.

도 4 및 도 5는 도 3의 장벽층 위에 금속 플러그 및 배선을 형성하는 공정을 나타낸 단면도이다.4 and 5 are cross-sectional views illustrating a process of forming a metal plug and a wiring on the barrier layer of FIG. 3.

도 6은 금속 플러그 및 배선의 형성 후 확산 방지층을 형성한 것을 나타낸 단면도이다.6 is a cross-sectional view illustrating the formation of a diffusion barrier layer after formation of a metal plug and wiring.

*도면의 주요 부분에 대한 부호의 설명*              * Description of the symbols for the main parts of the drawings *

10: 반도체기판 11: 절연막10: semiconductor substrate 11: insulating film

13: 하부 FSG막 14: SiN막13: lower FSG film 14: SiN film

15: 상부 FSG막 17: 질화막15: upper FSG film 17: nitride film

18: TaN막 19: 구리층18: TaN film 19: copper layer

20: 캡핑층20: capping layer

본 발명은 반도체소자의 금속배선에 관한 것으로, 특히 이중 데머신(Damascene) 공정을 이용하여 반도체소자의 금속배선을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to metallization of semiconductor devices, and more particularly, to a method of forming metallization of semiconductor devices using a double damascene process.

일반적으로 반도체 소자의 고집적화, 고속화를 실현하기 위하여 배선공정에서는 RC 시간지연을 감소시켜야 하며,금속 플러그의 스텝 커러리지와 매립특성을 향상시켜야 한다.In general, in order to realize high integration and high speed of semiconductor devices, the RC time delay should be reduced in the wiring process, and the step coverage and embedding characteristics of the metal plug should be improved.

그런데, 종래에는 SiOF(silicon oxyfluoride, 이하 FSG라 칭함)막과 구리배선을 사용하였는데, 이 FSG막(k~3.5)을 층간절연(inter layer dielectric, 이하 ILD라 칭함)층으로 사용하는 경우, 비아(via)가 형성된 FSG막에 습기가 흡수되어 비아저항이 증가하는 문제점이 발생하며, 비아 단락(fail)의 직접적인 원인이 되기도 하였다. 또한, 구리 플러그의 형성전에 미리 증착하는 장벽메탈(barrier matal)층의 스텝 커버리지가 좋지 않을 경우에도 장벽 특성이 나빠져서 비아 저항을 증가시키며, 비아 단락을 일이키기도 한다. 그 밖에, RC 시간지연이 증가하여 반도체소자의 동작속도가 느려지고, 제품의 신뢰성이 떨어지며, 구리배선 사이에 누설전류 가 증가하고, 수율이 감소하는 문제점을 유발한다. However, in the past, a SiOF (silicon oxyfluoride) film and a copper wiring were used. When the FSG film (k to 3.5) is used as an interlayer dielectric (hereinafter referred to as an ILD) layer, a via is used. Moisture is absorbed by the FSG film in which the via is formed, which causes a problem of increasing the via resistance, which may be a direct cause of via short circuit. In addition, even when the step coverage of the barrier metal layer deposited before the formation of the copper plug is not good, the barrier property is deteriorated to increase the via resistance, and cause via short circuit. In addition, the RC time delay is increased, the operation speed of the semiconductor device is slowed, the reliability of the product is deteriorated, the leakage current is increased between the copper wiring, and the yield is reduced.

따라서, FSG막과 구리배선을 사용하여 금속배선공정을 완성하려면, FSG막의 방습과 구리 플러그의 장벽특성 및 매립특성을 향상시키기 위한 기술이 요구되고 있다.Therefore, in order to complete a metal wiring process using an FSG film | membrane and copper wiring, the technique for improving the moisture resistance of an FSG film | membrane, the barrier property of a copper plug, and a buried characteristic is calculated | required.

따라서, 본 발명은 이와 같은 종래의 문제점을 해결하기 위해 안출한 것으로서, FSG막의 방습과 구리 플러그의 장벽특성 및 매립특성을 향상시킬 수 있는 반도체소자의 금속배선을 형성하는 방법을 제공함을 목적으로 한다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device capable of improving the moisture resistance of the FSG film and the barrier property and the buried property of the copper plug. .

본 발명의 다른 목적은 FSG막의 표면을 질화처리하여, 방습 및 구리이온의 확산을 방지하는 역할을 하는 장벽층을 형성하는 반도체소자의 금속배선을 형성하는 방법을 제공함을 목적으로 한다.
Another object of the present invention is to provide a method for forming a metal wiring of a semiconductor device to form a barrier layer that serves to prevent the moisture-proof and diffusion of copper ions by nitriding the surface of the FSG film.

이와 같은 목적을 달성하기 위한 본 발명은 반도체기판 위에 형성된 ILD층에 비아 및 트랜치를 형성하는 단계; 탈가스 공정과 전자 빔 처리공정을 진행하여 상기 ILD층의 상부와 상기 비아 및 트랜치의 일부분에 질화막을 형성하는 단계; 고주파 스퍼터링에 의한 세정공정을 실시하는 단계; 접착층 및 베리어 역할을 하는 메탈층을 상기 질화막이 형성된 구조물 전면에 형성하는 단계; 상기 메탈층 위에 구리를 매립한 후, 구리 플러그 및 배선부분을 제외한 나머지 부분을 제거하여 평탄 화하는 단계; 및 상기 구리 플러그 및 배선부분이 형성된 구조물 전면에 캡핑층을 형성하는 단계로 구성되는 것을 특징으로 한다.The present invention for achieving the above object comprises the steps of forming vias and trenches in the ILD layer formed on the semiconductor substrate; Performing a degassing process and an electron beam treatment process to form a nitride film on top of the ILD layer and a portion of the via and trench; Performing a cleaning process by high frequency sputtering; Forming a metal layer serving as an adhesive layer and a barrier on the entire structure of the nitride film; Embedding copper on the metal layer and removing the planarized portions except for the copper plug and the wiring portion; And forming a capping layer on the front surface of the structure in which the copper plug and the wiring portion are formed.

이하, 본 발명의 실시예를 첨부 도면을 참조하여 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

먼저, 도 1a 및 도 1b를 참조하면, 트랜지스터가 형성된 반도체기판(10) 위에 절연막(11)을 증착한 후, 절연막(11)의 소정부분에 하부 구리배선(12)을 형성한다. 그 다음, 하부 FSG막(13)과 SiN막(14) 그리고 상부 FSG막(15)을 PECVD 방법으로 순차적으로 증착하여 ILD층을 형성한다. 그 다음, 노광 및 식각 공정에 의하여 비아(14b)와 트랜치(16)를 동시에 형성한다. 즉, 비아(14b)가 형성될 부분(14a)에 SiN막(14)을 노광 및 식각공정에 의하여 제거하고, 상부 FSG막(15)을 증착한 다음, 트랜치 식각하면 비아(14b)와 트랜치(16)가 동시에 형성되는데, 이때 SiN막(14)은 식각정지층(etch stop layer) 역할을 한다.First, referring to FIGS. 1A and 1B, an insulating film 11 is deposited on a semiconductor substrate 10 on which a transistor is formed, and then a lower copper wiring 12 is formed on a predetermined portion of the insulating film 11. Next, the lower FSG film 13, the SiN film 14, and the upper FSG film 15 are sequentially deposited by PECVD to form an ILD layer. Then, vias 14b and trenches 16 are simultaneously formed by exposure and etching processes. That is, the SiN film 14 is removed by the exposure and etching process on the portion 14a where the via 14b is to be formed, the upper FSG film 15 is deposited, and the trench is etched to form the via 14b and the trench ( 16) are formed at the same time, wherein the SiN film 14 serves as an etch stop layer.

그 다음, 도 2에 도시된 바와 같이, 웨이퍼를 300℃~500℃에서 약 100초 이내로 유지하여 탈가스(degas)시킨 후, 질소(N2)의 분위기에서 전자 빔(electron beam) 처리하여 하부 FSG막(13) 및 상부 FSG막(15)의 노출된 표면을 질화처리시킨다. 이때, 상부 FSG막(15)의 표면과 비아(14b) 및 트랜치(16)의 측벽이 질화되어, 질화막(17)이 형성된다. FSG막(15)을 질화처리하여 형성된 질화막(17)은 방습특성과 구리원자의 확산을 막는 베리어(barrier) 역할을 한다. 상기 전자 빔 처리공정의 경우 처리온도가 300℃~400℃이며, 처리시간이 10분 이내이다. 이는 다른 공정의 진행온도와 비슷한 수준이므로, 웨이퍼에 써멀 스트레스(thermal stress)에 의한 열충격을 유발하지 않는다.Next, as shown in FIG. 2, the wafer is maintained at 300 ° C. to 500 ° C. within about 100 seconds to degas, and then treated with an electron beam in an atmosphere of nitrogen (N 2 ). The exposed surfaces of the FSG film 13 and the upper FSG film 15 are nitrided. At this time, the surface of the upper FSG film 15 and the sidewalls of the vias 14b and the trench 16 are nitrided to form the nitride film 17. The nitride film 17 formed by nitriding the FSG film 15 serves as a barrier to prevent moisture-proof characteristics and diffusion of copper atoms. In the case of the electron beam treatment process, the treatment temperature is 300 ℃ ~ 400 ℃, the treatment time is within 10 minutes. This is similar to the progress temperature of other processes, and thus does not cause thermal shock on the wafer due to thermal stress.

그 다음, 고주파(RF) 스퍼터링에 의한 세정공정을 실시하여, 질화막(17) 및 하부 구리배선(12)의 표면을 세정한다. 그 다음, 도 3에 도시된 바와 같이, 상기 결과물 전면에 접착층 및 베리어 매탈층 역할을 하는 TaN막(18)을 스퍼터링 방법으로 300Å~1000Å의 두께로 증착한다. 여기서, 질화막(17)에 의하여 베리어 특성이 이미 강화되었기 때문에, 상기 TaN막(18)은 기존의 공정에 비하여 얇게 증착해도 무방하다. 그리고, 비아의 어스펙트 비가 클 경우에는 TaN막(18)의 스퍼터링 증착시에 스텝 커버리지를 향상시킬 수 있는 조준(collimated) 또는 IMP(Ionized Metal Plasma) 방식을 사용한다.Next, a cleaning process by high frequency (RF) sputtering is performed to clean the surfaces of the nitride film 17 and the lower copper wiring 12. Next, as shown in FIG. 3, a TaN film 18 serving as an adhesive layer and a barrier metal layer is deposited on the entire surface of the resultant to a thickness of 300 kPa to 1000 kPa by a sputtering method. Here, since the barrier properties have already been enhanced by the nitride film 17, the TaN film 18 may be deposited thinner than the conventional process. When the aspect ratio of the via is large, a collimated or ionized metal plasma (IMP) method may be used to improve step coverage during sputter deposition of the TaN film 18.

그 다음, 도 4에 도시된 바와 같이, 상기 TaN막(18) 위에 구리를 매립하여 구리층(19)을 형성한다. 이때, 구리의 매립방법으로는 무전해도금, 전해도금, 스퍼터링, CVD 방법이 모두 가능하다, 그러나, 매립특성 및 물성이 우수한 전도도금 방법이 바람직하다. 구리 전해도금을 이용할 경우에는 구리시드(seed)층을 100Å~1000Å의 두께로 상기 TaN막(18) 위에 미리 증착해야 한다.Next, as shown in FIG. 4, copper is embedded on the TaN film 18 to form a copper layer 19. At this time, as a method of embedding copper, electroless plating, electroplating, sputtering, and CVD methods can all be used. However, a conductive plating method having excellent embedding characteristics and physical properties is preferable. When copper electroplating is used, a copper seed layer must be deposited on the TaN film 18 in a thickness of 100 kV to 1000 kPa in advance.

그 다음, 도 5에 도시된 바와 같이, 구리 CMP 방법의 단독사용 또는 전해폴리싱과 CMP의 동시사용에 의하여 구리 플러그 및 배선부분(19a)을 제외한 나머지 부분을 제거하여, 구리층(19)을 평탄화한다.Then, as shown in FIG. 5, the copper layer 19 is planarized by removing the remaining portions except the copper plug and the wiring portion 19a by single use of copper CMP method or simultaneous use of electrolytic polishing and CMP. do.

그 다음, 도 6에 도시된 바와 같이, 구리 플러그 및 배선부분(19a)가 형성된 구조물 전면에 SiN으로 이루어진 캡핑(capping)층(20)을 증착하여, 구리배선을 완성한다. 이 캡핑층(20)은 구리원자가 상부 ILD(미도시)층으로 확산되는 것을 막기 위한 것이다.Next, as shown in FIG. 6, a capping layer 20 made of SiN is deposited on the entire surface of the structure on which the copper plug and the wiring portion 19a are formed, thereby completing copper wiring. This capping layer 20 is intended to prevent copper atoms from diffusing into the upper ILD (not shown) layer.

이상에서 살펴 본 바와 같이, 본 발명은 금속배선을 형성하기 위하여 유전상수가 작은 FSG막과 비저항이 작은 구리배선을 사용하기 때문에, 금속배선의 RC 시간지연을 감소시켜 반도체소자의 성능을 향상시킬 수 있다. As described above, in the present invention, since the FSG film having the low dielectric constant and the copper wiring having the small specific resistance are used to form the metal wiring, the RC time delay of the metal wiring can be reduced to improve the performance of the semiconductor device. have.

또한, 본 발명은 FSG막을 전자 빔 처리하여 질화막을 형성시켜 구리원자의 확산을 막는 베리어 특성을 높이고, FSG막의 흡습을 방지할 수 있기 때문에, 흡습 방지를 위하여 신속히 후속공정을 진행할 필요가 없고 또한 흡습으로 인하여 소자의 성능(RC 시간지연)과 신뢰성(EM,SM)이 저하되는 것을 방지할 수 있다.In addition, the present invention can increase the barrier property of preventing the diffusion of copper atoms by forming an nitride film by electron beam treatment of the FSG film, and can prevent moisture absorption of the FSG film. Therefore, it is not necessary to proceed to the subsequent step quickly to prevent moisture absorption. Therefore, the performance (RC time delay) and reliability (EM, SM) of the device can be prevented from being lowered.

또한, 본 발명에 의하면, 상기 전자 빔 처리공정의 경우 처리온도가 300℃~400℃이며, 처리시간이 10분 이내이므로, 반도체소자에 써멀 스트레스를 포함한 열충격을 유발하지 않는다.In addition, according to the present invention, in the electron beam treatment process, since the treatment temperature is 300 ° C. to 400 ° C. and the treatment time is within 10 minutes, the semiconductor device does not cause thermal shock including thermal stress.

또한, 본 발명에 의하면, 상기 질화막에 의하여 베리어 특성이 이미 강화되었기 때문에, 상기 TaN막의 두께를 기존의 공정에 비하여 줄일 수 있다.In addition, according to the present invention, since the barrier property is already enhanced by the nitride film, the thickness of the TaN film can be reduced as compared with the existing process.

Claims (6)

반도체 기판 위에 하부 FSG막, SiN막 및 상부 FSG막이 순차 적층된 ILD층을 형성하는 단계;Forming an ILD layer in which a lower FSG film, an SiN film, and an upper FSG film are sequentially stacked on the semiconductor substrate; 상기 ILD층에 비아 및 트랜치를 형성하는 단계; Forming vias and trenches in the ILD layer; 탈가스 공정과 전자 빔 처리공정을 진행하여 상기 ILD층의 상부와 상기 비아 및 트랜치의 일부분에 질화막을 형성하는 단계;Performing a degassing process and an electron beam treatment process to form a nitride film on top of the ILD layer and a portion of the via and trench; 고주파 스퍼터링에 의한 세정공정을 실시하는 단계;Performing a cleaning process by high frequency sputtering; 접착층 및 베리어 역할을 하는 TaN막을 상기 질화막이 형성된 구조물 전면에 형성하는 단계;Forming a TaN film, which serves as an adhesive layer and a barrier, on the entire structure of the nitride film; 상기 TaN막 위에 구리를 매립한 후, 구리 플러그 및 배선부분을 제외한 나머지 부분을 제거하여 평탄화하는 단계; 및 Embedding copper on the TaN film, and then removing the planarized portion except for the copper plug and the wiring portion; And 상기 구리 플러그 및 배선부분이 형성된 구조물 전면에 캡핑층을 형성하는 단계로 구성되는 반도체소자의 금속배선 형성방법.Forming a capping layer on the front surface of the structure in which the copper plug and the wiring portion is formed. 제1항에 있어서, 상기 ILD층의 하부 FSG막, SiN막 및 상부 FSG막은 PECVD 방법으로 형성되는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein the lower FSG film, the SiN film, and the upper FSG film of the ILD layer are formed by a PECVD method. 제1항에 있어서, 상기 질화막은 The method of claim 1, wherein the nitride film 웨이퍼를 300℃~500℃에서 10분 이내로 유지하여 탈가스시킨 후 N2의 분위기에서 전자 빔 처리하여, 상기 ILD층 중에서 하부 FSG막 및 상부 FSG막의 노출된 표면을 질화시켜 형성되는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The wafer is maintained within 300 minutes at 300 ° C. to 500 ° C. for degassing, followed by electron beam treatment in an atmosphere of N 2 to form nitrides of the exposed surfaces of the lower FSG film and the upper FSG film in the ILD layer. Metal wiring formation method of a semiconductor device. 제1항에 있어서, 상기 TaN막은 스퍼터링 방법으로 300Å~1000Å의 두께로 증착하여 형성되는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.2. The method of claim 1, wherein the TaN film is formed by depositing a thickness of 300 mW to 1000 mW by a sputtering method. 제1항에 있어서, 상기 구리를 매립하는 공정은 The method of claim 1, wherein the step of embedding copper 무전해도금, 전해도금, 스퍼터링, CVD 방법 중에서 선택된 하나이고, 구리 전해도금을 이할할 경우에는 구리시드층을 100Å~1000Å의 두께로 상기 메탈층 위에 미리 증착하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.A metal selected from the group consisting of electroless plating, electroplating, sputtering, and CVD, and in the case of copper electroplating, a copper seed layer is deposited in advance on the metal layer to a thickness of 100 kV to 1000 kPa. Wiring formation method. 제1항에 있어서, 상기 캡핑층은 SiN으로 이루어진 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein the capping layer is formed of SiN.
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