KR100332118B1 - Method of forming a metal wiring in a semiconductor device - Google Patents
Method of forming a metal wiring in a semiconductor device Download PDFInfo
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- KR100332118B1 KR100332118B1 KR1019990025433A KR19990025433A KR100332118B1 KR 100332118 B1 KR100332118 B1 KR 100332118B1 KR 1019990025433 A KR1019990025433 A KR 1019990025433A KR 19990025433 A KR19990025433 A KR 19990025433A KR 100332118 B1 KR100332118 B1 KR 100332118B1
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- copper
- layer
- via contact
- forming
- trench
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- 238000000034 method Methods 0.000 title claims abstract description 69
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 38
- 239000002184 metal Substances 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 239000010949 copper Substances 0.000 claims abstract description 80
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 75
- 229910052802 copper Inorganic materials 0.000 claims abstract description 73
- 230000008569 process Effects 0.000 claims abstract description 24
- 238000007772 electroless plating Methods 0.000 claims abstract description 22
- 230000004888 barrier function Effects 0.000 claims abstract description 19
- 238000009792 diffusion process Methods 0.000 claims abstract description 19
- 238000007517 polishing process Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 87
- 238000004140 cleaning Methods 0.000 claims description 20
- 239000011229 interlayer Substances 0.000 claims description 19
- 238000005240 physical vapour deposition Methods 0.000 claims description 14
- 238000005229 chemical vapour deposition Methods 0.000 claims description 12
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 9
- 239000011810 insulating material Substances 0.000 claims description 9
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 229910001431 copper ion Inorganic materials 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 7
- 238000007747 plating Methods 0.000 claims description 7
- WSFSSNUMVMOOMR-UHFFFAOYSA-N Formaldehyde Chemical compound O=C WSFSSNUMVMOOMR-UHFFFAOYSA-N 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 150000003839 salts Chemical class 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 230000009977 dual effect Effects 0.000 claims description 5
- 239000000654 additive Substances 0.000 claims description 3
- 230000000996 additive effect Effects 0.000 claims description 3
- 239000003638 chemical reducing agent Substances 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 3
- 229910000365 copper sulfate Inorganic materials 0.000 claims description 3
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 2
- 229910021645 metal ion Inorganic materials 0.000 claims 1
- 230000008021 deposition Effects 0.000 abstract description 4
- 230000007547 defect Effects 0.000 abstract description 2
- 239000002002 slurry Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 239000003054 catalyst Substances 0.000 description 4
- 238000006722 reduction reaction Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- -1 or the like Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 무전해 도금법을 이용하여, 비아 콘택홀 및 트렌치에만 구리를 선택적으로 양호하게 매립할 수 있는 기술이다. 본 발명은 비아 콘택홀 및 트렌치가 형성된 웨이퍼의 표면에 확산 장벽층 및 구리 시드층을 형성하고, 선택적 구리 증착을 위해 비아 콘택홀 및 트렌치 부분이 덮히는 마스크층을 형성하고, 비아 콘택홀 및 트렌치 이외의 부분에 노출된 구리 시드층 및 확산 장벽층을 제거하고, 무전해 도금법을 이용한 구리 증착법으로 비아 콘택홀 및 트렌치에 구리 매립층을 형성하고, 이후 연마 공정 및 캡핑층 형성 공정을 진행한다. 이러한 공정으로 얻어지는 구리 매립층은 매립 특성이 우수하여, 구리 매립층의 보이드 및 키홀과 같은 내부 결함을 줄일 수 있어 금속 배선에 대한 신뢰성, 안정성 및 성능을 향상시킬 수 있을뿐만 아니라, 연마 공정의 진행시간과 슬러리 등의 소모품의 사용량을 줄일 수 있어 원가 절감 및 생산성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and is a technique capable of selectively filling copper only in via contact holes and trenches using an electroless plating method. The present invention forms a diffusion barrier layer and a copper seed layer on the surface of the wafer on which the via contact hole and the trench are formed, and forms a mask layer covering the via contact hole and the trench portion for selective copper deposition, and the via contact hole and the trench. The copper seed layer and the diffusion barrier layer exposed to other portions are removed, and a copper buried layer is formed in the via contact hole and the trench by copper deposition using an electroless plating method, and then a polishing process and a capping layer forming process are performed. The copper buried layer obtained by this process has excellent buried characteristics, which can reduce internal defects such as voids and keyholes of the copper buried layer, thereby improving reliability, stability, and performance of metal wiring, It is possible to reduce the use of consumables such as slurry to reduce costs and improve productivity.
Description
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 무전해 도금법을 이용하여 비아 콘택홀 및 트렌치에만 구리를 선택적으로 양호하게 매립하면서 연마 공정을 용이하게 실시할 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and in particular, to form metal wirings in semiconductor devices that can easily carry out polishing processes by selectively filling copper only in via contact holes and trenches using an electroless plating method. It is about a method.
반도체 산업이 초대규모 집적 회로(Ultra Large Scale Integration; ULSI)로 옮겨 가면서 소자의 지오메트리(geometry)가 서브-하프-마이크로(sub-half-micron) 영역으로 계속 줄어드는 반면, 성능 향상 및 신뢰도 측면에서 회로 밀도(circuit density)는 증가하고 있다. 이러한 요구에 부응하여, 반도체 소자의 금속 배선을 형성함에 있어서 구리 박막은 알루미늄에 비해 녹는점이 높아 전기이동도(electro-migration; EM)에 대한 저항이 커서 반도체 소자의 신뢰성을 향상시킬 수 있고, 비저항이 낮아 신호전달 속도를 증가시킬 수 있어, 집적 회로(integration circuit)에 유용한 상호연결 재료(interconnection material)로 사용되고 있다.As the semiconductor industry moves to Ultra Large Scale Integration (ULSI), the geometry of the device continues to shrink to the sub-half-micron region, while improving circuitry in terms of performance and reliability. Circuit density is increasing. In response to these demands, the copper thin film has a higher melting point than aluminum in forming metal wirings of the semiconductor device, and thus has high resistance to electro-migration (EM), thereby improving reliability of the semiconductor device and providing a specific resistance. This low rate can increase the signal transfer rate, making it a useful interconnect material for integration circuits.
현재, 사용이 가능한 구리 매립 방법으로는 물리기상증착(PVD)법/리플로우 (reflow), 화학기상증착법(CVD), 전해 도금(Electroplating)법, 무전해 도금(Electroless-plating)법 등이 있으며, 이들 중에서 선호되는 방법은 구리 매립 특성이 비교적 양호하며 공정이 널리 알려진 전해 도금법과 화학기상증착법이다. 한편, 무전해 도금법은 반도체 소자의 제조 공정에 아직 널리 사용되고 있지는 않으나 스텝 커버리지가 우수하여 매립 특성이 양호한 것으로 알려져 있다. 그러나, 반도체 소자의 고집적화에 따라 비아 콘택홀의 크기가 감소하고, 어스펙트 비가 증가하게 되었고, 이로 인해 점점 열악해지는 구리 매립 특성을 향상시키고자하는 방안이 연구 개발 중이다.Currently available copper embedding methods include physical vapor deposition (PVD) / reflow, chemical vapor deposition (CVD), electroplating, and electroless-plating. Among them, preferred methods are electroplating and chemical vapor deposition, which have a relatively good copper embedding property and are well known. On the other hand, the electroless plating method is not yet widely used in the manufacturing process of a semiconductor device, but is known to have excellent buried characteristics due to its excellent step coverage. However, due to the high integration of semiconductor devices, the size of the via contact hole is reduced and the aspect ratio is increased. Accordingly, a method for improving copper embedding characteristics, which is worsened, is being researched and developed.
구리 매립 특성이 불량할 경우에는 비아 콘택홀의 저항이 높거나 구리 플러그가 단락(fail)되는 문제가 발생한다. 또한 반도체 소자의 속도가 느려지며(RC time delay 증가), 신뢰성이 열악해지고, 수율이 감소하는 문제점이 발생한다.If the copper buried property is poor, a high resistance of the via contact hole or a shortage of the copper plug may occur. In addition, there is a problem that the speed of the semiconductor device becomes slow (increased RC time delay), the reliability becomes poor, and the yield decreases.
따라서, 본 발명은 매립 특성이 양호한 무전해 도금법을 이용한 구리(Cu) 증착법으로 비아 콘택홀 및 트렌치에만 구리를 선택적으로 매립하면서 연마 공정을 용이하게 실시할 수 있게하여, 금속 배선에 대한 신뢰성, 안정성, 성능 및 생산성을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention enables the polishing process to be easily carried out by selectively embedding copper only in via contact holes and trenches by the copper (Cu) deposition method using the electroless plating method having good buried characteristics, thereby providing reliability and stability for metal wiring. It is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device capable of improving performance and productivity.
이러한 목적을 달성하기 위한 본 발명의 반도체 소자의 금속 배선 형성 방법은 하지층상에 층간 절연막을 형성한 후, 상기 층간 절연막의 일부분을 식각하여 비아 콘택홀 및 트렌치를 형성하는 단계; 클리닝 공정을 실시한 후, 상기 비아 콘택홀 및 트렌치를 포함한 상기 층간 절연막 표면에 확산 장벽층 및 구리 시드층을 형성하는 단계; 상기 비아 콘택홀 및 트렌치가 덮히는 마스크층을 형성한 후, 노출된 상기 구리 시드층 및 확산 장벽층을 제거하는 단계; 상기 마스크층을 제거한 후, 구리의 무전해 도금 공정으로 상기 비아 콘택홀 및 트렌치에만 구리 매립층을선택적으로 형성하는 단계; 및 연마 공정을 실시하여 구리 금속 배선을 형성하고, 웨이퍼의 표면에 캡핑층을 전면 증착하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, a method of forming a metal wiring of a semiconductor device according to an embodiment of the present invention may include forming a via contact hole and a trench by forming an interlayer insulating film on an underlayer and then etching a portion of the interlayer insulating film; After the cleaning process, forming a diffusion barrier layer and a copper seed layer on a surface of the interlayer insulating layer including the via contact hole and the trench; Forming a mask layer covering the via contact hole and the trench, and then removing the exposed copper seed layer and the diffusion barrier layer; After removing the mask layer, selectively forming a copper buried layer only in the via contact hole and the trench by an electroless plating process of copper; And forming a copper metal wiring by performing a polishing process, and depositing a capping layer on the entire surface of the wafer.
도 1a 내지 도 1d는 본 발명의 제 1 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.1A to 1D are cross-sectional views of a device for explaining a method of forming metal wirings in a semiconductor device according to a first embodiment of the present invention.
도 2a 내지 도 2c는 본 발명의 제 2 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.2A to 2C are cross-sectional views of a device for explaining a method of forming metal wirings in a semiconductor device according to a second embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11, 21: 하지층 12, 22: 층간 절연막11, 21: base layer 12, 22: interlayer insulating film
13, 23: 비아 콘택홀 14, 24: 트렌치13, 23: via contact hole 14, 24: trench
15, 25: 확산 장벽층 16, 26: 구리 시드층15, 25: diffusion barrier layer 16, 26: copper seed layer
17, 27: 구리 매립층 167, 267: 구리 금속 배선17, 27: copper buried layer 167, 267: copper metal wiring
18, 28: 캡핑층 100: 마스크층18, 28: capping layer 100: mask layer
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d는 본 발명의 제 1 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1D are cross-sectional views of devices for explaining a method of forming metal wirings in a semiconductor device according to a first embodiment of the present invention.
도 1a를 참조하면, 하지층(11)상에 층간 절연막(12)을 형성한 후, 층간 절연막(12)의 일부분을 식각하여 비아 콘택홀(13) 및 트렌치(14)를 형성한다. 클리닝(cleaning) 공정을 실시한 후, 비아 콘택홀(13) 및 트렌치(14)를 포함한 층간 절연막(12) 표면에 확산 장벽층(15)을 형성한다. 무전해 도금 공정을 진행하기 위해 촉매 역할을 하는 구리 시드층(16)을 확산 장벽층(15) 상에 형성한다.Referring to FIG. 1A, after forming the interlayer insulating layer 12 on the base layer 11, a portion of the interlayer insulating layer 12 is etched to form the via contact hole 13 and the trench 14. After the cleaning process, the diffusion barrier layer 15 is formed on the surface of the interlayer insulating layer 12 including the via contact hole 13 and the trench 14. A copper seed layer 16 is formed on the diffusion barrier layer 15 to serve as a catalyst for the electroless plating process.
상기에서, 하지층(11)은 반도체 기판, 폴리실리콘(poly-Si), 텅스텐(W), 알루미늄(Al), 구리(Cu) 등과 같은 전도성 물질로 형성된 층이거나, 절연 물질로 형성된 층이다. 층간 절연막(12)은 낮은 유전 상수(low k)를 갖는 절연 물질로 형성한다. 비아 콘택홀(13) 및 트렌치(14)는 듀얼 다마신(dual damascene) 방식으로 형성한다.In the above, the base layer 11 is a layer formed of a conductive material such as a semiconductor substrate, polysilicon (poly-Si), tungsten (W), aluminum (Al), copper (Cu), or the like, or a layer formed of an insulating material. The interlayer insulating film 12 is formed of an insulating material having a low dielectric constant (low k). The via contact hole 13 and the trench 14 are formed in a dual damascene method.
클리닝 공정은 하지층(11)이 텅스텐(W)이나 알루미늄(Al)과 같은 금속일 경우 고주파 플라즈마(RP plasma)를 이용하고, 하지층(11)이 구리(Cu)일 경우 리액티브 클리닝(reactive cleaning) 방식을 적용하며, 하지층(11)이 절연 물질일 경우 스퍼터링(sputtering) 방식을 적용하고, 이외에도 NF3클리닝, 습식(wet) 클리닝이 있다. 확산 장벽층(15)은 ionized PVD TiN, CVD TiN, MOCVD TiN, ionized PVD Ta, ionized PVD TaN, CVD Ta, CVD TaN, CVD WN 중 적어도 어느 하나로 형성하며, 100 내지 700Å 두께의 접착층과 100 내지 1000Å 두께의 베리어 메탈층이 적층되어 있다.The cleaning process uses high frequency plasma (RP plasma) when the base layer 11 is a metal such as tungsten (W) or aluminum (Al), and reactive cleaning when the base layer 11 is copper (Cu). The cleaning method is applied, and if the base layer 11 is an insulating material, a sputtering method is applied. In addition, there are NF 3 cleaning and wet cleaning. The diffusion barrier layer 15 is formed of at least one of ionized PVD TiN, CVD TiN, MOCVD TiN, ionized PVD Ta, ionized PVD TaN, CVD Ta, CVD TaN, and CVD WN, and has an adhesive layer having a thickness of 100 to 700 GPa and a thickness of 100 to 1000 GPa. The barrier metal layer of thickness is laminated | stacked.
구리 시드층(16)은 스퍼터링법, 화학기상증착법, 메탈 이온 플라즈마(Ionic Metal Plasma; IMP)-물리기상증착법 등으로 100 내지 1000Å의 두께로 증착한다. 구리 시드층(16)은 스텝 커버리지가 우수하여야 한다.The copper seed layer 16 is deposited to a thickness of 100 to 1000 mW by sputtering, chemical vapor deposition, Ionic Metal Plasma (IMP) -physical vapor deposition, or the like. The copper seed layer 16 should have good step coverage.
도 1b를 참조하면, 선택적 구리 증착을 위해 비아 콘택홀(13) 및 트렌치(14)가 덮히는(close) 마스크층(100)을 형성한 후, 노출된 구리 시드층(16) 및 확산 장벽층(15)을 순차적으로 제거하고, 이로 인하여 구리 시드층(16)은 비아 콘택홀(13) 및 트렌치(14) 내부에만 존재하게 된다.Referring to FIG. 1B, after forming the mask layer 100 in which the via contact holes 13 and the trenches 14 are closed for selective copper deposition, the exposed copper seed layer 16 and the diffusion barrier layer are formed. (15) is sequentially removed, which causes the copper seed layer 16 to exist only within the via contact holes 13 and trenches 14.
상기에서, 마스크층(100)은 구리의 무전해 도금 공정시 구리가 도금될 부분을 보호하는 역할을 하며, 포토레지스트(photoresist)와 같은 물질로 형성 가능하다. 구리 시드층(16) 및 확산 장벽층(15)의 제거를 위한 식각 방법으로는 건식 식각, 반응성 이온 식각(Reactive Ion Etch; RIE) 등이 가능하다.In the above, the mask layer 100 serves to protect the portion to be copper plated during the electroless plating process of copper, it may be formed of a material such as photoresist (photoresist). Etching methods for removing the copper seed layer 16 and the diffusion barrier layer 15 may be dry etching, reactive ion etching (RIE), or the like.
도 1c를 참조하면, 마스크층(100)을 제거한 후, 무전해 도금법을 이용한 구리 증착법으로 비아 콘택홀(13) 및 트렌치(14) 내에 구리 매립층(17)을 선택적으로형성한다.Referring to FIG. 1C, after removing the mask layer 100, a copper buried layer 17 is selectively formed in the via contact hole 13 and the trench 14 by copper deposition using an electroless plating method.
구리의 매립 작용은 무전해 도금 용액 내에서의 구리 이온의 환원 반응에 의하여 진행된다. 이때, 구리 시드층(16)은 구리 이온 환원 반응의 촉매 작용을 한다. 무전해 구리 도금 용액은 구리 이온을 공급하는 금속염인 황산동과, 전자를 공급하는 환원제인 포르말린과, 용액의 수명 연장을 목적으로 첨가하는 첨가제인 롯셀염 등으로 이루어지며, 도금 온도는 20 내지 70℃, pH는 9.0 내지 13.0 이다. 무전해 구리 도금 공정은 스텝 커버리지 특성과 비아 매립 특성이 우수한 공정이다. 한편, 비아 콘택홀의 크기와 어스펙트 비가 서로 다르거나, 트렌치의 깊이와 폭이 서로 다른 경우에도 무전해 도금에 의해 동시 매립이 가능하다.The buried action of copper proceeds by the reduction reaction of copper ions in the electroless plating solution. At this time, the copper seed layer 16 serves as a catalyst for the copper ion reduction reaction. The electroless copper plating solution consists of copper sulfate, a metal salt for supplying copper ions, formalin, a reducing agent for supplying electrons, and rossel salt, an additive added for the purpose of extending the life of the solution. The plating temperature is 20 to 70 ° C. , pH is 9.0 to 13.0. The electroless copper plating process has excellent step coverage and via filling properties. Meanwhile, even when the size and aspect ratio of the via contact hole are different from each other, or the depth and width of the trench are different from each other, simultaneous filling may be performed by electroless plating.
도 1d를 참조하면, 무전해 도금 공정으로 형성된 구리 매립층(17) 표면의 불필요한 부분을 화학적 기계적 연마(CMP) 공정으로 제거하고, 포스트-클리닝(post-cleaning) 공정을 실시하여 비아 콘택홀(13) 및 트렌치(14) 내에 구리 금속 배선(167)을 형성한다. 이후, 웨이퍼의 표면에 캡핑층(18)을 전면 증착한다.Referring to FIG. 1D, unnecessary portions of the surface of the copper buried layer 17 formed by the electroless plating process are removed by a chemical mechanical polishing (CMP) process, and a post-cleaning process is performed to form the via contact hole 13. And a copper metal wiring 167 in the trench 14. Thereafter, the capping layer 18 is entirely deposited on the surface of the wafer.
상기에서, 캡핑층(18)은 구리 금속 배선(167)으로부터 구리 원자가 이후에 구리 금속 배선(167) 상부쪽에 형성될 층간 절연막으로 확산하는 것을 막는 역할을 하며, 주로 실리콘 나이트라이드(SiN)로 형성한다. 이로써, 듀얼 다마신 공정에 의한 최종적인 구리 금속 배선이 완성된다.In the above, the capping layer 18 serves to prevent diffusion of copper atoms from the copper metal wiring 167 to the interlayer insulating film to be formed later on the copper metal wiring 167, and is mainly formed of silicon nitride (SiN). do. This completes the final copper metal wiring by the dual damascene process.
도 2a 내지 도 2c는 본 발명의 제 2 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도이다.2A to 2C are cross-sectional views of devices for describing a method for forming metal wirings in a semiconductor device according to a second embodiment of the present invention.
도 2a를 참조하면, 하지층(21)상에 층간 절연막(22)을 형성한 후, 층간 절연막(22)의 일부분을 식각하여 비아 콘택홀(23) 및 트렌치(24)를 형성한다. 클리닝(cleaning) 공정을 실시한 후, 비아 콘택홀(23) 및 트렌치(24)를 포함한 층간 절연막(22) 표면에 확산 장벽층(25)을 형성한다. 무전해 도금 공정을 진행하기 위해 촉매 역할을 하는 구리 시드층(26)을 확산 장벽층(25) 상에 형성한다.Referring to FIG. 2A, after the interlayer insulating layer 22 is formed on the base layer 21, a portion of the interlayer insulating layer 22 is etched to form the via contact hole 23 and the trench 24. After performing a cleaning process, a diffusion barrier layer 25 is formed on the surface of the interlayer insulating film 22 including the via contact hole 23 and the trench 24. A copper seed layer 26 is formed on the diffusion barrier layer 25 to serve as a catalyst for the electroless plating process.
상기에서, 하지층(21)은 반도체 기판, 폴리실리콘(poly-Si), 텅스텐(W), 알루미늄(Al), 구리(Cu) 등과 같은 전도성 물질로 형성된 층이거나, 절연 물질로 형성된 층이다. 층간 절연막(22)은 낮은 유전 상수(low k)를 갖는 절연 물질로 형성한다. 비아 콘택홀(23) 및 트렌치(24)는 듀얼 다마신(dual damascene) 방식으로 형성한다.In the above, the base layer 21 is a layer formed of a conductive material such as a semiconductor substrate, polysilicon (poly-Si), tungsten (W), aluminum (Al), copper (Cu), or the like, or a layer formed of an insulating material. The interlayer insulating film 22 is formed of an insulating material having a low dielectric constant (low k). The via contact hole 23 and the trench 24 are formed in a dual damascene method.
클리닝 공정은 하지층(21)이 텅스텐(W)이나 알루미늄(Al)과 같은 금속일 경우 고주파 플라즈마(RP plasma)를 이용하고, 하지층(21)이 구리(Cu)일 경우 리액티브 클리닝(reactive cleaning) 방식을 적용하며, 하지층(21)이 절연 물질일 경우 스퍼터링(sputtering) 방식을 적용하고, 이외에도 NF3클리닝, 습식(wet) 클리닝이 있다. 확산 장벽층(15)은 ionized PVD TiN, CVD TiN, MOCVD TiN, ionized PVD Ta, ionized PVD TaN, CVD Ta, CVD TaN, CVD WN 중 적어도 어느 하나로 형성하며, 100 내지 700Å 두께의 접착층과 100 내지 1000Å 두께의 베리어 메탈층이 적층되어 있다.The cleaning process uses RP plasma when the base layer 21 is a metal such as tungsten (W) or aluminum (Al), and reactive cleaning when the base layer 21 is copper (Cu). The cleaning method is applied, and if the base layer 21 is an insulating material, a sputtering method is applied. In addition, there are NF 3 cleaning and wet cleaning. The diffusion barrier layer 15 is formed of at least one of ionized PVD TiN, CVD TiN, MOCVD TiN, ionized PVD Ta, ionized PVD TaN, CVD Ta, CVD TaN, and CVD WN, and has an adhesive layer having a thickness of 100 to 700 GPa and a thickness of 100 to 1000 GPa. The barrier metal layer of thickness is laminated | stacked.
구리 시드층(26)은 스퍼터링법, 화학기상증착법, 메탈 이온 플라즈마(IonicMetal Plasma; IMP)-물리기상증착법 등으로 100 내지 1000Å의 두께로 증착한다. 구리 시드층(26)은 스텝 커버리지가 우수하여야 한다.The copper seed layer 26 is deposited to a thickness of 100 to 1000 mW by sputtering, chemical vapor deposition, Ionic Metal Plasma (IMP) -physical vapor deposition, or the like. The copper seed layer 26 should have good step coverage.
도 2b를 참조하면, 무전해 도금법을 이용한 구리 증착법으로 비아 콘택홀(23) 및 트렌치(24)를 완전히 매립시키는 구리 매립층(27)을 형성한다.Referring to FIG. 2B, a copper buried layer 27 for completely filling the via contact hole 23 and the trench 24 is formed by a copper deposition method using an electroless plating method.
구리의 매립 작용은 무전해 도금 용액 내에서의 구리 이온의 환원 반응에 의하여 진행된다. 이때, 구리 시드층(26)은 구리 이온 환원 반응의 촉매 작용을 한다. 무전해 구리 도금 용액은 구리 이온을 공급하는 금속염인 황산동과, 전자를 공급하는 환원제인 포르말린과, 용액의 수명 연장을 목적으로 첨가하는 첨가제인 롯셀염 등으로 이루어지며, 도금 온도는 20 내지 70℃, pH는 9.0 내지 13.0 이다. 무전해 구리 도금 공정은 스텝 커버리지 특성과 비아 매립 특성이 우수한 공정이다. 한편, 비아 콘택홀의 크기와 어스펙트 비가 서로 다르거나, 트렌치의 깊이와 폭이 서로 다른 경우에도 무전해 도금에 의해 동시 매립이 가능하다.The buried action of copper proceeds by the reduction reaction of copper ions in the electroless plating solution. At this time, the copper seed layer 26 serves as a catalyst for the copper ion reduction reaction. The electroless copper plating solution consists of copper sulfate, a metal salt for supplying copper ions, formalin, a reducing agent for supplying electrons, and rossel salt, an additive added for the purpose of extending the life of the solution. The plating temperature is 20 to 70 ° C. , pH is 9.0 to 13.0. The electroless copper plating process has excellent step coverage and via filling properties. Meanwhile, even when the size and aspect ratio of the via contact hole are different from each other, or the depth and width of the trench are different from each other, simultaneous filling may be performed by electroless plating.
도 2c를 참조하면, 화학적 기계적 연마(CMP) 공정 및 포스트-클리닝(post-cleaning) 공정을 실시하여 비아 콘택홀(23) 및 트렌치(24) 내에 구리 금속 배선(267)을 형성한다. 이후, 웨이퍼의 표면에 캡핑층(28)을 전면 증착한다.Referring to FIG. 2C, a copper mechanical wiring 267 is formed in the via contact hole 23 and the trench 24 by performing a chemical mechanical polishing (CMP) process and a post-cleaning process. Thereafter, the capping layer 28 is entirely deposited on the surface of the wafer.
상기에서, 캡핑층(28)은 구리 금속 배선(267)으로부터 구리 원자가 이후에 구리 금속 배선(267) 상부쪽에 형성될 층간 절연막으로 확산하는 것을 막는 역할을 하며, 주로 실리콘 나이트라이드(SiN)로 형성한다. 이로써, 듀얼 다마신 공정에 의한 최종적인 구리 금속 배선이 완성된다.In the above, the capping layer 28 serves to prevent diffusion of copper atoms from the copper metal wiring 267 to the interlayer insulating film to be formed later on the copper metal wiring 267, and is mainly formed of silicon nitride (SiN). do. This completes the final copper metal wiring by the dual damascene process.
상술한 바와 같이, 본 발명은 매립 특성이 우수한 무전해 도금법을 이용하여 구리 매립층을 형성하므로써, 구리 매립층의 보이드 및 키홀과 같은 내부 결함을 줄일 수 있어 금속 배선에 대한 신뢰성, 안정성 및 성능을 향상시킬 수 있을뿐만 아니라, 마스크층을 이용한 무전해 도금법으로 비아 콘택홀 및 트렌치에만 선택적으로 구리 매립층을 형성하므로써, 연마 공정의 진행시간과 슬러리(slurry) 등의 소모품의 사용량을 줄일 수 있어 원가 절감 및 생산성을 향상시킬 수 있다.As described above, the present invention can reduce the internal defects such as voids and keyholes of the copper buried layer by using the electroless plating method having excellent buried characteristics, thereby improving the reliability, stability and performance of the metal wiring. In addition, by selectively forming a copper buried layer only in via contact holes and trenches using an electroless plating method using a mask layer, it is possible to reduce the running time of the polishing process and the use of consumables such as slurry, thereby reducing costs and productivity. Can improve.
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| JP4350337B2 (en) * | 2001-04-27 | 2009-10-21 | 富士通マイクロエレクトロニクス株式会社 | Semiconductor device |
| KR20020092002A (en) * | 2001-06-01 | 2002-12-11 | 주식회사 하이닉스반도체 | Method for Forming Cu lines in Semiconductor Device |
| KR100403197B1 (en) * | 2001-06-21 | 2003-10-23 | 주식회사 하이닉스반도체 | Method of forming a metal wiring in a semiconductor device |
| KR100440476B1 (en) * | 2001-12-14 | 2004-07-14 | 아남반도체 주식회사 | Method for fabricating semiconductor device |
| KR100451766B1 (en) * | 2001-12-22 | 2004-10-08 | 주식회사 하이닉스반도체 | Method for forming interconnect structures of semiconductor device |
| KR100421913B1 (en) * | 2001-12-22 | 2004-03-11 | 주식회사 하이닉스반도체 | Method for forming interconnect structures of semiconductor device |
| KR20030056913A (en) * | 2001-12-28 | 2003-07-04 | 주식회사 하이닉스반도체 | A method for forming copper layer of semiconductor device |
| KR100805843B1 (en) * | 2001-12-28 | 2008-02-21 | 에이에스엠지니텍코리아 주식회사 | Method of forming copper interconnection, semiconductor device fabricated by the same and system for forming copper interconnection |
| KR100782790B1 (en) * | 2002-07-30 | 2007-12-05 | 동부일렉트로닉스 주식회사 | Semiconductor device and fabrication method of thereof |
| US8025922B2 (en) | 2005-03-15 | 2011-09-27 | Asm International N.V. | Enhanced deposition of noble metals |
| KR100717286B1 (en) | 2006-04-21 | 2007-05-15 | 삼성전자주식회사 | Methods of forming a phase change material layer and method of forming phase change memory device using the same and phase change memory device formed from using the same |
| US9379011B2 (en) | 2008-12-19 | 2016-06-28 | Asm International N.V. | Methods for depositing nickel films and for making nickel silicide and nickel germanide |
| US8871617B2 (en) | 2011-04-22 | 2014-10-28 | Asm Ip Holding B.V. | Deposition and reduction of mixed metal oxide thin films |
| US9607842B1 (en) | 2015-10-02 | 2017-03-28 | Asm Ip Holding B.V. | Methods of forming metal silicides |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5931041A (en) * | 1982-08-13 | 1984-02-18 | Seiko Epson Corp | Thin film semiconductor device |
| JPH1022285A (en) * | 1996-07-02 | 1998-01-23 | Toshiba Corp | Production of semiconductor device |
| JPH10321561A (en) * | 1997-05-12 | 1998-12-04 | Motorola Inc | Method for manufacturing metallic layer on surface of substrate |
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- 1999-06-29 KR KR1019990025433A patent/KR100332118B1/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5931041A (en) * | 1982-08-13 | 1984-02-18 | Seiko Epson Corp | Thin film semiconductor device |
| JPH1022285A (en) * | 1996-07-02 | 1998-01-23 | Toshiba Corp | Production of semiconductor device |
| JPH10321561A (en) * | 1997-05-12 | 1998-12-04 | Motorola Inc | Method for manufacturing metallic layer on surface of substrate |
Also Published As
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|---|---|
| KR20010004719A (en) | 2001-01-15 |
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