KR100431742B1 - Method for fabricating copper interconnect in semiconductor device - Google Patents
Method for fabricating copper interconnect in semiconductor device Download PDFInfo
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- KR100431742B1 KR100431742B1 KR10-2001-0081272A KR20010081272A KR100431742B1 KR 100431742 B1 KR100431742 B1 KR 100431742B1 KR 20010081272 A KR20010081272 A KR 20010081272A KR 100431742 B1 KR100431742 B1 KR 100431742B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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Abstract
본 발명은 반도체 소자 제조 방법에 관한 것으로 특히, 구리이온의 재증착에 따른 절연막의 절연특성 열화를 방지하며 구리배선간의 비아저항을 감소시키기에 적합한 반도체 소자의 구리배선 형성 방법을 제공하기 위한 것으로, 이를 위해 본 발명은, 제1구리배선 상에 상기 제1구리배선을 노출시키는 오픈부를 갖는 절연막을 형성하는 단계; 상기 오픈부가 형성된 프로파일을 따라 전도성 배리어막을 형성하는 단계; 비활성가스를 이용하여 건식세정 공정을 통해 상기 오픈부 형성에 따른 식각부산물을 제거함과 동시에 상기 오픈부 저면의 상기 전도성배리어막을 제거하여 상기 제1구리배선을 노출시키는 단계; 및 상기 오픈부를 매립하여 상기 제1구리배선과 직접 콘택된 제2구리배선을 형성하는 단계를 포함하는 반도체 소자의 구리배선 형성 방법을 제공한다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to provide a method for forming a copper wiring of a semiconductor device suitable for preventing degradation of insulation characteristics of an insulating film due to redeposition of copper ions and for reducing via resistance between copper wirings. To this end, the present invention comprises the steps of forming an insulating film having an open portion for exposing the first copper wiring on the first copper wiring; Forming a conductive barrier layer along the profile in which the open portion is formed; Exposing the first copper interconnection by removing the etching byproduct resulting from the formation of the open portion through a dry cleaning process using an inert gas and simultaneously removing the conductive barrier film on the bottom surface of the open portion; And filling the open part to form a second copper wiring directly contacted with the first copper wiring.
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로 특히, 다층구조의 구리 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a copper wiring having a multilayer structure.
일반적으로 반도체 소자 제조시 소자와 소자간 또는 배선과 배선간을 전기적으로 연결시키기 위해 금속 배선을 사용하고 있다.In general, in the manufacture of semiconductor devices, metal wires are used to electrically connect devices and devices, or wires and wires.
이러한 금속 배선 재료로는 알루미늄(Al) 또는 텅스텐(W)이 널리 사용되고 있으나, 낮은 융점과 높은 비저항으로 인하여 초고집적 반도체 소자에 더이상 적용이 어렵게 되었다. 반도체 소자의 초고집적화에 따라 비저항은 낮고 일렉트로마이그레이션(electromigration; EM) 및 스트레스마이그레이션(stressmigration; SM) 등의 신뢰성이 우수한 물질의 이용이 필요하게 되었으며, 이에 부합할 수 있는 가장 적합한 재료로 구리가 최근에 관심의 대상이 되고 있다.Aluminum (Al) or tungsten (W) is widely used as the metal wiring material. However, due to low melting point and high resistivity, it is no longer applicable to ultra-high density semiconductor devices. Due to the ultra-high integration of semiconductor devices, it is necessary to use materials having low resistivity and highly reliable materials such as electromigration (EM) and stress migration (SM), and copper is the most suitable material to cope with this. Has become an object of interest.
구리를 금속배선 재료로 이용하는 이유는, 구리의 녹는점이 1080℃로서 비교적 높을 뿐만 아니라(알루미늄: 660℃, 텅스텐: 3400℃), 비저항은 1.7μΩ㎝로서 알루미늄(2.7μΩ㎝), 텅스텐(5.6μΩ㎝)보다 매우 낮기 때문이다.The reason why copper is used as a metal wiring material is not only that the melting point of copper is relatively high as 1080 ° C. (aluminum: 660 ° C., tungsten: 3400 ° C.), but the specific resistance is 1.7 μm cm, aluminum (2.7 μΩ cm) and tungsten (5.6 μΩ). It is because it is much lower than cm).
그러나, 구리 배선은 식각이 어렵고, 부식이 확산되는 문제를 지니고 있어서, 실용화에 상당한 어려움을 지니고 있었다.However, copper wiring has a problem that etching is difficult and corrosion is diffused, and thus it has a considerable difficulty in practical use.
이를 개선하고 실용화하기 위하여 싱글 다마신 공정(Single damascene process) 또는 듀얼 다마신 공정(Dual Damascene process)을 적용하였는데, 특히 듀얼 다마신 공정(Dual Damascence)을 주로 적용하고 있다.The single damascene process or the dual damascene process is applied to improve and put this into practical use. In particular, the dual damascene process is mainly applied.
여기서, 다마신 공정이라 함은 절연막(Dielectric layer)을 사진식각 공정을 통해 식각하여 트렌치(Trench)를 형성하고, 이 트렌치에 텅스텐(W), 알루미늄(Al), 구리(Cu) 등의 도전 물질을 채워 넣고 필요한 배선 이외의 도전 물질은에치백(Etchback)이나 화학적기계적연마(Chemical Mechanical Polishing; CMP) 등의 기술을 이용하여 제거하므로써 처음에 형성한 트렌치 모양으로 배선을 형성하는 기술이다.Here, the damascene process is used to form a trench by etching the dielectric layer through a photolithography process, the conductive material such as tungsten (W), aluminum (Al), copper (Cu), etc. The conductive material other than the necessary wiring is filled in by using a technique such as etching back or chemical mechanical polishing (CMP) to form the wiring in the trench shape first formed.
상기한 다마신 공정은, 특히 듀얼 다마신 공정은 주로 DRAM 등의 비트 라인(bit line) 또는 워드라인(Wordline), 금속배선 형성에 이용되며, 특히 다층 금속배선에서 상층 금속배선과 하층 금속배선을 접속시키기 위한 비아홀을 동시에 형성할 수 있을뿐만 아니라, 금속배선에 의해 발생하는 단차를 제거할 수 있으므로 후속 공정을 용이하게 하는 장점이 있다.In the damascene process, in particular, the dual damascene process is mainly used for forming bit lines, word lines, and metal wirings such as DRAM, and in particular, the upper metal wiring and the lower metal wiring in the multilayer metal wiring. Not only can the via holes for connection be formed at the same time, but also the step caused by the metal wiring can be eliminated, thereby facilitating subsequent processes.
최근에는 전해도금(Electro Plating; EP)을 이용한 구리 배선공정이 실용화 단계에 이르고 있는데, 구리배선 공정은 반응성이온식각(Reactive Ion Etching; RIE) 방식으로 배선을 형성하는 알루미늄배선 공정과 달리 듀얼 다마신 공정을 이용하여 패턴을 형성시키고 배리어메탈을 증착한 후 구리의 전해도금으로 배선을 형성시킨다.Recently, the copper wiring process using electroplating (EP) has been put into practical use, and the copper wiring process is dual damascene unlike an aluminum wiring process in which wiring is formed by using reactive ion etching (RIE). The process is used to form a pattern, deposit a barrier metal, and then form a wire by electroplating copper.
이 때, 구리 전해도금은 배리어메탈상에서 직접 이루어지는 것이 불가능하기 때문에 시드층(Seed layer)으로서 구리를 얇게 증착한 후 전해도금을 수행해야 한다. 대표적인 방법으로는 물리기상증착(Physical Vapor Deposition; PVD) 방식의 TaNx, 구리시드층(Cu seed)을 순차적으로 증착한 후 구리를 전해도금한다.At this time, since copper electroplating cannot be directly performed on the barrier metal, electroplating should be performed after thinly depositing copper as a seed layer. Typical methods include physical vapor deposition (PVD) -based TaN x , a copper seed layer (Cu seed) sequentially deposited and then electroplated copper.
그러나, 0.13㎛ 이하의 기술에서는 물리기상증착방식으로 배리어메탈을 증착하는 것이 더이상 불가능하고, 이를 해결하기 위해 단차피복성이 우수한 화학기상증착(Chemical Vapor Deposition; CVD) 방식을 적용하고 있다. 또한, 구리 전해도금을 위한 물리기상증착(PVD) 방식의 구리 시드층의 증착도 미세한 크기의 패턴에는 더이상 적용할 수 없는 문제점이 있다.However, in the technique of 0.13 μm or less, it is no longer possible to deposit the barrier metal by physical vapor deposition, and in order to solve this problem, chemical vapor deposition (CVD), which has excellent step coverage, is applied. In addition, the deposition of the copper seed layer of the physical vapor deposition (PVD) method for copper electroplating has a problem that can not be applied to the pattern of the fine size anymore.
이와 같은 화학기상증착(CVD) 방식의 배리어메탈로는 TiN, WN, TaN 등이 적용되고 있으나, 특히 TiN은 통상의 알루미늄배선 공정에 사용되고 있는 것이므로 가장 이용 가능성이 높으며, TiN막 위에서 우수한 막질의 구리 전해도금막을 얻을 수 있다는 것이 보고된 바 있다.[Yuri, Lantasov, Roger palmans, and Karen maex, "Direct copper electroplating", Advanced Metallization Conference in 2000, San Diego, CA, abstract No.53]As such a chemical vapor deposition (CVD) barrier metal, TiN, WN, TaN, etc. have been applied, but in particular, since TiN is used in a general aluminum wiring process, it is most likely to be used, and copper having excellent film quality on the TiN film. It has been reported that electroplated films can be obtained. [Yuri, Lantasov, Roger palmans, and Karen maex, "Direct copper electroplating", Advanced Metallization Conference in 2000, San Diego, CA, abstract No. 53]
1a 내지 도 1f는 기술에 따른 구리배선의 형성 공정을 도시한 단면도이다.1A to 1F are cross-sectional views showing a process for forming a copper wiring according to the technique.
먼저, 도 1a에 도시된 바와 같이 반도체기판, 소스/드레인, 금속층 등의 하부층(11)상에 제1절연막(12)을 증착한 후, 제1절연막(12)을 선택적으로 식각하여 하부층(11)의 소정 표면을 노출시키는 트렌치(도시하지 않음)를 형성한다.First, as illustrated in FIG. 1A, a first insulating layer 12 is deposited on a lower layer 11 such as a semiconductor substrate, a source / drain, or a metal layer, and then the first insulating layer 12 is selectively etched to form a lower layer 11. To form a trench (not shown) that exposes a predetermined surface.
이어서, 트렌치가 형성된 프로파일을 따라 TiN 또는 WN 등을 이용하여 제1전도성배리어막(13)을 형성한다.Subsequently, the first conductive barrier film 13 is formed using TiN, WN, or the like along the trenched profile.
다음으로, 도 1b에 도시된 바와 같이 제1전도성배리어막(13) 상에 구리의 전해도금을 위한 구리 시드층을 화학기상증착법(CVD) 또는 무전해도금법으로 증착한다. 그리고, 얇게 증착된 구리시드층상에 전해도금법으로 제1구리막(14)을 증착한다.Next, as shown in FIG. 1B, a copper seed layer for electroplating copper is deposited on the first conductive barrier film 13 by chemical vapor deposition (CVD) or electroless plating. Then, the first copper film 14 is deposited on the thinly deposited copper seed layer by electroplating.
다음으로, 도 1c에 도시된 바와 같이 제1절연막(12)의 표면이 노출될 때까지CMP 공정을 실시하여 트렌치에 매립되는 제1구리배선(15)을 형성한다. 이어서, 제1구리배선(15) 및 제1절연막(12) 상에 후속 제2구리배선 형성을 위한 식각 공정에서의 제1절연막(12) 손상을 방지하기 위해 질화막 또는 산화질화막 등을 이용하여 식각방지막(16)을 형성한다.Next, as shown in FIG. 1C, the CMP process is performed until the surface of the first insulating layer 12 is exposed to form the first copper wiring 15 embedded in the trench. Subsequently, etching is performed using a nitride film or an oxynitride film to prevent damage to the first insulating film 12 in an etching process for forming a subsequent second copper wiring on the first copper wiring 15 and the first insulating film 12. The prevention film 16 is formed.
다음으로, 도 1d에 도시된 바와 같이 식각방지막(16) 상에 제2절연막(17)을 형성한 다음, 제2절연막(17)과 식각방지막(16)을 선택적으로 식각하여 제1구리배선(15) 표면을 노출시키는 오픈부(18)를 형성한다.Next, as shown in FIG. 1D, the second insulating layer 17 is formed on the etch stop layer 16, and then the second insulating layer 17 and the etch stop layer 16 are selectively etched to form the first copper wiring ( 15) An open portion 18 is formed that exposes the surface.
다음으로, 도 1e에 도시된 바와 같이 Ar 등의 비활성 가스를 이용한 세정 공정을 통해 전술한 식각 공정에 따라 잔류하는 식각부산물을 제거한다.Next, as shown in FIG. 1E, the etching by-products remaining in the above-described etching process are removed through a cleaning process using an inert gas such as Ar.
한편, 세정시 Ar 이온이 도시된 바와 같이 제1구리배선(15)에 충돌하게 되는 바, 이에 따라 전도성을 갖는 구리이온이 제1구리배선(15)에서 빠져 나와 제2절연막(17)의 측벽에 재증착되며, 이는 제2절연막(17)의 절연특성을 열화시킨다.On the other hand, Ar ions collide with the first copper interconnection 15 as shown in the drawing, and thus, conductive copper ions escape from the first copper interconnection 15 and the sidewalls of the second insulating layer 17. Redeposited, which degrades the insulating properties of the second insulating film 17.
결국, 제2절연막(17)의 절연특성 열화에 따라 후속 제2구리배선과 제1금속배선의 직접 콘택이 불가능하게 되므로, 도 1f에 도시된 바와 같이 오픈부(18)가 형성된 프로파일을 따라 TiN 또는 WN 등을 이용하여 제2전도성배리어막(19)을 형성한 다음, 제2전도성배리어막(19) 상에 구리의 전해도금을 위한 구리 시드층을 화학기상증착법(CVD) 또는 무전해도금법으로 증착한다. 그리고, 얇게 증착된 구리시드층상에 전해도금법으로 제2구리막(도시하지 않음)을 증착한다.As a result, direct contact between the second copper interconnection and the first metal interconnection is impossible due to the deterioration of the insulating property of the second insulation layer 17. As shown in FIG. 1F, the TiN is formed along the profile in which the open portion 18 is formed. Alternatively, the second conductive barrier film 19 is formed using WN or the like, and then a copper seed layer for electroplating copper on the second conductive barrier film 19 is formed by chemical vapor deposition (CVD) or electroless plating. Deposit. Then, a second copper film (not shown) is deposited on the thinly deposited copper seed layer by electroplating.
계속해서, 제2절연막(17)의 표면이 노출될 때까지 CMP 공정을 실시하여 오픈부에 매립된 제2구리배선(20)을 형성한다.Subsequently, the CMP process is performed until the surface of the second insulating film 17 is exposed to form the second copper wiring 20 embedded in the open portion.
한편, 전술한 종래기술에서는 제1구리배선을 노출시킨 후 제2구리배선 증착을 위한 건식세정 중에 제1구리배선의 구리이온이 오픈부 내벽 즉, 제2절연막 측벽에 재증착되고 제2절연막으로 침투하여 절연특성을 열화시키며, 제2구리배선과 절연특성이 열화된 제2절연막과의 직접 접촉을 차단하기 위해 그 접촉 계면에 제2전도성배리어막을 사용해야 됨에 따라 제1 및 제2구리배선 간의 비아저항이 증가되는 문제점이 발생한다.Meanwhile, in the above-described conventional technique, the copper ions of the first copper wiring are redeposited on the inner wall of the open portion, that is, the sidewall of the second insulating film during dry cleaning for the second copper wiring deposition after exposing the first copper wiring. The second conductive barrier film must be used at the contact interface to penetrate and deteriorate the insulating property, and to prevent direct contact between the second copper wiring and the second insulating film whose insulation property is degraded. The problem arises in that the resistance is increased.
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로서, 구리이온의 재증착에 따른 절연막의 절연특성 열화를 방지하며 구리배선간의 비아저항을 감소시키기에 적합한 반도체 소자의 구리배선 형성 방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and a method for forming a copper wiring of a semiconductor device suitable for preventing the deterioration of insulation characteristics of the insulating film due to the redeposition of copper ions and reducing the via resistance between the copper wirings. The purpose is to provide.
도 1a 내지 도 1f는 종래기술에 따른 구리배선 형성 공정을 도시한 단면도,1a to 1f are cross-sectional views showing a copper wiring forming process according to the prior art,
도 2a 내지 도 2g는 본 발명의 일실시예에 따른 구리배선 형성 공정을 도시한 단면도.2A to 2G are cross-sectional views illustrating a copper wiring forming process according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
31 : 하부층 32 : 제1절연막31 lower layer 32 first insulating film
33 : 제1전도성배리어막 35 : 제1구리배선33: first conductive barrier film 35: first copper wiring
36 : 식각방지막 37 : 제2절연막36: etching prevention film 37: second insulating film
39 : 제2전도성배리어막 40 : 제2구리배선39: second conductive barrier film 40: second copper wiring
상기의 목적을 달성하기 위한 본 발명은, 제1구리배선 상에 상기 제1구리배선을 노출시키는 오픈부를 갖는 절연막을 형성하는 단계; 상기 오픈부가 형성된 프로파일을 따라 전도성 배리어막을 형성하는 단계; 비활성가스를 이용하여 건식세정 공정을 통해 상기 오픈부 형성에 따른 식각부산물을 제거함과 동시에 상기 오픈부 저면의 상기 전도성배리어막을 제거하여 상기 제1구리배선을 노출시키는 단계; 및 상기 오픈부를 매립하여 상기 제1구리배선과 직접 콘택된 제2구리배선을 형성하는 단계를 포함하는 반도체 소자의 구리배선 형성 방법을 제공한다.The present invention for achieving the above object, forming an insulating film having an open portion for exposing the first copper wiring on the first copper wiring; Forming a conductive barrier layer along the profile in which the open portion is formed; Exposing the first copper interconnection by removing the etching byproduct resulting from the formation of the open portion through a dry cleaning process using an inert gas and simultaneously removing the conductive barrier film on the bottom surface of the open portion; And filling the open part to form a second copper wiring directly contacted with the first copper wiring.
본 발명은, 하부 구리배선을 노출시킨 후 세정 공정을 바로 실시하지 않고 오픈부를 오픈부를 따라 전도성배리어막을 먼저 증착한 다음, 세정 공정을 통해 전도성배리어막을 세정 및 식각하여 다시 하부 구리배선을 노출시킴으로써, 이과정에서 구리이온이 오픈부 내벽에 재증착되더라도 오픈부 내벽을 이루는 물질이 전도성배리어막이므로 전술한 절연특성 열화를 방지할 수 있을 뿐만아니라, 상부 및 하부 구리배선의 직접 콘택을 이룰 수 있어 비아 저항을 감소시킬 수 있도록 하는 것을 기술적 특징으로 한다.According to the present invention, after exposing the lower copper wiring, the conductive barrier film is first deposited along the open portion without performing the cleaning process immediately, and then the lower copper wiring is exposed again by cleaning and etching the conductive barrier film through the cleaning process. In this process, even if the copper ions are re-deposited on the inner wall of the open part, since the material forming the inner wall of the open part is a conductive barrier film, it is possible not only to prevent the above-described deterioration of the insulation characteristics, but also to make direct contact between the upper and lower copper wires It is a technical feature that the resistance can be reduced.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하는 바, 도 2a 내지 도 2g는 본 발명의 실시예에 따른 구리 배선의 형성 공정을 도시한 단면도이다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. 2A to 2G are cross-sectional views illustrating a process of forming a copper wiring according to an embodiment of the present invention.
먼저, 도 2a에 도시된 바와 같이 반도체기판, 소스/드레인, 금속층 등의 하부층(31)상에 제1절연막(32)을 증착한 후, 제1절연막(32)을 선택적으로 식각하여 하부층(31)의 소정 표면을 노출시키는 트렌치(도시하지 않음)를 형성한다.First, as illustrated in FIG. 2A, a first insulating layer 32 is deposited on a lower layer 31 such as a semiconductor substrate, a source / drain, or a metal layer, and then the first insulating layer 32 is selectively etched to lower the layer 31. To form a trench (not shown) that exposes a predetermined surface.
이어서, 트렌치가 형성된 프로파일을 따라 TiN, WN, TaN, TaW, TiW, CrN 또는 AlN 등을 이용하여 제1전도성배리어막(33)을 형성한다.Subsequently, the first conductive barrier film 33 is formed using TiN, WN, TaN, TaW, TiW, CrW, AlN, or the like along the trenched profile.
다음으로, 도 2b에 도시된 바와 같이 제1전도성배리어막(33) 상에 구리의 전해도금을 위한 구리 시드층을 화학기상증착법(CVD) 또는 무전해도금법으로 증착한다. 그리고, 얇게 증착된 구리시드층 상에 전해도금법으로 제1구리막(34)을 증착한다.Next, as shown in FIG. 2B, a copper seed layer for electroplating copper is deposited on the first conductive barrier film 33 by chemical vapor deposition (CVD) or electroless plating. Then, the first copper film 34 is deposited on the thinly deposited copper seed layer by electroplating.
다음으로, 도 2c에 도시된 바와 같이 제1절연막(32)의 표면이 노출될 때까지 CMP 공정을 실시하여 트렌치에 매립되는 제1구리배선(35)을 형성한다. 이어서, 제1구리배선(35) 및 제1절연막(32) 상에 후속 제2구리배선 형성을 위한 식각 공정에서의 제1절연막(32) 손상을 방지하기 위해 질화막 또는 산화질화막 등을 이용하여 식각방지막(36)을 형성한다.Next, as shown in FIG. 2C, the CMP process is performed until the surface of the first insulating layer 32 is exposed to form the first copper wiring 35 embedded in the trench. Subsequently, etching is performed using a nitride film or an oxynitride film to prevent damage to the first insulating film 32 in an etching process for forming a subsequent second copper wiring on the first copper wiring 35 and the first insulating film 32. The prevention film 36 is formed.
다음으로, 도 2d에 도시된 바와 같이 식각방지막(36) 상에 제2절연막(37)을 형성한 다음, 제2절연막(37)과 식각방지막(36)을 선택적으로 식각하여 제1구리배선(35) 표면을 노출시키는 오픈부(38)를 형성하는 바, 다마신 구조가 형성된다.Next, as shown in FIG. 2D, the second insulating layer 37 is formed on the etch stop layer 36, and then the second insulating layer 37 and the etch stop layer 36 are selectively etched to form the first copper wiring ( 35) Open portions 38 exposing the surface form a damascene structure.
다음으로, 도 2e에 도시된 바와 같이 식각부산물을 제거하기 위한 세정 공정을 실시하지 않고, 오픈부(38)가 형성된 프로파일을 따라 TiN 또는 WN 등을 이용하여 100Å ∼ 2000Å의 두께로 제2전도성배리어막(39)을 형성한다.Next, as shown in FIG. 2E, the second conductive barrier has a thickness of 100 kV to 2000 kV using TiN, WN, or the like along the profile in which the open portion 38 is formed, without performing the cleaning process for removing the etch byproducts. A film 39 is formed.
다음으로, 도 2f에 도시된 바와 같이 He, Ne, Ar 또는 Xe 등의 비활성가스를 이용한 건식 세정을 통해 전술한 식각 공정에 따라 잔류하는 식각부산물을 제거하는 바, CF4를 첨가하여 제1구리배선(35) 상부의 제2전도성배리어막(39)을 제거하여 제1구리배선(35)을 노출시키며 이 때, 제2절연막(37) 상의 제2전도성배리어막(39)도 제거되므로, 후속 CMP 공정에 따른 마진을 향상시킬 수 있다.Next, the bars to remove the etch by-products remaining in accordance with the etching process described above through the dry cleaning using inert gas such as He, Ne, Ar or Xe, as shown in Figure 2f, the addition of CF 4 of copper The second conductive barrier film 39 on the wiring 35 is removed to expose the first copper wiring 35. At this time, the second conductive barrier film 39 on the second insulating film 37 is also removed. Margins from CMP processes can be improved.
여기서, 제1구리배선(35)의 구리이온이 오픈부(38) 내벽에 재증착되더라도 오픈부(38) 내벽을 제2전도성배리어막(39)이 감싸고 있으므로 제2절연막(37)의 절연특성 열화를 방지할 수 있다.Here, even if the copper ions of the first copper wiring 35 are re-deposited on the inner wall of the open portion 38, the second conductive barrier film 39 surrounds the inner wall of the open portion 38, so that the insulating properties of the second insulating layer 37 are maintained. Deterioration can be prevented.
또한, CF4및 비활성 가스를 이용한 세정 후 식각잔류물이 존재할 경우 비활성 가스 만을 사용하여 추가의 세정을 실시할 수도 있다In addition, if an etching residue is present after cleaning with CF 4 and an inert gas, further cleaning may be performed using only the inert gas.
여기서, CF4가스는 1SCCM ∼ 10SCCM의 적은 유량을 사용하는 것이 바람직하다.Here, CF 4 gas is preferably used in a small flow of 1SCCM ~ 10SCCM.
다음으로, 도 2g에 도시된 바와 같이 제2전도성배리어막(39) 상에 구리의 전해도금을 위한 구리 시드층을 화학기상증착법(CVD) 또는 무전해도금법으로 증착한다. 그리고, 얇게 증착된 구리시드층상에 전해도금법으로 제2구리막(도시하지 않음)을 증착한다.Next, as shown in FIG. 2G, a copper seed layer for electroplating copper is deposited on the second conductive barrier film 39 by chemical vapor deposition (CVD) or electroless plating. Then, a second copper film (not shown) is deposited on the thinly deposited copper seed layer by electroplating.
계속해서, 제2절연막(37)의 표면이 노출될 때까지 CMP 공정을 실시하여 오픈부에 매립된 제2구리배선(40)을 형성한다.Subsequently, the CMP process is performed until the surface of the second insulating film 37 is exposed to form the second copper wiring 40 embedded in the open portion.
전술한 제1 및 제2 절연막(32, 37)은 HDP(High Density Plasma) 산화막, APL(Advanced Planalization Layer) 산화막, TEOS(Tetra Ethyl Ortho Silicate)막, PSG(Phospho Silicate Glass)막 또는 BPSG(Boro Phospho Silicate Glass)막 등의 산화막 또는 무기계열의 저유전율(Inorganic Low-k)막 등을 사용하며, 구리막 증착은 전술한 EP법 이외에 PVD 또는 금속유기화학기상증착(Metal Organic ChemicalVapor Deposition; 이하 MOCVD라 함)법 등을 이용할 수 있다.The above-described first and second insulating layers 32 and 37 may be formed of a high density plasma (HDP) oxide film, an advanced planarization layer (APL) oxide film, a tetra ethyl ortho silicate (TEOS) film, a phospho-silicate glass (PSG) film, or a borosilicate glass (BPSG). Oxide films such as Phospho Silicate Glass) or inorganic low-k films are used, and copper film deposition is carried out by PVD or Metal Organic Chemical Vapor Deposition (MOCVD) in addition to the above-described EP method. Method) may be used.
전술한 본 발명은, 상부 구리배선 형성을 위한 식각 공정 후 세정 공정을 바로 실시하지 않고, 전도성 배리어막을 형성한 후 세정 공정을 실시함으로써 세정 공정에 따른 구리이온의 재증착에 따른 절연 특성 열화를 방지할 수 있으며, 이 때 하부 구리배선을 노출시켜 상부 구리배선과 직접 콘택되도록 함으로써 비아저항을 감소시킬 수 있음을 실시예를 통해 알아 보았다.The present invention described above does not immediately perform the cleaning process after the etching process for forming the upper copper wiring, but performs the cleaning process after forming the conductive barrier film to prevent deterioration of insulation characteristics due to redeposition of copper ions according to the cleaning process. In this case, it was found through the embodiment that the via resistance can be reduced by exposing the lower copper wiring to be in direct contact with the upper copper wiring.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명은 절연막의 절연특성 열화를 방지하며 구리배선간의 비아저항을 감소시킬 수 있어, 궁극적으로 반도체 소자의 전기적 특성을 향상시킬 수 있는 탁월한 효과를 기대할 수 있다.As described above, the present invention can prevent the deterioration of the insulating properties of the insulating film and can reduce the via resistance between the copper wirings, and thus, an excellent effect of ultimately improving the electrical characteristics of the semiconductor device can be expected.
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| KR20010076659A (en) * | 2000-01-27 | 2001-08-16 | 박종섭 | Method for fabricating an interconnection layer for semiconductor device |
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2001
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010076659A (en) * | 2000-01-27 | 2001-08-16 | 박종섭 | Method for fabricating an interconnection layer for semiconductor device |
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| KR20030050757A (en) | 2003-06-25 |
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