KR20000003563A - Metallic line manufacturing method of semiconductor device - Google Patents
Metallic line manufacturing method of semiconductor device Download PDFInfo
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- KR20000003563A KR20000003563A KR1019980024823A KR19980024823A KR20000003563A KR 20000003563 A KR20000003563 A KR 20000003563A KR 1019980024823 A KR1019980024823 A KR 1019980024823A KR 19980024823 A KR19980024823 A KR 19980024823A KR 20000003563 A KR20000003563 A KR 20000003563A
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract
Description
본 발명은 반도체 소자의 금속배선 제조방법에 관한 것으로, 특히 선택적인 무전해 구리도금에 의한 구리 플러그와 금속배선을 형성하는 구리 두얼 다마신(dual damascene)공정을 이용함으로서 비아콘택 매립 특성 및 금속배선의 신뢰성을 향상시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for manufacturing metal wiring of a semiconductor device, and particularly, by using a copper dual damascene process for forming a copper plug and a metal wiring by selective electroless copper plating. It relates to a technique for improving the reliability of.
일반적으로 금속 배선으로 널리 사용하는 금속으로는 텅스텐(W), 알루미늄(Al) 및 알루미늄 합금 등이 있다. 그러나, 구리(Cu)는 텅스텐, 알루미늄에 비하여 비저항이 작으며 신뢰성(특히 이.엠(electro migration 이하, EM), 에스.엠(SM)이 우수한 금속 배선 재료이다. 따라서, 반도체 소자의 금속배선을 구리로 대체하려는 연구가 활발히 진행되고 있다.In general, metals widely used for metal wiring include tungsten (W), aluminum (Al), and aluminum alloys. However, copper (Cu) is a metal wiring material having a lower specific resistance and superior reliability (especially EM and SM) compared to tungsten and aluminum. There is an active research into replacing copper with copper.
한편, 구리는 텅스텐, 알루미늄과는 달리 건식 식각(Reactive Ion Etching)에 의한 배선 형성이 어려운 재료이다. 따라서, 구리의 경우에는 건식 식각 공정을 거치지 않으면서 플러그(plug)와 금속배선(line)을 동시에 형성할 수 있는 방법에 관하여 활발히 연구되고 있는바, 이러한 공정을 두얼 다마신(dual damascene)공정이라고 한다.On the other hand, unlike tungsten and aluminum, copper is a material that is difficult to form wiring by dry etching (Reactive Ion Etching). Therefore, in the case of copper, active research has been conducted on a method of simultaneously forming a plug and a metal line without going through a dry etching process. Such a process is called a dual damascene process. do.
그리고, 기존의 구리를 이용한 두얼 다마신공정에 의하면 구리를 웨이퍼에 전면(blanket) 증착한 후에 불필요한 웨이퍼 표면의 구리층을 화확적, 기계적 연마(Chemical Mechanical Polishing 이하, CMP)공정으로 제거함으로써 최종적인 구리 플러그(plug)와 금속배선(line)을 형성한다.In addition, according to the conventional damascene process using copper, copper is deposited on the wafer and then the copper layer on the surface of the wafer is removed by chemical mechanical polishing (CMP). It forms a plug and a metal line.
이 때, 상기 구리를 전면 증착하는 방법으로는 물리적기상증착(Physical Vapor Deposition 이하, PVD) & 리플로우(reflow) 화학적기상증착(Chemical Vapor Deposition이하, CVD), 무전해도금(electroless deposition),전기도금(electrodeposition) 등을 이용할 수 있다.At this time, the method of depositing the entire surface of the copper includes physical vapor deposition (PVD) & reflow chemical vapor deposition (CVD), electroless deposition, electricity Plating or the like can be used.
그런데, 웨이퍼 표면의 비아(via)와 트렌치(trench)에 구리를 전면증착하는 경우 구리 플러그(plug)와 금속배선(line) 형성시 반도체소자의 고집적화에 따른 비아 크기의 감소와 에스퍽트 비의 증가에 따라 금속배선이 단락됨으로서 소자의 생산수율 및 신뢰성을 떨어뜨리는 문제점이 있다.However, when copper is entirely deposited on vias and trenches on the wafer surface, the via size decreases and the spokt ratio increases due to the high integration of semiconductor devices when forming copper plugs and metal lines. As a result, the metal wiring is short-circuited, which lowers the yield and reliability of the device.
이에, 본 발명은 상기한 문제점을 해결하기 위한 것으로 금속배선 상부 표면이 노출되는 콘택홀과 중첩되는 트렌치를 형성하고 상기 콘택홀과 트렌치 내벽에 촉매 금속배선패턴 및 식각장벽층패턴을 형성한 후, 상기 콘택홀 및 트렌치를 메우는 무전해 도금 플러그 및 캡핑층을 형성함으로서 선택적인 무전해 구리도금에 의한 구리 플러그와 금속배선을 형성하는 구리 두얼 다마신(dual damascene) 공정을 이용할 수 있어 비아콘택 매립 특성 및 금속배선의 신뢰성을 향상시키는 반도체 소자의 금속배선 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention is to solve the above problems and to form a trench overlapping the contact hole exposed the upper surface of the metal wiring and to form a catalytic metal wiring pattern and an etching barrier layer pattern in the contact hole and the inner wall of the trench, By forming an electroless plating plug and a capping layer filling the contact hole and the trench, a copper dual damascene process for forming a copper plug and a metal wiring by selective electroless copper plating can be used, so that the via contact buried characteristics And to provide a method for manufacturing a metal wiring of the semiconductor device for improving the reliability of the metal wiring.
도 1a 내지 도 1i 는 본 발명에 따른 반도체 소자의 금속배선 제조공정도1A to 1I are metal wiring manufacturing process diagrams of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>
10 : 절연막 12 : 금속배선10 insulating film 12 metal wiring
13 : 제 1층간절연막 14 : 제 2층간절연막13: 1st interlayer insulation film 14: 2nd interlayer insulation film
16 : 콘택홀 18 : 트랜치16: contact hole 18: trench
20 : 식각장벽층 22 : 촉매 금속배선20: etching barrier layer 22: catalytic metal wiring
24 : 감광막 26 : 무전해 도금 플러그24 photosensitive film 26 electroless plating plug
28 : 캡핑층28: capping layer
상기 목적을 달성하기 위해 본 발명에 따르면,According to the present invention to achieve the above object,
소정의 하부구조물을 구비하는 반도체 기판 상에 형성되어있는 절연막상에 금속배선을 형성하는 공정과,Forming a metal wiring on an insulating film formed on a semiconductor substrate having a predetermined substructure;
상기 구조의 전표면에 층간절연막을 형성하는 공정과,Forming an interlayer insulating film on the entire surface of the structure;
상기 금속배선 상부 표면이 노출되는 콘택홀을 형성하는 공정과,Forming a contact hole exposing the upper surface of the metal wiring;
상기 콘택홀과 중첩되는 넓은 폭의 트렌치를 형성하는 공정과,Forming a wide trench which overlaps the contact hole;
상기 콘택홀과 트랜치의 내벽에 식각장벽층 패턴 및 무전해 도금을 위한 촉매 금속배선 패턴을 순차적으로 형성하는 공정과,Sequentially forming an etch barrier layer pattern and a catalyst metal wiring pattern for electroless plating on the inner walls of the contact hole and the trench;
상기 콘택홀 및 트렌치를 메우는 무전해 도금 플러그를 형성하는 공정과,Forming an electroless plating plug filling the contact hole and the trench;
상기 구조의 전표면에 캡핑층을 형성하는 공정을 포함하는 것을 특징으로 한다.And forming a capping layer on the entire surface of the structure.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 금속배선 제조방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a metal wire manufacturing method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1i 는 본 발명에 따른 반도체 소자의 금속배선 제조공정도이다.1A to 1I are diagrams illustrating a process for manufacturing metallization of a semiconductor device according to the present invention.
먼저, 반도체 기판(도시되지 않음) 상부에 소정의 하부 구조물들, 예컨대 소자분리 산화막과, 모스 전계효과 트랜지스터, 비트선, 캐패시터등을 형성하고, 상기 구조의 전표면에 산화막으로 이루어진 절연막(10)을 형성한 후, 예를들어 Al막 또는 Cu막으로 이루어진 금속배선(12)과 산화막 재질의 제 1층간절연막(13) 및 제 2층간절연막(14)을 순차적으로 형성한다.First, predetermined lower structures such as a device isolation oxide film, a MOS field effect transistor, a bit line, a capacitor, and the like are formed on a semiconductor substrate (not shown), and the insulating film 10 made of an oxide film on the entire surface of the structure. After the formation, the metal wiring 12 made of, for example, an Al film or a Cu film, the first interlayer insulating film 13 and the second interlayer insulating film 14 made of an oxide film are sequentially formed.
다음, 후속공정에서 두얼 마다신공정을 진행하기 위해 상기 제 2층간절연막(14)에서 콘택마스크를 이용하여 콘택으로 예정된 부분의 상기 금속배선(12) 상부 표면이 노출될때 까지 식각하여 콘택홀(16)을 형성한 후, 식각마스크를 이용하여 상기 제 2층간절연막(14)의 일부가 노출될때 까지 식각하여 상기 콘택홀(16)과 층첩되는 넓은 폭의 트렌치(18)을 형성한다. (도 1a 참조).Next, in order to proceed with the new process every subsequent step, the contact hole 16 is etched by using the contact mask in the second interlayer insulating film 14 until the upper surface of the upper portion of the metal wiring 12 exposed as the contact is exposed. After forming the etch mask, the trench 18 is etched using an etching mask until a part of the second interlayer insulating layer 14 is exposed to form a wide trench 18 overlapping the contact hole 16. (See FIG. 1A).
그 다음, 상기 구조의 전표면에 TiN막, Ta막, TaN막으로 이루어진 군에서 하나의 막으로 형성되는 식각장벽층(20)을 CVD법 또는 PVD법으로 형성한다. 이 때, 상기 식각장벽층(20)은 후속 공정에서 플러그의 구리원자가 확산되는 것을 방지할 수 있다. (도 1b 참조).Next, an etch barrier layer 20 formed of one film from the group consisting of a TiN film, a Ta film, and a TaN film is formed on the entire surface of the structure by CVD or PVD. In this case, the etching barrier layer 20 may prevent the copper atoms of the plug from being diffused in a subsequent process. (See FIG. 1B).
다음, 상기 식각장벽층(20) 상부에 후속공정의 무전해 구리 도금층을 위한 촉매 금속배선(22)을 PVD법 또는 무전해 도금법으로 형성한다. 이 때, 상기 촉매 금속배선(22)은 무전해 구리 도금 용액에 존재하는 구리이온의 환원를 촉진시키며, 무전해 구리 도금층의 균일성을 증가시키며, 무전해 구리 도금층의 초기 핵생성 자리 역할을 한다. 따라서, 상기 촉매 금속배선(22)이 존재하는 부위에만 구리가 선택적으로 무전해 도금된다. 상기 촉매 금속배선(22)으로는 금(Au), 은(Ag), 백금(Pt), 필라듐(Pd) 등이 사용되나, 무전해 구리 도금의 경우에는 주로 필라듐(Pd)을 사용한다. 또한, 구리가 촉매 금속배선(22) 상부에 도금된 후에는 구리층 자신이 촉매역할을 하여 무전해 도금이 계속적으로 진행된다. (도 1c 참조).Next, the catalyst metal wiring 22 for the electroless copper plating layer of the subsequent process is formed on the etching barrier layer 20 by PVD or electroless plating. At this time, the catalytic metal wiring 22 promotes reduction of copper ions present in the electroless copper plating solution, increases uniformity of the electroless copper plating layer, and serves as an initial nucleation site of the electroless copper plating layer. Therefore, copper is selectively electroless plated only at the portion where the catalytic metal wiring 22 is present. Gold (Au), silver (Ag), platinum (Pt), piladium (Pd), and the like are used as the catalyst metal wiring 22, but in the case of electroless copper plating, mainly palladium (Pd) is used. . In addition, after copper is plated on the catalyst metal wiring 22, the copper layer itself acts as a catalyst and electroless plating proceeds continuously. (See FIG. 1C).
다음, 상기 콘택홀(16)과 중첩되는 트렌치(18) 내벽에 감광막(24)을 형성한다. (도 1d 참조).Next, a photosensitive film 24 is formed on the inner wall of the trench 18 overlapping the contact hole 16. (See FIG. 1D).
그 다음, 상기 감광막(24)을 전면노광 및 용해 공정을 거쳐 상기 콘택홀(16)와 트렌치(18)내의 감광막(24)을 제외한 나머지 부분을 제거한다. 이 때, 상기 감광막(24) 패턴 형성공정은 상기 콘택홀(16)와 트렌치(18)를 제외한 표면 부위의 상기 촉매 금속배선(22)과 식각장벽층(20)을 제거하기 위함이다. (도 1e 참조).Then, the photoresist layer 24 is subjected to full exposure and melting to remove the remaining portions except for the photoresist layer 24 in the contact hole 16 and the trench 18. At this time, the photosensitive film 24 pattern forming process is to remove the catalyst metal wiring 22 and the etch barrier layer 20 on the surface portion except the contact hole 16 and the trench 18. (See FIG. 1E).
다음, 상기 제 2층간절연막(14) 상부에 존재하는 상기 촉매 금속배선(22)과 식각장벽층(20)을 건식 또는 습식공정으로 제거한다. 이 때. 상기 콘택홀(16)과 중첩되는 트렌치(18) 내벽에 촉매 금속배선(22)패턴 및 식각장벽층(20)패턴을 형성하되 표면 균일성을 향상시키기 위한 상기 촉매 금속배선(22) 패턴의 일부가 식각되게 형성한 후, 상기 감광막(24) 패턴을 제거한다. 여기서, 상기와 같은 공정은 상기 콘택홀(16)와 트렌치(18)에만 구리를 선택적으로 무전해 도금하기 위함이다. 또한, 상기 트렌치(18) 내벽에 존재하는 촉매 금속배선(22)의 윗부분을 일부 제거함으로써 무전해 도금에 의한 구리 플러그와 금속배선의 표면 균일성을 높일 수 있다. (도 1f 및 도 1g 참조).Next, the catalyst metal wiring 22 and the etch barrier layer 20 on the second interlayer insulating layer 14 are removed by a dry or wet process. At this time. A portion of the catalyst metal wiring 22 pattern is formed on the inner wall of the trench 18 overlapping the contact hole 16 to form a catalyst metal wiring 22 pattern and an etching barrier layer 20 pattern. After the etching is formed, the photosensitive film 24 pattern is removed. In this case, the above process is for selectively electroless plating copper only on the contact hole 16 and the trench 18. In addition, the surface uniformity of the copper plug and the metal wiring by the electroless plating may be improved by removing a portion of the upper portion of the catalyst metal wiring 22 existing on the inner wall of the trench 18. (See FIGS. 1F and 1G).
다음, 상기 콘택홀(16) 및 트렌치(18)를 메우는 구리막을 형성하여 무전해 도금 플러그(26)를 형성한다.Next, a copper film filling the contact hole 16 and the trench 18 is formed to form an electroless plating plug 26.
이 때, 무전해 구리 도금층으로 이루어진 Pd 무전해 도금 플러그(24)에서의 구리 이온의 환원 반응은 다음과 같다.At this time, the reduction reaction of copper ions in the Pd electroless plating plug 24 made of the electroless copper plating layer is as follows.
CU2++ 2e →Pd 촉매 → Cu0 CU 2+ + 2e → Pd Catalyst → Cu 0
즉, 상기 무전해 도금플러그(26)는 구리이온과 환원제가 함유된 무전해 구리 도금 용액을 적절한 온도와 pH로 유지할 경우에 환원제로부터 공급된 전자와 촉매 금속배선(22)과의 작용으로 인하여 구리이온이 촉매금속배선(22)의 표면에 자발적으로 환원 석출된다. 상기 무전해 구리도금 용액은 황산동(금속염 : 구리이온의 공급), 포르말린(환원제 : 전자의 공급), 롯셀염 (착화제 : 용액의 수명연장을 목적으로 첨가하는 용액) 등으로 이루어지며, 도금온도는 20∼70℃, pH는 9.0~13.0 이다.That is, the electroless plating plug 26 is formed by the action of the electrons and the catalytic metal wiring 22 supplied from the reducing agent when the electroless copper plating solution containing the copper ions and the reducing agent is maintained at an appropriate temperature and pH. Ions spontaneously reduce and precipitate on the surface of the catalytic metal wiring 22. The electroless copper plating solution is composed of copper sulfate (metal salt: supply of copper ions), formalin (reducing agent: supply of electrons), lotel salt (complexing agent: a solution added for the purpose of extending the life of the solution), plating temperature Is 20-70 degreeC and pH is 9.0-13.0.
여기서, 상기 무전해 구리 도금 공정을 진행함으로써 스텝 커버리지 특성과 비아콘택 매립 특성이 개선된다.Here, the step coverage characteristics and the via contact embedding characteristics are improved by performing the electroless copper plating process.
그리고 상기 콘택홀(16)의 크기와 에스펙트 비가 서로 다르거나, 상기 트렌치(18)의 깊이와 폭이 서로 다른 경우에는 최종적인 구리 플러그와 금속배선의 표면 높낮이가 서로 다를 수 있는데, 이런 경우에는 불필요한 구리 부분을 CMP 공정으로 제거할 수 있다. (도 1h 참조).When the size and aspect ratio of the contact hole 16 are different or the depth and width of the trench 18 are different from each other, the surface heights of the final copper plug and the metal wiring may be different from each other. Unnecessary copper can be removed by the CMP process. (See FIG. 1H).
다음, 상기 구조의 전표면에 SiN막으로 형성된 캡핑층(capping layer, 28)을 형성한다. 여기서 상기 캡핑층(28)은 구리원자가 상기 제 2층간절연막(14)으로 확산하는 것을 막는 역할을 한다. 그리고, 금속배선의 수에 따라 상기와 같은 공정을 반복함으로써 다층의 금속배선을 형성하게 된다.(도 1i 참조)Next, a capping layer 28 formed of a SiN film is formed on the entire surface of the structure. The capping layer 28 prevents copper atoms from diffusing into the second interlayer insulating film 14. Then, the above process is repeated according to the number of metal wires to form a multi-layer metal wire (see FIG. 1I).
상기한 바와같이 본 발명에 따르면, 선택적인 무전해 구리도금 공정으로 구리 플러그와 금속배선을 형성할 수 있는 두얼 다미신공정을 사용함으로써 다음과 같은 잇점이 있다.As described above, according to the present invention, there is the following advantages by using a dual damisin process that can form a copper plug and metal wiring in a selective electroless copper plating process.
첫째, 구리는 텅스텐, 알루미늄에 비하여 비저항이 작으며 신뢰성(특히 EM, SM)이 우수한 금속 재료이므로 반도체 소자의 성능 향상(RC delay time 감소)과 신뢰성 향상에 유리하다.First, copper is a metal material having a lower specific resistance and excellent reliability (especially EM and SM) than tungsten and aluminum, and thus is advantageous for improving performance (reducing RC delay time) and reliability of semiconductor devices.
둘째, 콘택홀과 트렌치에 구리를 선택적으로 무전해 도금함으로써, 기존의 구리 전면 증착 & 구리전면 CMP 공정을 진행하지 않고 최종적인 구리 플러그와 금속배선을 형성할 수 있으며, 기존의 구리 두얼 다마신공정에 비하여 훨씬 단순화된 공정에 의하여 구리 두얼 다마신공정을 완성할 수 있어 생산성을 향상시킬 수 있다.Second, by selectively electroless plating copper in the contact holes and trenches, the final copper plug and metal wiring can be formed without the conventional copper front deposition & copper front CMP process. In comparison, a much simpler process can complete the copper dual damascene process, thereby improving productivity.
셋째, 콘택홀과 트렌치에 구리를 선택적으로 무전해 도금함으로써, 비아 매립 특성을 더욱 높일 수 있어 반도체 소자의 고집적화에 따른 비아 크기의 감소와 어스펙트 비의 증가에도 불구하고 단락 현상없이 금속 배선을 형성시킬 수 있다.Third, by selectively electroless plating copper into contact holes and trenches, via filling characteristics can be further enhanced, thereby forming metal wiring without short-circuit despite the decrease in via size and increase in aspect ratio due to high integration of semiconductor devices. You can.
넷째, 구리 무전해 도금은 20~70℃에서 가능하므로, 구리 플러그와 금속배선의 형성시에 반도체 기판에 열충격을 유발하지 않는다.Fourth, copper electroless plating is possible at 20 to 70 ° C., and thus does not cause thermal shock to the semiconductor substrate during formation of the copper plug and the metal wiring.
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20020092002A (en) * | 2001-06-01 | 2002-12-11 | 주식회사 하이닉스반도체 | Method for Forming Cu lines in Semiconductor Device |
| KR100383759B1 (en) * | 2000-06-15 | 2003-05-14 | 주식회사 하이닉스반도체 | Method of forming a copper metal wiring in a semiconductor drvice |
| KR100404941B1 (en) * | 2000-06-20 | 2003-11-07 | 주식회사 하이닉스반도체 | Method of forming a metal wiring in a semiconductor device |
| KR100407681B1 (en) * | 2000-06-26 | 2003-12-01 | 주식회사 하이닉스반도체 | Method of forming a metal line in a semiconductor device |
| KR100407679B1 (en) * | 2000-06-15 | 2003-12-01 | 주식회사 하이닉스반도체 | Method of forming a copper wiring in a semiconductor device |
| KR20040007098A (en) * | 2002-07-16 | 2004-01-24 | 주식회사 하이닉스반도체 | Semiconductor device for including copper wiring and method for the same |
| KR100449223B1 (en) * | 2000-06-29 | 2004-09-18 | 인터내셔널 비지네스 머신즈 코포레이션 | Method for depositing copper onto a barrier layer |
| KR100528530B1 (en) * | 2000-12-20 | 2005-11-15 | 매그나칩 반도체 유한회사 | Method for forming a metal layer of a semiconductor device |
| KR100720401B1 (en) * | 2001-06-01 | 2007-05-22 | 매그나칩 반도체 유한회사 | Method for Forming Cu lines in Semiconductor Device |
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| KR100476702B1 (en) * | 2000-12-28 | 2005-03-16 | 주식회사 하이닉스반도체 | Method of forming a copper wiring in a semiconductor device |
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1998
- 1998-06-29 KR KR1019980024823A patent/KR100265615B1/en not_active IP Right Cessation
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| KR100383759B1 (en) * | 2000-06-15 | 2003-05-14 | 주식회사 하이닉스반도체 | Method of forming a copper metal wiring in a semiconductor drvice |
| KR100407679B1 (en) * | 2000-06-15 | 2003-12-01 | 주식회사 하이닉스반도체 | Method of forming a copper wiring in a semiconductor device |
| KR100404941B1 (en) * | 2000-06-20 | 2003-11-07 | 주식회사 하이닉스반도체 | Method of forming a metal wiring in a semiconductor device |
| KR100407681B1 (en) * | 2000-06-26 | 2003-12-01 | 주식회사 하이닉스반도체 | Method of forming a metal line in a semiconductor device |
| KR100449223B1 (en) * | 2000-06-29 | 2004-09-18 | 인터내셔널 비지네스 머신즈 코포레이션 | Method for depositing copper onto a barrier layer |
| KR100528530B1 (en) * | 2000-12-20 | 2005-11-15 | 매그나칩 반도체 유한회사 | Method for forming a metal layer of a semiconductor device |
| KR100720400B1 (en) * | 2001-05-30 | 2007-05-22 | 매그나칩 반도체 유한회사 | Method for forming interconnect structures of semiconductor device |
| KR20020092002A (en) * | 2001-06-01 | 2002-12-11 | 주식회사 하이닉스반도체 | Method for Forming Cu lines in Semiconductor Device |
| KR100720401B1 (en) * | 2001-06-01 | 2007-05-22 | 매그나칩 반도체 유한회사 | Method for Forming Cu lines in Semiconductor Device |
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