KR20040007098A - Semiconductor device for including copper wiring and method for the same - Google Patents
Semiconductor device for including copper wiring and method for the same Download PDFInfo
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- KR20040007098A KR20040007098A KR1020020041747A KR20020041747A KR20040007098A KR 20040007098 A KR20040007098 A KR 20040007098A KR 1020020041747 A KR1020020041747 A KR 1020020041747A KR 20020041747 A KR20020041747 A KR 20020041747A KR 20040007098 A KR20040007098 A KR 20040007098A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
Abstract
Description
본 발명은 반도체소자의 구리배선에 관한 것으로 특히, 무전해도금법을 이용한 구리배선의 확산방지막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to copper wiring of semiconductor devices, and more particularly, to a method of forming a diffusion barrier film of copper wiring using an electroless plating method.
구리(Cu)는 알루미늄(Al)에 비해 여러가지 장점이 있다. 첫째, 전기전도도가 탁월하여 저항이 작다. 이는 반송전류를 일정하게 유지하면서 배선의 미세화와 고집적화의 실현이 가능하다는 의미이다. 따라서, 사용하는 금속층이 감소하고 생산비용을 절감할 수 있게 된다. 저저항 역시 고속성능을 구현한다.Copper (Cu) has several advantages over aluminum (Al). First, the electrical conductivity is excellent, so the resistance is small. This means that miniaturization and high integration of wiring can be realized while keeping the carrier current constant. Therefore, the metal layer used can be reduced and the production cost can be reduced. Low resistance also provides high speed performance.
둘째, 구리는 전해도금특성(내전해도금성)이 우수하여 소자의 신뢰도를 높일 수 있다. 셋째, 무엇보다도 구리는 동일하게 설계한 알루니늄 기반 소자에 비해 수율이 높은 것으로 보고되고 있다.Second, copper has excellent electroplating characteristics (electrolytic plating resistance), thereby increasing the reliability of the device. Third, copper has been reported to have higher yield than aluminum-based devices designed in the same way.
한편, 구리는 식각에 어려움이 따르므로 듀얼다마신(Dual damascene)이란 패턴 형성방법을 주로 사용하며, 듀얼다마신의 경우 절연막 내부로 트렌치(Trench)와 홀(Hole)을 식각하는데 이 때, 생긴 자리를 구리로 채우는 방식이다.On the other hand, since copper has difficulty in etching, a dual damascene pattern is mainly used. In the case of dual damascene, the trench and the hole are etched into the insulating layer. This is done by filling the seat with copper.
도 1은 종래기술에 따른 다층구조의 구리배선이 형성된 반도체소자의 단면도이다.1 is a cross-sectional view of a semiconductor device in which a copper wiring of a multilayer structure according to the prior art is formed.
도 1을 참조하면, 소정의 공정이 완료된 기판(10) 상에 식각정지막(11)과 구리배선(13) 및 비아콘택(12)이 형성되어 있으며, 각각의 구리배선(13) 상에는 확산방지막(14)이 형성되어 있으며, 구리배선(13)과 비아콘택(12)은 절연막(15)을 관통하여 상하부로 연결된 구조를 갖는다. 최상층에는 보호막(16)이 형성되어 있다.Referring to FIG. 1, an etch stop layer 11, a copper interconnect 13, and a via contact 12 are formed on a substrate 10 on which a predetermined process is completed, and a diffusion barrier layer is formed on each copper interconnect 13. 14 is formed, and the copper wiring 13 and the via contact 12 have a structure connected to the upper and lower portions through the insulating film 15. The protective film 16 is formed in the uppermost layer.
한편, 전술한 종래의 경우 구리배선(13)을 다마신 구조의 홀에 매립한 후, 화학기계적연마(Chemical Mechanical Polishing; 이하 CMP라 함) 공정을 통해 분리시킨 후, 그 상부를 NH3가스를 이용하여 처리 후, SiN 또는 SiC 등의 구리 확산방지막(14)을 증착하였다.On the other hand, is embedded in the hole of the case of the prior damascene copper wiring 13, the structure after chemical-mechanical polishing; was separated through (Chemical Mechanical Polishing hereinafter referred to as CMP) process, to the upper NH 3 gas After the treatment, a copper diffusion barrier 14 such as SiN or SiC was deposited.
그러나, SiN 또는 SiC 등의 구리 확산방지막(14)은 다음과 같은 문제점이 있다.However, the copper diffusion barrier 14, such as SiN or SiC, has the following problems.
첫째, 유전율이 증가한다. 구리 배선공정은 RC 딜레이(Delay)를 낮추기 위해 종래의 알루미늄 대신 저항이 낮은 구리를 사용할 뿐만아니라 유전율을 낮추기 위하여 저유전율을 갖도록 하는 공정을 적용한다. 그런데, 이러한 확산방지막이 각 층마다 들어감으로써 전체의 유효 유전률 값(Effective k value)이 증가하여 저유전율의 적용에 큰 실효를 거둘 수 없다.First, the permittivity increases. The copper wiring process uses low-resistance copper instead of conventional aluminum to lower the RC delay, and applies a low dielectric constant to lower the dielectric constant. However, as the diffusion barrier layer enters each layer, the overall effective dielectric constant (Effective k value) increases, so that it is not effective for the application of the low dielectric constant.
둘째, EM(Electro-Migration) 특성이 악화된다. SiN/Cu 또는 SiC/Cu 계면에서는 다마신 배선공정에서 항상 신뢰할 수 있는 부분이 아니다. 따라서, 이러한 계면에는 공정중에 벗겨지지(Peeling) 않도록 주의가 필요하며, 이러한 계면은 EM 공극(Void)이 발생할 가능성이 항상 존재한다.Second, EM (Electro-Migration) characteristics deteriorate. The SiN / Cu or SiC / Cu interface is not always a reliable part of the damascene wiring process. Therefore, care must be taken to avoid peeling during the process at such interfaces, and there is always the possibility that EM voids occur.
셋째, 결함(Defect) 증식이 문제점이 있다. 이러한 절연성 캡핑층(Capping layer)인 확산방지막과 구리의 계면에서 결합(Bonding)이 약하여 결함을 양산하는 부분이 되는 등 많은 문제점들이 발생하여 NH3처리 등의 전처리가 필요하며, 이러한 전처리 역시 제어가 쉽지는 않다.Third, there is a problem in defect propagation. There are many problems such as weak bonding at the interface between the diffusion barrier layer and the copper, which is an insulating capping layer, to produce a defect, and thus pretreatment such as NH 3 treatment is required. It's not easy.
상기와 같은 종래 기술의 문제점을 해결하기 위해 제안된 본 발명은, 구리배선 상부에 형성하는 확산방지막에 따른 EM 특성의 열화와 유효 유전율 값의 증가를 방지할 수 있는 구리배선을 포함하는 반도체소자 및 반도체소자의 제조방법을 제공하는데 그 목적이 있다.The present invention proposed to solve the above problems of the prior art, a semiconductor device comprising a copper wiring that can prevent the degradation of EM characteristics and the increase in the effective dielectric constant value according to the diffusion barrier formed on the copper wiring and Its purpose is to provide a method for manufacturing a semiconductor device.
도 1은 종래기술에 따른 다층구조의 구리배선이 형성된 반도체소자의 단면도.1 is a cross-sectional view of a semiconductor device in which a copper wiring of a multilayer structure according to the prior art is formed.
도 2a 내지 도 2d는 본 발명의 일실시예에 따른 구리배선 형성 공정을 도시한 단면도.2A to 2D are cross-sectional views illustrating a copper wiring forming process according to an embodiment of the present invention.
도 3a는 종래기술과 본 발명의 EM 특성을 비교한 단면도.Figure 3a is a cross-sectional view comparing the EM characteristics of the prior art and the present invention.
도 3b는 종래기술과 본 발명의 유효 유전율을 비교한 단면도.Figure 3b is a cross-sectional view comparing the effective dielectric constant of the prior art and the present invention.
도 4는 본 발명에 따른 다층구조의 구리배선이 형성된 반도체소자의 단면도.4 is a cross-sectional view of a semiconductor device having a copper wiring having a multilayer structure according to the present invention;
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
20 : 전도층21, 27 : 절연막20: conductive layer 21, 27: insulating film
23 : 구리배선26 : 확산방지막23 copper wiring 26 diffusion barrier
28 : 식각정지막29 : 보호막28: etching stop film 29: protective film
상기 목적을 달성하기 위하여 본 발명은, 절연막을 관통하여 전도층에 도통되며 그 상부가 평탄화된 구리배선; 및 무전해도금법을 통해 상기 구리배선 상부에만 선택적으로 형성된 금속성 확산방지막을 포함하는 반도체소자를 제공한다.In order to achieve the above object, the present invention is a copper wiring conductive through the insulating layer and the top of the flattened; And it provides a semiconductor device comprising a metal diffusion barrier selectively formed only on the copper wiring through the electroless plating method.
또한, 상기 목적을 달성하기 위하여 본 발명은, 절연막을 관통하여 전도층에 도통되며 그 상부가 평탄화된 구리배선을 형성하는 단계; 상기 구리배선 상부에만 흡착층을 형성하는 단계; 무전해도금법을 통해 상기 구리배선 상부의 상기 흡착층 주변에만 도금막을 형성하는 단계; 및 세정공정을 실시하여 상기 구리배선 상부에만 선택적으로 금속성 확산방지막을 형성하는 단계를 포함하는 반도체소자의 제조방법을 제공한다.In addition, to achieve the above object, the present invention comprises the steps of: penetrating through the insulating film to the conductive layer and forming a planarized copper wiring thereon; Forming an adsorption layer only on the copper wirings; Forming a plating film only around the adsorption layer on the upper part of the copper wiring by an electroless plating method; And forming a metallic diffusion barrier layer on only the copper wiring by performing a cleaning process.
본 발명은, 구리배선 형성을 위한 CMP 공정후, SiN 또는 SiC 등의 구리 확산방지막을 증착하는 공정을 없애고, 선택적인 무전해도금법(Selective electroless plating)에 의해 구리 확산방지막을 형성하는 방법이다. 즉, 선택적인 무전해도금법을 이용하여 구리배선이 노출된 부분에만 금속성 확산방지막을 증착하여 종래의 공정상의 문제점을 해결하고자 한다.The present invention is a method of forming a copper diffusion barrier layer by selective electroless plating after eliminating the process of depositing a copper diffusion barrier layer such as SiN or SiC after the CMP process for forming copper wiring. In other words, by using a selective electroless plating method to solve the conventional process problems by depositing a metal diffusion barrier only the portion of the copper wiring exposed.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부한 도면을 참조하여 설명한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.
도 4는 본 발명에 따른 다층구조의 구리배선이 형성된 반도체소자의 단면도이다.4 is a cross-sectional view of a semiconductor device having a copper wiring having a multilayer structure according to the present invention.
도 4를 참조하면, 소정의 공정이 완료된 기판 구체적으로, 전도층(20) 상에 식각정지막(28)과 구리배선(23)이 형성되어 있으며, 각각의 구리배선(23) 상에만 선택적으로 금속성 확산방지막(26)이 형성되어 있으며, 구리배선(23)은 절연막(21)을 관통하여 상하부로 도통된 구조를 갖는다. 최상층에는 보호막(29)과 절연막(27)이 형성되어 있다.Referring to FIG. 4, an etch stop layer 28 and a copper wiring 23 are formed on the conductive layer 20, specifically, on a substrate on which a predetermined process is completed, and selectively on each copper wiring 23. The metallic diffusion barrier film 26 is formed, and the copper wiring 23 penetrates through the insulating film 21 and has a structure of conducting up and down. On the uppermost layer, a protective film 29 and an insulating film 27 are formed.
여기서, 확산방지막(26)은 Ni, W, NiRe-P, NoMo-P, NiW-P, NiCo-P 또는 CoW-P 등을 사용한다.Here, the diffusion barrier 26 uses Ni, W, NiRe-P, NoMo-P, NiW-P, NiCo-P or CoW-P.
무전해도금법으로 비아 및 트렌치만 매립을 구현하는 선택적 공정을 적용하는 본 발명을 구현하기 위한 본 발명의 핵심은 Pd활성화 흡착제가 절연막(Dielectric) 위에는 흡착되지 않고 구리등의 금속에만 흡착되는 흡착되는 성잘을 이용하여 구리의 확산방지막 역할을 할 수 있는 금속성 막을 무전해도금법을 이용하여 구리배선 상부에만 캡핑을 형성하는 방법으로서, 종래에 적용되는 전처리 및 확산방지막 형성 단계를 없애므로서 결함 제어를 용이하게 하고, EM 특성을 강화시키며, 무엇보다 유효 유전률 값을 큰 폭으로 감소시킬 수 있는 방법이다.The core of the present invention for applying the selective process for implementing only via and trench only by electroplating method is that the Pd-activated adsorbent is adsorbed only on metal such as copper, not on the dielectric. A method of forming a capping only on an upper portion of a copper wiring by an electroless plating method using an electroless plating method, which eliminates pretreatment and diffusion barrier formation steps that are conventionally applied, thereby easily controlling defects. It is possible to greatly reduce the effective dielectric constant value, and above all, to enhance the EM characteristics.
도 2a 내지 도 2d는 본 발명의 일실시예에 따른 구리배선 형성 공정을 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a copper wiring forming process according to an embodiment of the present invention.
도 2a는 반도체소자를 이루기 위한 여러 요소가 형성된 기판 구체적으로, 전도층(20) 상에 형성된 통상의 층간절연을 위해 형성된 절연막(21)을 관통하여 형성된 오픈부를 통해 Ti/TiN 등의 금속배리어막(22)과 구리배선(23)이 하부의 전도층(20)과 도통된 후, CMP 등에 의해 평탄화된 후 세정 공정을 마치고 Pd 또는 Co 등의 활성화 흡착제를 이용하여 흡착층(24)을 구리배선(23) 상부에만 형성 즉, 흡착시킨 상태를 나타낸다.FIG. 2A illustrates a metal barrier film such as Ti / TiN through a substrate formed with various elements for forming a semiconductor device, specifically, an opening formed through an insulating film 21 formed for normal interlayer insulation formed on the conductive layer 20. After the conductive layer 20 and the copper wiring 23 are connected to the lower conductive layer 20, the copper wiring 23 is flattened by CMP or the like, and then the cleaning process is completed. (23) Formation only in the upper part, that is, the state which adsorbed is shown.
여기서, Pd 활성화 흡착제의 경우 스퍼터링(Sputtering) 방식 또는 습식처리(Wet treatment)를 이용하는 바, 습식처리를 이용하는 한 예로 Pd 활성화 흡착제가 도금조 내에 들어 있는 욕(Bath)은 PdCl2를 용해시켜 사용하며, 이 때 Pd2+이온의 농도가 10-4M ∼ 10M이 되도록 하고 활성화 시간은 1초 ∼ 200초 정도가 적당하다.Here, in the case of Pd-activated adsorbents, sputtering or wet treatment is used. As an example of using wet treatment, a bath containing a Pd-activated adsorbent in a plating bath is used by dissolving PdCl 2 . At this time, the concentration of Pd 2+ ions is set to 10 −4 M to 10 M, and the activation time is suitably about 1 second to 200 seconds.
도 2b는 선택적인 무전해도금법을 이용하여 흡착층(24)이 형성된 구리배선(23) 상부에만 도금막(25)이 형성된 상태를 나타낸다.FIG. 2B shows a state in which the plating film 25 is formed only on the copper wiring 23 on which the adsorption layer 24 is formed using a selective electroless plating method.
즉, 무전해도금법을 이용하여 금속성 확산방지막으로 사용될 도금막을 구리배선(23)이 노출된 영역에만 선택적으로 증착한다. 이러한 무전해도금법에서는 흡착층(24)에 선택성이 있기 때문에 흡착층(24)에 도금되는 금속성 이온이 집중되어 증착되게 된다. 다른영역 예컨대, 절연막(21) 상부에서는 전류의 이동이 제한되기 때문에 부전해도금으로 증착하려는 막의 핵형성(Nuclearation) 및 성장(Growth)이 일어나지 않는다. 즉, 활성화 흡착층(24)이 집중되어 있는 부분을 중심으로 막 증착이 가속화되기 때문에 선택적인 도금막(25)의 형성이 가능하게 된다.That is, by using an electroless plating method, a plated film to be used as the metallic diffusion barrier film is selectively deposited only in a region where the copper wiring 23 is exposed. In such an electroless plating method, since the adsorption layer 24 is selective, metallic ions to be plated on the adsorption layer 24 are concentrated and deposited. In other regions, for example, the current is restricted in the upper portion of the insulating layer 21, so that nucleation and growth of the film to be deposited by the electroless plating do not occur. That is, since the deposition of the film is accelerated around the portion where the activated adsorption layer 24 is concentrated, the selective plating film 25 can be formed.
이 때, 무전해도금을 위한 도금액은 증착하려는 막의 원소 물질, HCHO(Formaldehyde)와 같은 환원제(Reducing agent)와 pH조절(pH adjuster)과 용액안정에 따른 몇가지 첨가제(Complexing agent, surfactant)들로 구성된다. 무전해도금시 도금액의 온도는 20℃ ∼ 100℃의 범위를 유지하도록 한다.At this time, the plating solution for electroless plating is composed of elemental material of the film to be deposited, reducing agent such as HCHO (Formaldehyde), pH adjuster and several additives (Complexing agent, surfactant) according to solution stability. do. In electroless plating, the temperature of the plating liquid is maintained in the range of 20 ° C to 100 ° C.
무전해도금법을 이용해 증착된 도금막(25)은 Ni, W, NiRe-P, NoMo-P, NiW-P, NiCo-P 또는 CoW-P 등을 적용할 수 있다.As the plated film 25 deposited using the electroless plating method, Ni, W, NiRe-P, NoMo-P, NiW-P, NiCo-P or CoW-P may be applied.
도 2c는 도금막(25)이 형성된 기판을 세정하여 구리배선(23) 상부에만 선택적으로 형성된 확산방지막(26)을 형성한 상태를 나타낸다.FIG. 2C illustrates a state in which the diffusion barrier layer 26 formed on the upper portion of the copper wiring 23 is selectively formed by cleaning the substrate on which the plating layer 25 is formed.
세정시 산성(Acid)용액을 순수(DI)에 희석시킨 용액을 사용하는 것이 바람직하다.When washing, it is preferable to use a solution in which an acidic solution is diluted with pure water (DI).
따라서, 종래의 CMP 공정 후에 실시하던 NH3등의 처리를 생략할 수 있다.Therefore, it is possible to skip processing such as the NH 3 was carried out after a conventional CMP process.
도 2d는 확산방지막(26)이 형성된 전체구조 상부에 3000Å ∼ 10000Å의 두께로 절연막(27)증착한 상태를 나타낸다.FIG. 2D shows a state in which the insulating film 27 is deposited to have a thickness of 3000 kPa to 10000 kPa over the entire structure on which the diffusion barrier 26 is formed.
여기서, 절연막(27)은 폴리머계열의 막을 스핀-온(Spin-on) 방식으로 도포하거나, 화학기상증착(Chemical Vapor Deposition; 이하 CVD라 함)방식을 이용하여 메팅 또은 에틸을 함유하거나 저밀도 산화막을 이용한다.Herein, the insulating film 27 may be formed by applying a polymer-based film by spin-on, or by using a chemical vapor deposition (CVD) method, which may include a metal oxide or a low density oxide film. I use it.
도 3a는 종래기술과 본 발명의 EM 특성을 비교한 단면도이며, 도 3b는 종래기술과 본 발명의 유효 유전율을 비교한 단면도이다.Figure 3a is a cross-sectional view comparing the EM characteristics of the prior art and the present invention, Figure 3b is a cross-sectional view comparing the effective dielectric constant of the prior art and the present invention.
여기서, 전술한 도 1과 도 2d 내지 도 2d와 동일한 구성요소에 대해서는 설명을 생략한다.Here, the description of the same components as those of FIG. 1 and FIGS. 2D to 2D described above will be omitted.
도 3a를 참조하면, 종래의 경우 구리배선(13)과 SiN 또는 SiC의 계면에서 결함에 의해 도시된 'X'와 같은 공극입 발생하거나 EM 특성이 열화되는 문제점이 발생하나, 본 발명의 경우 구리배선(23)과 금속성 확산방지막(26)의 접착력이 우수하여 계면에서의 결함과 EM 특성이 개선됨을 알 수 있다.Referring to FIG. 3A, in the conventional case, there is a problem that voids such as 'X' are shown due to defects at the interface between the copper wiring 13 and SiN or SiC, or the EM characteristics are deteriorated. It can be seen that the adhesion between the wiring 23 and the metallic diffusion barrier 26 is improved, and defects at the interface and EM characteristics are improved.
도 3b를 참조하면, 종래의 경우 확산방지막(11)으로 유전상수(k)가 "7"인 SiN과 "5"인 SiC를 사용하였지만, 이들은 구리배선(13) 상부 뿐만이아닌 전면에 형성되므로 전체의 유효 유전율 값은 증가하게 되나, 본 발명의 경우 구리배선(23)을 제외한 영역에는 확산방지막(26)이 형성되지 않으므로 유효 유전율의 증가를 방지할 수 있다.Referring to FIG. 3B, in the conventional case, as the diffusion barrier 11, SiN having a dielectric constant k of “7” and SiC of “5” are used, but they are formed on the entire surface of the copper wiring 13 instead of the top. Although the effective dielectric constant value of is increased, in the present invention, since the diffusion barrier layer 26 is not formed in the region except the copper wiring 23, an increase in the effective dielectric constant can be prevented.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명은,The present invention described above,
수 있는 탁월한 효과를 기대할 수 있다.You can expect an excellent effect.
Claims (7)
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990049050A (en) * | 1997-12-11 | 1999-07-05 | 구본준 | Wiring Formation Method of Semiconductor Device |
| KR20000003563A (en) * | 1998-06-29 | 2000-01-15 | 김영환 | Metallic line manufacturing method of semiconductor device |
| KR20010082732A (en) * | 2000-02-18 | 2001-08-30 | 이데이 노부유끼 | Process for fabricating a semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990049050A (en) * | 1997-12-11 | 1999-07-05 | 구본준 | Wiring Formation Method of Semiconductor Device |
| KR20000003563A (en) * | 1998-06-29 | 2000-01-15 | 김영환 | Metallic line manufacturing method of semiconductor device |
| KR20010082732A (en) * | 2000-02-18 | 2001-08-30 | 이데이 노부유끼 | Process for fabricating a semiconductor device |
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