KR20010076493A - An interconnection structure formed by damascene process of semiconductor device - Google Patents

An interconnection structure formed by damascene process of semiconductor device Download PDF

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Publication number
KR20010076493A
KR20010076493A KR1020000003671A KR20000003671A KR20010076493A KR 20010076493 A KR20010076493 A KR 20010076493A KR 1020000003671 A KR1020000003671 A KR 1020000003671A KR 20000003671 A KR20000003671 A KR 20000003671A KR 20010076493 A KR20010076493 A KR 20010076493A
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South Korea
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layer
copper
film
metal layer
barrier
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KR1020000003671A
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Korean (ko)
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장규환
이선정
이현덕
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윤종용
삼성전자 주식회사
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Priority to KR1020000003671A priority Critical patent/KR20010076493A/en
Publication of KR20010076493A publication Critical patent/KR20010076493A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper

Abstract

PURPOSE: A metal line structure of a semiconductor device formed with a damascene process is provided to improve an adhesion between a metal line layer and a barrier layer and to improve the characteristics of a metal line, by forming a multi-layered metal line layer. CONSTITUTION: After forming an interlayer insulation film(24) on a semiconductor substrate(22), a contact hole revealing the semiconductor substrate is formed by etching the interlayer insulation film. And a plug(26) connected with the substrate is formed by depositing and etching back a conductive material like a tungsten. Then, a trench is formed by etching an interlayer insulation film(28). After forming a barrier metal layer(30) to prevent the diffusion of a copper line layer, a seed layer(32) is formed to form a copper layer for a metal line by depositing a copper film. A copper layer(34) is formed on the seed layer using an electroplating method. Then, the copper layer is formed only in the trench by polishing the copper layer and the seed layer and the barrier metal layer using a CMP process. And a thin palladium film(36) is formed on an upper part of the copper layer. After forming a barrier layer(38) to prevent a reaction with the insulation film on the semiconductor substrate where the palladium film is formed, an insulation film for insulation with another conductive layer is formed on the barrier layer.

Description

다마신 공정으로 형성된 반도체 소자의 배선구조{An interconnection structure formed by damascene process of semiconductor device}An interconnection structure formed by damascene process of semiconductor device

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 다마신 공정을 이용하여 형성된 신뢰성있는 금속 배선구조에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a reliable metal wiring structure formed using a damascene process.

반도체 장치의 배선구조가 다층화 됨에 따라 콘택홀의 어스펙트 비(aspect ratio)가 증가하여, 비평탄화, 불량한 단차 도포성, 금속 단락, 낮은 수율 및 신뢰성의 열화 등과 같은 문제점들이 발생하게 된다. 이러한 문제점들을 해결하기 위한 새로운 배선기술로서, 후속 평탄화 공정이 용이하고 경제성 면에서 유리한 다마신(Damascene) 기술이 사용되고 있다. 다마신 공정에 의하면, 평탄한 절연막을 식각하여 비아(via) 패턴을 형성한 후, 그 결과물을 금속으로 매립하고, 절연막 상의 과도한 금속층을 CMP 방법으로 제거한다.As the wiring structure of the semiconductor device is multilayered, the aspect ratio of the contact hole increases, resulting in problems such as unevenness, poor step coatability, metal short circuit, low yield, and deterioration of reliability. As a new wiring technology to solve these problems, a damascene technique is used, which is easy in subsequent planarization processes and advantageous in economics. According to the damascene process, a flat insulating film is etched to form a via pattern, and the resultant is buried in metal, and the excess metal layer on the insulating film is removed by the CMP method.

특히, 차세대 고속 CPU나 에스램(SRAM) 등의 배선기술에는 구리(copper)를 이용하는 공정을 도입하고 있다. 구리(copper)를 이용한 배선은 기존의 알루미늄 배선에 비해 저항이 낮고, 일렉트로 마이그레이션(electromigration) 내성이 우수한 것으로 알려져 있다.In particular, wiring technology such as next-generation high-speed CPUs and SRAMs employs copper. It is known that wiring using copper has a lower resistance and better electromigration resistance than conventional aluminum wiring.

도 1a 내지 도 1d는 종래의 단일 다마신 공정을 이용한 구리배선층 형성방법을 설명하기 위한 단면도들이다.1A to 1D are cross-sectional views illustrating a method of forming a copper wiring layer using a conventional single damascene process.

도 1a를 참조하면, 반도체기판(2) 상에 층간절연막(4)을 형성한 후, 이 층간절연막(4)을 식각하여 상기 반도체기판을 노출시키는 콘택홀을 형성한다. 여기에 예를 들어 텅스텐과 같은 도전물질을 증착한 다음 에치백하여 플러그(6)를 형성한다. 다음, 결과물 상에 층간절연막(8)을 형성한 다음 소정의 사진식각 공정으로 상기 층간절연막을 식각하여 배선용 트렌치를 형성한다.Referring to FIG. 1A, after forming the interlayer insulating film 4 on the semiconductor substrate 2, the interlayer insulating film 4 is etched to form a contact hole exposing the semiconductor substrate. Here, for example, a conductive material such as tungsten is deposited and then etched back to form the plug 6. Next, an interlayer insulating film 8 is formed on the resultant, and the interlayer insulating film is etched by a predetermined photolithography process to form a wiring trench.

도 1b를 참조하면, 배선용 트렌치가 형성된 결과물 상에, 구리 배선층의 확산을 방지하기 위한 장벽 금속층(10)을 형성한 다음, 구리 시드층(12)을 형성한다.다음, 전기도금 방법을 이용하여 상기 구리 시드층(12) 위에 상기 배선용 트렌치가 채워지도록 구리층(14)을 형성한다.Referring to FIG. 1B, a barrier metal layer 10 for preventing diffusion of the copper wiring layer is formed on the resulting wiring trench, and then a copper seed layer 12 is formed. Next, the electroplating method is used. A copper layer 14 is formed on the copper seed layer 12 to fill the wiring trench.

도 1c를 참조하면, 화학적 기계적 연마(CMP) 공정을 이용하여 구리층(14), 구리 시드층(12) 및 장벽 금속층(10)을 연마하여 트렌치 내부에만 구리층(14)이 형성되도록 한다. 다음에, 상기 구리층(14)과 후속 절연막의 반응을 방지하기 위하여 결과물 상에 질화막을 증착하여 장벽층(16)을 형성한 다음, 이 장벽층(16) 위에 다른 도전층과의 절연을 위하여 절연막(18)을 형성한다.Referring to FIG. 1C, the copper layer 14, the copper seed layer 12, and the barrier metal layer 10 are polished using a chemical mechanical polishing (CMP) process to form the copper layer 14 only in the trench. Next, to prevent the reaction between the copper layer 14 and the subsequent insulating film, a nitride film is deposited on the resultant to form a barrier layer 16, and then insulated from other conductive layers on the barrier layer 16. The insulating film 18 is formed.

상기한 종래의 다마신 공정을 이용한 구리 배선층 형성방법에 있어서, 구리층(14)과 이후 증착되는 질화막 장벽층(16) 간의 계면문제가 심각하다. 즉, 구리층/질화막 사이의 계면 접착성(adhesion)이 불량하고, 구리/질화막 계면이 불안정하여 구리의 확산이 일어나기 쉬워 일렉트로 마이그레이션 특성도 불량하여 소자의 신뢰성에 문제를 일으키기 쉽다는 결점이 있다.In the method for forming a copper wiring layer using the conventional damascene process described above, the interface problem between the copper layer 14 and the nitride film barrier layer 16 deposited thereafter is serious. That is, there is a drawback that the interface adhesion between the copper layer / nitride film is poor, the copper / nitride film interface is unstable, so that copper is easily diffused, and the electromigration property is also poor, which causes problems in device reliability.

따라서, 본 발명이 이루고자 하는 기술적 과제는, 계면 접착특성이 우수한 금속을 배선층 위에 형성하여 다층 구조의 배선층을 형성함으로써, 배선층/장벽층 계면의 문제점을 해결하고, 배선층의 특성을 향상시킬 수 있는 반도체 소자의 배선구조를 제공하는 것이다.Accordingly, a technical problem to be achieved by the present invention is to form a multilayered wiring layer by forming a metal having excellent interfacial adhesion properties on the wiring layer, thereby solving the problem of the wiring layer / barrier layer interface and improving the characteristics of the wiring layer. It is to provide a wiring structure of the device.

도 1a 내지 도 1d는 종래의 단일 다마신 공정을 이용한 구리배선층 형성방법을 설명하기 위한 단면도들이다.1A to 1D are cross-sectional views illustrating a method of forming a copper wiring layer using a conventional single damascene process.

도 2a 내지 도 2c는 본 발명의 일 실시예에 따라 다마신 공정을 이용하여 반도체 소자의 배선층을 형성하는 방법을 설명하기 위한 단면도들이다.2A to 2C are cross-sectional views illustrating a method of forming a wiring layer of a semiconductor device using a damascene process according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

2, 22.....반도체기판 4, 24.....층간절연막2, 22 ... semiconductor board 4, 24 ... interlayer insulating film

6, 26.....플러그(plug) 8, 28.....층간절연막6, 26 ... plug 8, 28 ... interlayer insulation film

10, 30....장벽 금속층 12, 32....시드층10, 30 .... barrier metal layer 12, 32 .... seed layer

14, 34....구리 배선층 16, 38....장벽층14, 34 ... copper wiring layer 16, 38 ... barrier layer

18........절연막 36, 38....배선용 금속층18 ....... Insulation 36, 38..Metal layer for wiring

상기 과제를 이루기 위하여 본 발명에 의한 반도체 소자의 배선구조는, 반도체기판 상에 형성되며 배선모양의 트렌치가 형성된 절연막과, 트렌치의 일부를 채우는 제1 금속층과, 제1 금속층 위에 형성된 제2 금속층, 및 제2 금속층이 형성된 결과물을 덮는 장벽층을 포함한다.In order to achieve the above object, a wiring structure of a semiconductor device according to the present invention includes an insulating film formed on a semiconductor substrate and having a wiring-shaped trench, a first metal layer filling a portion of the trench, a second metal layer formed on the first metal layer, And a barrier layer covering the resultant on which the second metal layer is formed.

본 발명에 있어서, 상기 제1 금속층은 구리(Cu)로 형성하고, 배선용 제2 금속층은 팔라듐, 팔라듐/백금 적층막, 팔라듐/코발트 적층막 또는 팔라듐/니켈 적층막 중의 어느 하나로 형성이루어진다. 그리고, 상기 제1 금속층 하부에, 상기 제1 금속층을 구성하는 물질의 확산을 방지하기 위한 장벽 금속층을 더 구비할 수 있다.In the present invention, the first metal layer is formed of copper (Cu), and the wiring second metal layer is formed of any one of palladium, palladium / platinum laminated film, palladium / cobalt laminated film, or palladium / nickel laminated film. Further, a barrier metal layer may be further provided below the first metal layer to prevent diffusion of a material constituting the first metal layer.

이하, 첨부된 도면을 참조하여 본 발명을 더욱 상세히 설명하기로 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

도 2a 내지 도 2c는 본 발명에 일 실시예에 의한 배선구조를 다마신 공정을 이용하여 형성하는 방법을 설명하기 위한 단면도들이다.2A to 2C are cross-sectional views illustrating a method of forming a wiring structure according to an embodiment of the present invention using a damascene process.

도 2a를 참조하면, 반도체기판(22) 상에 층간절연막(24)을 형성한 후, 이 층간절연막(24)을 식각하여 상기 반도체기판을 노출시키는 콘택홀을 형성한다. 여기에, 예를 들어 텅스텐(W)과 같은 도전물질을 증착한 다음 에치백하여 상기 반도체기판과 접속된 플러그(26)를 형성한다. 다음, 결과물 상에 층간절연막(28)을 형성한 다음 소정의 사진식각 공정으로 상기 층간절연막(28)을 식각하여 배선용 트렌치를 형성한다.Referring to FIG. 2A, after forming the interlayer insulating film 24 on the semiconductor substrate 22, the interlayer insulating film 24 is etched to form a contact hole for exposing the semiconductor substrate. Here, for example, a conductive material such as tungsten (W) is deposited and then etched back to form a plug 26 connected to the semiconductor substrate. Next, an interlayer insulating film 28 is formed on the resultant, and then the interlayer insulating film 28 is etched by a predetermined photolithography process to form a wiring trench.

이어서, 배선용 트렌치가 형성된 결과물 상에, 구리 배선층의 확산을 방지하기 위한 장벽 금속층(30)을 형성한 다음, 구리막을 증착하여 배선용 구리층을 형성하기 위한 시드층(32)을 형성한다.Subsequently, a barrier metal layer 30 for preventing diffusion of the copper wiring layer is formed on the resulting wiring trench, and then a copper film is deposited to form a seed layer 32 for forming the wiring copper layer.

도 2b를 참조하면, 전기도금 방법을 이용하여 상기 시드층(22) 위에 상기 배선용 트렌치가 채워지도록 충분한 두께의 구리층(34)을 형성한다. 다음에, 화학적 기계적 연마(CMP) 공정을 이용하여 상기 구리층(34), 시드층(32) 및 장벽 금속층(30)을 연마하여 상기 배선용 트렌치의 내부에만 구리층(34)이 형성되도록 한다.Referring to FIG. 2B, a copper layer 34 having a sufficient thickness is formed on the seed layer 22 by using an electroplating method to fill the wiring trench. Next, the copper layer 34, the seed layer 32, and the barrier metal layer 30 are polished using a chemical mechanical polishing (CMP) process so that the copper layer 34 is formed only inside the wiring trench.

도 2c를 참조하면, 상기 반도체기판을 염화팔라듐(PdCl2) 용액에 30초 정도 담그면, 용액의 환원성에 의해 반도체기판 표면의 구리중 일부가 산화되어 구리 이온으로 녹아 나오고, 대신 용액중의 팔라듐(Pd)이 환원되어 구리가 있던 자리에 증착되어, 도시된 바와 같이 배선 구리층(34)의 상부에 얇은 팔라듐막(36)이 형성된다. 이 팔라듐막(36)은 전도성이 좋기 때문에 그 자체로 배선층으로 사용할 수 있을 뿐만 아니라, 다른 금속을 무전해 도금할 수 있는 촉매로 사용할 수 있다.Referring to FIG. 2C, when the semiconductor substrate is immersed in a palladium chloride (PdCl 2 ) solution for about 30 seconds, some of the copper on the surface of the semiconductor substrate is oxidized and melted into copper ions due to the reducibility of the solution, and instead palladium in the solution ( Pd) is reduced and deposited in the place where copper was, and a thin palladium film 36 is formed on the wiring copper layer 34 as shown. Since the palladium film 36 has good conductivity, it can be used not only as a wiring layer per se, but also as a catalyst capable of electroless plating other metals.

다음, 팔라듐막이 형성된 반도체기판 상에 절연막과의 반응을 방지하기 위한 장벽층(38)을 형성한 다음, 이 장벽층(38) 위에 다른 도전층과의 절연을 위하여 절연막(도시되지 않음)을 형성한다.Next, a barrier layer 38 for preventing a reaction with the insulating film is formed on the semiconductor substrate on which the palladium film is formed, and then an insulating film (not shown) is formed on the barrier layer 38 to insulate with another conductive layer. do.

도 3은 본 발명의 다른 실시예에 의한 반도체 소자의 배선층 형성방법을 설명하기 위한 것으로, 도 2c의 공정에서 형성된 팔라듐막(36) 위에, 팔라듐막(36)을 촉매로 이용하여 무전해 도금방법으로 금속막(37)을 형성한 예를 나타낸다. 상기 금속막(37)의 재료로는 백금(Pt), 코발트(Co) 또는 니켈(Ni)을 사용할 수 있으며, 이로써 구리/팔라듐/백금(코발트 또는 니켈) 구조의 배선층이 형성된다.FIG. 3 illustrates a method for forming a wiring layer of a semiconductor device according to another embodiment of the present invention. An electroless plating method using a palladium film 36 as a catalyst on a palladium film 36 formed in the process of FIG. 2C. An example in which the metal film 37 is formed is shown. Platinum (Pt), cobalt (Co), or nickel (Ni) may be used as a material of the metal film 37, thereby forming a wiring layer having a copper / palladium / platinum (cobalt or nickel) structure.

이상 본 발명을 상세히 설명하였으나 본 발명은 상술한 실시예에 한정되지 않고, 본 발명의 기술적 사상과 범주내에서 당업자에 의해 여러 가지 변형이 가능하다.Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications may be made by those skilled in the art within the spirit and scope of the present invention.

상술한 본 발명에 의한 반도체 소자의 배선구조에 따르면, 종래의 구리 단일층 대신에 구리/팔라듐, 구리/팔라듐/백금(또는 니켈) 구조의 다층 배선구조로서, 구리/장벽층 계면 접착성을 향상시키고, 구리 원자의 확산이나 일렉트로 마이그레이션도 문제를 해소할 수 있다.According to the wiring structure of the semiconductor device according to the present invention described above, a multilayer wiring structure of copper / palladium, copper / palladium / platinum (or nickel) structure, instead of the conventional copper single layer, improves copper / barrier layer interface adhesion. In addition, diffusion and electromigration of copper atoms can also solve the problem.

Claims (3)

반도체기판 상에 형성되며 배선모양의 트렌치가 형성된 절연막;An insulating film formed on the semiconductor substrate and having a trench formed therein; 상기 트렌치의 일부를 채우는 제1 금속층;A first metal layer filling a portion of the trench; 상기 제1 금속층 위에 형성된 제2 금속층; 및A second metal layer formed on the first metal layer; And 상기 제2 금속층이 형성된 결과물을 덮는 장벽층을 포함하는 것을 특징으로 하는 반도체 소자의 배선구조.And a barrier layer covering a resultant material on which the second metal layer is formed. 제1항에 있어서, 상기 제1 금속층은 구리(Cu)로 이루어지고,The method of claim 1, wherein the first metal layer is made of copper (Cu), 상기 제2 금속층은 팔라듐, 팔라듐/백금의 적층막, 팔라듐/코발트의 적층막 또는 팔라듐/니켈의 적층막 중의 어느 하나로 이루어진 것을 특징으로 하는 반도체 소자의 배선구조.And the second metal layer is made of any one of palladium, a palladium / platinum lamination film, a palladium / cobalt lamination film, and a palladium / nickel lamination film. 제1항에 있어서, 상기 제1 금속층 하부에,The method of claim 1, wherein the lower portion of the first metal layer, 상기 제1 금속층을 구성하는 물질의 확산을 방지하기 위한 장벽 금속층을 더 구비하는 것을 특징으로 하는 반도체 소자의 배선구조.And a barrier metal layer for preventing diffusion of a material constituting the first metal layer.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020034373A (en) * 2000-11-01 2002-05-09 박종섭 Method for forming metal wire of semiconductor device
KR100781855B1 (en) * 2006-04-21 2007-12-03 주식회사 하이닉스반도체 Circuit for pumping voltage of RFID
KR100859951B1 (en) * 2006-12-20 2008-09-23 동부일렉트로닉스 주식회사 Metal line of semiconductor device and method for fabricating the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020034373A (en) * 2000-11-01 2002-05-09 박종섭 Method for forming metal wire of semiconductor device
KR100781855B1 (en) * 2006-04-21 2007-12-03 주식회사 하이닉스반도체 Circuit for pumping voltage of RFID
KR100859951B1 (en) * 2006-12-20 2008-09-23 동부일렉트로닉스 주식회사 Metal line of semiconductor device and method for fabricating the same

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