KR100283110B1 - Metal wiring formation method of semiconductor device - Google Patents
Metal wiring formation method of semiconductor device Download PDFInfo
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- KR100283110B1 KR100283110B1 KR1019980059360A KR19980059360A KR100283110B1 KR 100283110 B1 KR100283110 B1 KR 100283110B1 KR 1019980059360 A KR1019980059360 A KR 1019980059360A KR 19980059360 A KR19980059360 A KR 19980059360A KR 100283110 B1 KR100283110 B1 KR 100283110B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
Abstract
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 비아 콘택홀 및 트렌치를 갖는 듀얼 다마신(dual damascene) 구조를 형성한 후, 듀얼 다마신 패턴 상에 확산 방지막을 얇게 형성하고, 화학기상증착법으로 확산 방지막상에 구리를 얇게 증착하여 비아 콘택 부분을 매립시키고, 물리기상증착법으로 1차 증착된 구리층 상에 구리를 증착하여 트렌치를 완전히 매립시켜 금속 배선용 구리층을 형성하는 기술이다. 이와 같이 구리층을 2단계 공정으로 증착시키므로써, 우수한 단차 피복성 및 매립 특성으로 구리 금속 배선의 전기적 특성이 향상되어 속도가 개선되며, 소자의 집적도가 증가하여 콘택의 단차가 커지더라도 공정마진이 높아 불량을 감소시킬 수 있을 뿐만 아니라, 구리 금속 배선의 신뢰성, 안정성 및 성능을 향상시킬 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, and after forming a dual damascene structure having a via contact hole and a trench, a thin film of a diffusion barrier is formed on the dual damascene pattern, and a chemical vapor deposition method. In this way, a thin layer of copper is deposited on the diffusion barrier to fill the via contact portion, and copper is deposited on the first copper layer deposited by physical vapor deposition to completely fill the trench to form a copper layer for metal wiring. As a result of the deposition of the copper layer in a two-step process, the electrical resistance of the copper metal wiring is improved due to the excellent step coverage and embedding characteristics, and the speed is improved. This can not only reduce defects, but also improve the reliability, stability and performance of copper metal wiring.
Description
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 배선 재료로 구리를 이용하는 듀얼 다마신(dual damascene) 구조에서, 2 단계 공정(step process)으로 구리층을 매립하므로써, 우수한 단차 피복성 및 매립 특성으로 구리 금속 배선의 전기적 특성이 향상되어 속도가 개선되며, 소자의 집적도가 증가하여 콘택의 단차가 커지더라도 공정마진이 높아 불량을 감소시킬 수 있을 뿐만 아니라, 구리 금속 배선의 신뢰성, 안정성 및 성능을 향상시킬 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and in particular, in a dual damascene structure using copper as wiring material, by filling a copper layer in a two step process, excellent step coverage and The buried characteristic improves the electrical characteristics of copper metal wiring to improve speed, and increases the integration level of the device, so that the process margin is high even if the step height of the contact is increased. A metal wiring formation method of a semiconductor element which can improve performance.
일반적으로, 반도체 소자 제조시 소자와 소자간 또는 배선과 배선간을 전기적으로 연결시키기 위해 금속 배선을 사용하고 있다. 금속 배선 재료로 알루미늄(Al) 또는 텅스텐(W)이 널리 사용되고 있으나, 낮은 융점과 높은 비저항으로 인하여 초고집적 반도체 소자에 더 이상 적용이 어렵게 되었다. 따라서, 차세대 반도체 소자의 초고집적화 및 고성능화를 실현하기 위해, 금속 배선의 대체 재료에 대한 개발 및 미세 선폭을 갖는 금속 배선의 형성에 대한 필요성이 대두되고 있는 실정이다. 대체 재료로 전도성이 우수한 물질인 구리(Cu), 금(Au), 은(Ag), 코발트(Co), 크롬(Cr), 니켈(Ni) 등이 있다. 이러한 물질들 중 비저항이 작고, 전자 이동(electromigration; EM)과 스트레스 이동(stress migration; SM) 등의 신뢰성이 우수하며, 생산원가가 저렴한 구리 및 구리 합금이 널리 적용되고 있는 추세이다.In general, in the manufacture of semiconductor devices, metal wires are used to electrically connect between devices and devices or between wires and wires. Although aluminum (Al) or tungsten (W) is widely used as a metal wiring material, its low melting point and high resistivity make it difficult to apply to ultra-high density semiconductor devices. Therefore, in order to realize ultra-high integration and high performance of next-generation semiconductor devices, there is a need for development of alternative materials for metal wiring and formation of metal wirings having a fine line width. Alternative materials include copper (Cu), gold (Au), silver (Ag), cobalt (Co), chromium (Cr), nickel (Ni), and the like. Among these materials, copper and copper alloys having low specific resistance, excellent reliability such as electromigration (EM) and stress migration (SM), and low production cost are widely applied.
구리 금속 배선은 물리기상증착(PVD)법, 화학기상증착(CVD)법, 전기도금법 등이 사용되고 있으나, 현재의 추세는 확산 방지막, 물리기상증착법에 의한 구리 시드층 및 전기도금법에 의한 구리층을 순차적으로 형성하는 방법이 진행되고 있다. 그러나, 이러한 방법은 차세대 반도체 소자의 초고집적화 및 급격한 고성능화로 인해 콘택 크기의 감소와 급격한 단차(aspect ratio)의 증가로 적용하는데 한계가 있다.Physical metal deposition (PVD) method, chemical vapor deposition (CVD) method, electroplating method, etc. are used for copper metal wiring, but the current trend is copper seed layer by diffusion barrier film, physical vapor deposition method, and copper layer by electroplating method. The method of forming in order is progressing. However, this method has a limitation in application due to a decrease in contact size and a sudden increase in aspect ratio due to ultra-high integration and rapid high performance of next-generation semiconductor devices.
따라서, 본 발명은 배선 재료로 구리를 이용하는 듀얼 다마신 구조에서, 2 단계 공정으로 구리층을 매립하므로써, 우수한 단차 피복성 및 매립 특성으로 구리 금속 배선의 전기적 특성이 향상되어 속도가 개선되며, 소자의 집적도가 증가하여 콘택의 단차가 커지더라도 공정마진이 높아 불량을 감소시킬 수 있을 뿐만 아니라, 구리 금속 배선의 신뢰성, 안정성 및 성능을 향상시킬 있는 반도체 소자의 금속 배선 형성 방법을 제공함에 그 목적이 있다.Therefore, in the dual damascene structure using copper as the wiring material, by embedding the copper layer in a two-step process, the electrical characteristics of the copper metal wiring are improved and the speed is improved due to the excellent step coverage and embedding characteristics. The purpose of the present invention is to provide a method for forming a metal wiring of a semiconductor device, which can reduce defects due to a high process margin even if the level of contact increases due to an increase in the degree of integration, and improves the reliability, stability, and performance of copper metal wiring. have.
이러한 목적을 달성하기 위한 본 발명의 반도체 소자의 금속 배선 형성 방법은 비아 콘택홀과 트렌치로 이루어진 듀얼 다마신 패턴을 형성하는 단계; 상기 듀얼 다마신 패턴을 포함한 층간 절연막 상에 확산 방지막을 형성하는 단계; 상기 확산 방지막을 형성한 후에 진공파괴 없이 확산 방지막 상에 금속-유기 화학기상증착법으로 구리를 증착하여 상기 비아 콘택홀 부분이 완전히 매립되고, 상기 트렌치 부분에 얇게 증착되는 제 1 구리층을 형성하는 단계; 상기 제 1 구리층을 형성한 후에 진공파괴 없이 물리기상증착법으로 구리를 증착하여 상기 트렌치 부분이 완전히 매립되는 제 2 구리층을 형성하는 단계; 및 상기 제 1 구리층과 상기 제 2 구리층으로 된 구리층을 수소 가스 분위기에서 열처리하는 단계를 포함하여 이루어지는 것을 특징으로 한다.Method of forming a metal wiring of the semiconductor device of the present invention for achieving this purpose comprises the steps of forming a dual damascene pattern consisting of a via contact hole and a trench; Forming a diffusion barrier on the interlayer insulating layer including the dual damascene pattern; After forming the diffusion barrier layer, depositing copper on the diffusion barrier layer using a metal-organic chemical vapor deposition method without vacuum breaking to form a first copper layer in which the via contact hole part is completely buried and is thinly deposited on the trench part. ; Depositing copper by physical vapor deposition without vacuum destruction after forming the first copper layer to form a second copper layer in which the trench portion is completely buried; And heat-treating the copper layer formed of the first copper layer and the second copper layer in a hydrogen gas atmosphere.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.1A to 1D are cross-sectional views of a device for explaining a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.
〈도면의 주요 부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
11: 반도체 기판 12: 도전층11: semiconductor substrate 12: conductive layer
13: 층간 절연막 14: 듀얼 다마신 패턴13: interlayer insulating film 14: dual damascene pattern
14A: 비아 콘택홀 14B: 트렌치14A: Via Contact Hole 14B: Trench
15: 확산 방지막 16: 구리층15: diffusion barrier 16: copper layer
16A: 제 1 구리층 16B: 제 2 구리층16A: first copper layer 16B: second copper layer
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1D are cross-sectional views of devices for describing a method for forming metal wirings in a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 반도체 기판(11)에 도전층(12)을 형성하고, 도전층(12) 상에 층간 절연막(13)을 형성한다. 듀얼 다마신 방법으로 층간 절연막(13)의 일부분을 식각 하여 도전층(12)이 노출되는 비아 콘택홀(via contact hole; 14A)과 트렌치(trench; 14B)를 동시에 형성하여 듀얼 다마신 패턴(14)을 형성한다.Referring to FIG. 1A, a conductive layer 12 is formed on a semiconductor substrate 11, and an interlayer insulating layer 13 is formed on the conductive layer 12. A portion of the interlayer insulating layer 13 is etched by the dual damascene method to simultaneously form a via contact hole 14A and a trench 14B through which the conductive layer 12 is exposed, thereby forming a dual damascene pattern 14. ).
상기에서, 도전층(12)은 불순물 이온 주입으로 반도체 기판(11)에 형성되는 접합부이거나, 전극 또는 하부 금속 배선 등 본 발명에 의해 형성될 금속 배선과 연결될 소자의 모든 구성 요소가 포함된다. 비아 콘택홀(14A)과 트렌치(14B)를 갖는 듀얼 다마신 패턴(14)은 절연막상에 마스크를 이용하여 TiN 등으로 식각 방지막을 형성하고, 다시 절연막을 형성하여 트렌치 및 콘택을 동시에 형성한다. 이때 깊은 미세 콘택 형성을 위해서 충분한 포토레지스트(photoresist)를 100 내지 2000Å의 두께로 형성하도록 한다.In the above, the conductive layer 12 is a junction formed in the semiconductor substrate 11 by impurity ion implantation, or includes all components of an element to be connected to a metal wiring to be formed by the present invention, such as an electrode or a lower metal wiring. In the dual damascene pattern 14 having the via contact hole 14A and the trench 14B, an etch stop layer is formed of TiN or the like using a mask on the insulating film, and the insulating film is formed again to form trenches and contacts simultaneously. At this time, sufficient photoresist is formed to have a thickness of 100 to 2000 microns for deep microcontact formation.
도 1b를 참조하면, 듀얼 다마신 패턴(14)을 포함한 층간 절연막(13) 상에 확산 방지막(15)을 형성한다.Referring to FIG. 1B, the diffusion barrier layer 15 is formed on the interlayer insulating layer 13 including the dual damascene pattern 14.
상기에서, 확산 방지막(15)은 물리기상증착법이나 화학기상증착법으로 TiN, Ta, TaN, WNX, TiAl(N) 등을 10 내지 1000Å의 두께로 증착 하여 형성된다.In the above, the diffusion barrier 15 is formed by depositing TiN, Ta, TaN, WN X , TiAl (N), or the like in a thickness of 10 to 1000 kPa by physical vapor deposition or chemical vapor deposition.
도 1c를 참조하면, 확산 방지막(15)을 형성한 후에 진공파괴 없이 확산 방지막(15) 상에 금속-유기 화학기상증착(MOCVD)법으로 구리를 증착하여 비아 콘택(14A) 부분이 완전히 매립되고, 트렌치(14B) 부분에 얇게 증착되는 제 1 구리층(16A)을 형성한다.Referring to FIG. 1C, after forming the diffusion barrier 15, the via contact 14A is completely filled by depositing copper on the diffusion barrier 15 by metal-organic chemical vapor deposition (MOCVD) without vacuum destruction. The first copper layer 16A is thinly deposited on the trench 14B.
상기에서, 금속-유기 화학기상증착법으로 형성되는 제 1 구리층(16A)은 전구체(precursor)를 5 내지 100sccm(standard cubic centimeter per minute) 사용하고, 사용 가능한 전구체로는 (hfac)CuTMVS 및 첨가제가 포함된 그 혼합체, (hfac)CuVTMOS 및 첨가제가 포함된 그 혼합체, 또는 (hfac)CuPENTENE 및 첨가제가 포함된 그 혼합체를 사용한다. 증착 온도는 100 내지 300℃으로 한다. 챔버의 압력은 0.1 내지 5Torr정도로 하며, 전구체의 유속은 0.1 내지 3sccm으로 한다. 플라즈마 처리는 100 내지 500W의 전력에서 1분 내지 120분간 실시한다. 이때 플라즈마 가스로는 수소나 아르곤을 이용한다.In the above description, the first copper layer 16A formed by the metal-organic chemical vapor deposition method uses a precursor of 5 to 100 sccm (standard cubic centimeter per minute), and as a usable precursor, (hfac) CuTMVS and an additive are used. The mixtures included, (hfac) CuVTMOS and the mixtures containing additives, or (hfac) CuPENTENE and the mixtures containing additives are used. The deposition temperature is set to 100 to 300 ° C. The pressure of the chamber is about 0.1 to 5 Torr, and the flow rate of the precursor is about 0.1 to 3 sccm. Plasma treatment is carried out for 1 to 120 minutes at a power of 100 to 500W. At this time, hydrogen or argon is used as the plasma gas.
도 1d를 참조하면, 제 1 구리층(16A)을 형성한 후에 진공파괴 없이 물리기상증착법으로 구리를 증착하여 트렌치(14B) 부분이 완전히 매립되는 제 2 구리층(16B)을 형성하고, 고진공에서 수소 가스를 유입하여 300 내지 640℃의 온도에서 1분 내지 60분간 열처리하여 제 1 구리층(16A)과 제 2 구리층(16B)이 적층된 구리층(16)이 완성된다.Referring to FIG. 1D, after forming the first copper layer 16A, copper is deposited by physical vapor deposition without vacuum destruction to form a second copper layer 16B in which the trench 14B portion is completely embedded, and at high vacuum. Hydrogen gas is introduced and heat treated at a temperature of 300 to 640 ° C. for 1 to 60 minutes to complete the copper layer 16 having the first copper layer 16A and the second copper layer 16B laminated thereon.
상기에서, 물리기상증착법으로 형성되는 제 2 구리층(16B)은 100 내지 300℃의 증착 온도에서 증착한다. 플라즈마 처리는 100 내지 500W의 전력에서 1분 내지 10분간 실시한다. 이때 플라즈마 가스로는 수소나 아르곤을 이용한다.In the above, the second copper layer 16B formed by the physical vapor deposition method is deposited at a deposition temperature of 100 to 300 ℃. Plasma treatment is performed for 1 to 10 minutes at a power of 100 to 500W. At this time, hydrogen or argon is used as the plasma gas.
상기한 본 발명에 의하면, 고성능의 구리 금속 배선을 얻기 위해 듀얼 다마신 패턴을 형성한 후에 비아 콘택홀 부분을 먼저 금속-유기 화학기상증착법으로 매립하고, 물리기상증착법으로 트렌치를 매립하는 기술이다. 이 기술은 미세한 듀얼 다마신 구조로 되어 있는 배선에 확산 방지막으로 PVD TaN과 전기도금법으로 구리 배선을 적용하는 기술로는 한계가 있으므로, 이 방법을 사용하면 보다 더 작은 콘택 크기 및 높은 단차의 듀얼 다마신 구조에 적용이 가능한 매립 방법이다.According to the present invention described above, after the dual damascene pattern is formed in order to obtain high-performance copper metal wiring, the via contact hole portion is first buried by a metal-organic chemical vapor deposition method, and a trench is buried by a physical vapor deposition method. This technique has limitations in applying copper wiring by PVD TaN and electroplating as a diffusion barrier to wirings having a fine dual damascene structure. It is a landfill method that can be applied to the structure of drinking.
한편, 상기한 본 발명의 실시예에서 기재된 본 발명의 기술적 원리를 적용하여, 금속 배선 재료로 구리 대신에 알루미늄이나 텅스텐 등을 사용하여 금속 배선을 형성할 수 있다.On the other hand, by applying the technical principles of the present invention described in the embodiments of the present invention described above, metal wirings can be formed using aluminum, tungsten, or the like instead of copper as the metal wiring material.
상술한 바와 같이, 본 발명은 비아 콘택홀 및 트렌치를 갖는 듀얼 다마신 구조를 형성한 후, 듀얼 다마신 패턴 상에 확산 방지막을 얇게 형성하고, 화학기상증착법으로 확산 방지막상에 구리를 얇게 증착하여 비아 콘택 부분을 매립시키고, 물리기상증착법으로 1차 증착된 구리층 상에 구리를 증착하여 트렌치를 완전히 매립시켜 금속 배선용 구리층을 형성하므로써, 우수한 단차 피복성 및 매립 특성으로 구리 금속 배선의 전기적 특성이 향상되어 속도가 개선되며, 소자의 집적도가 증가하여 콘택의 단차가 커지더라도 공정마진이 높아 불량을 감소시킬 수 있을 뿐만 아니라, 구리 금속 배선의 신뢰성, 안정성 및 성능을 향상시킬 있다.As described above, the present invention forms a dual damascene structure having via contact holes and trenches, and then forms a thin diffusion barrier layer on the dual damascene pattern, and deposits a thin copper layer on the diffusion barrier layer by chemical vapor deposition. By filling the via contact portion, depositing copper on the first deposited copper layer by physical vapor deposition, and completely filling the trench to form a copper layer for metal wiring, the electrical characteristics of the copper metal wiring with excellent step coverage and filling characteristics This improves the speed, improves the integration level of the device, and increases the process margin even when the contact height increases, thereby reducing defects and improving reliability, stability, and performance of the copper metal wiring.
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| KR100743770B1 (en) * | 2000-12-05 | 2007-07-30 | 주식회사 하이닉스반도체 | Method of forming a copper metal wiring in a semiconductor device |
| KR100635872B1 (en) * | 2000-12-28 | 2006-10-18 | 매그나칩 반도체 유한회사 | A method for forming a metal line of semiconductor device |
| KR100713900B1 (en) * | 2001-02-23 | 2007-05-07 | 주식회사 하이닉스반도체 | Method for manufacturing metal line in semiconductor device |
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