KR100186509B1 - Method of forming metal interconnector in semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to metallization of semiconductor devices, and more particularly, to a method of forming a semiconductor device suitable for simplifying the process and improving resistance and reliability of the wiring.

The wiring forming method of the semiconductor device of the present invention for this purpose is a step of forming a first insulating layer on the substrate on which the lower conductive layer is formed, and selectively removing the first insulating layer to form a connection hole and includes the connection hole Forming a first conductive material layer on the entire surface, selectively removing a second insulating layer on the first conductive material layer, and forming a second insulating layer on the exposed first conductive material layer, Selectively raising the second insulating layer in a width that is extended to the center thereof, including the connection hole, and forming a second conductive material layer at the same height as the second insulating layer on the exposed first conductive material layer And removing the second insulating layer and removing the exposed first conductive material layer.

Description

Wiring Formation Method of Semiconductor Device

1 (a) to (e) are process cross-sectional views showing a wiring forming method of a conventional semiconductor device.

2A to 2E are cross-sectional views illustrating a method of forming wirings in a semiconductor device according to a first embodiment of the present invention.

2 (a) to 2 (d) are cross sectional views showing a wiring forming method of a semiconductor device according to a second embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

20: substrate 21: lower conductive line

22: first insulating layer 23: connection hole

24: first conductive material layer 25: second insulating layer

26: second conductive material layer 27: upper conductive line

The present invention relates to a wiring forming method of a semiconductor integrated circuit, and more particularly, to a wiring forming method of a semiconductor device that is suitable for simplifying the process and improving the resistance and reliability of the wiring.

In general, aluminum and its alloy thin films have high electrical conductivity and excellent pattern formation by dry etching. In addition, it has been widely used as a wiring material for semiconductor circuits because of its excellent adhesion with a silicon oxide film and relatively low cost.

However, as the degree of integration of integrated circuits increases, the size of the device decreases and the wiring becomes fine and multi-layered, so that the stepcoverge inside a portion having a topology, a contact hole or a via hole, etc. ) Has emerged as an important issue.

That is, when the sputtering method, which is a conventional metal wiring film forming method, is used, the thickness of the wiring film is locally thinned by the shadow effect in the curved portion.

In particular, it is more severe in connection holes having an aspect ratio of 1 or more.

Therefore, instead of the physical vapor deposition method, a chemical vapor deposition method that can be deposited with a uniform thickness was introduced, and a study to improve the step coverage by forming a tungsten film by a low pressure chemical vapor deposition method was performed.

However, since the tungsten wiring film has a resistivity twice or more than that of the aluminum wiring film, it is difficult to apply it as a wiring film. Therefore, development as a method of forming a buried layer (plug) in the connection hole is in progress.

The buried layer is formed by selectively growing a tungsten film through a substrate exposed in a connection hole by applying a selective chemical vapor deposition method, or by forming a barrier metal film or an adhesive layer, and then depositing a tungsten film on the entire surface and etching it back to a deposition thickness or more. There is a way.

However, in such a selective growth method, it is not easy to maintain the growth on the insulating layer.

In the case of etching back after full deposition, it is necessary to form a reliable barrier layer or adhesive layer in a connection hole having a high aspect ratio.

To this end, a collimator or chemical vapor deposition (CVD) method should be used to ensure the minimum thickness of tungsten nucleation on the bottom or sidewall of the connection hole.

On the other hand, since the depth of the connection hole depends on the degree of flattening of the insulating layer, the surface of the connection hole and the surface of the investment layer are not substantially the same (generally, the surface of the investment layer is lower).

On the other hand, if aluminum-based wiring films are formed by chemical vapor deposition, step coverage can be improved and continuity with the surrounding processes of aluminum wiring film technology by conventional sputtering such as photolithography and etching can be maintained. So it is advantageous.

On the other hand, copper (copper) has a lower specific resistance than aluminum, and excellent electrical conductivity or stress migration (stress migration) characteristics can further improve the reliability.

Therefore, a method of forming copper by sputtering or chemical vapor deposition has been studied.

However, when a halogen compound useful for etching aluminum is applied to copper etching, since the vapor pressure of the halogen compound is low, the operating temperature must be raised to about 500 ° C. in order to obtain an applicable etching rate. Thus, in the case of copper wiring, instead of direct patterning by etching, trenches are formed in the substrate in the form of wiring patterns.

After the copper is deposited, it is etched back by Chemical Mechanical Polishing (CMP) method to form a buried conductive line or vertical growth by using a lower conductive layer of a contact hole or a via hole as a seed. Has been attempted to selectively form a plug.

As a method of forming a wiring by selectively depositing copper, a copper pattern is formed by selectively depositing copper on a seed layer using a TEOS oxide film pattern as a sacrificial film for wiring formation, removing the TEOS oxide film, and selectively etching the seed layer. Formed.

Hereinafter, a wiring forming method of a conventional semiconductor device will be described with reference to the accompanying drawings.

1 (a) to (e) are cross-sectional views of a conventional metal wiring process (Thin Solid Films 262 (1995) p. 52-59).

First, as shown in FIG. 1A, the lower conductive line 2 is formed on the substrate 1, and the interlayer insulating layer 3 is formed on the entire surface including the oxide film by using an oxide film or the like.

Subsequently, the interlayer insulating layer 3 is selectively etched to form a connection hole 4 for electrical connection with an upper conductive line formed in a later process, and conductive material such as W is formed in the connection hole 4. Deposit and etch back or selectively grow to form a buried plug 5.

Then, a nucleation layer 6 for depositing Cu for forming an upper conductive line is formed on the interlayer insulating layer 3 including the buried plug 5.

The nucleation layer 6 is formed of a laminated film of W and TiN so as to be suitable as an adhesive force and a diffusion barrier of Cu.

Next, a tetraethyleorthosilicate (TEOS) layer 7 is formed on the nucleation layer 6 as a sacrificial insulating film.

As shown in FIG. 1B, the TEOS layer 7 is selectively etched in the form of an upper conductive line to form a trench 8 to expose a portion of the nucleation layer 6.

Then, as shown in FIG. 1 (c), the Cu film is selectively grown on the exposed nucleation layer 6 using a metal orgarnic source such as (hfac) Cu (VTMS): (heafluoroacetylacetonate) Cu (vinyltrimethylsilane). The trench 8 is then buried.

As shown in FIG. 1D, the TEOS layer 7 is removed to expose the nucleation layer 6 except for the Cu film.

Subsequently, the exposed nucleation layer 6 is selectively removed using the Cu film as a mask to form an upper conductive line 9 composed of the nucleation layer 6 and the Cu film.

However, in the above-described flattened wiring technology, since the buried plug is formed in the connection hole and the nucleation layer and the upper conductive line are formed, the process of forming the buried plug and the upper conductive line is performed separately. There is a problem.

An interface caused by a heterogeneous material such as a nucleation layer is generated between the surface of the buried plug and the upper conductive line, resulting in an increase in contact resistance or deterioration in reliability such as electromigration.

In addition, a sacrificial insulating film is used as the TEOS layer, but it is not effective because it is not used as an interlayer insulating film.

The present invention has been made to solve the above problems of the metal wiring of the prior art, a buried plug and the upper conductive wire is formed by using the same material at the same time to simplify the process and improve the resistance characteristics and reliability of the wiring It is an object of the present invention to provide a method for forming metal wiring in an apparatus.

The metal wiring forming method of the semiconductor device of the present invention for achieving the above object is a step of forming a first insulating worm on the substrate on which the lower conductive layer is formed, and selectively removing the first insulating layer to form a connection hole And forming a first conductive material layer on the front surface including the connection hole, and forming a second insulating layer on the first conductive material layer, and including the connection hole to extend the width of the first conductive material layer. Selectively removing the second insulating layer, forming a second conductive material layer on the exposed first conductive material layer at the same height as the second insulating layer, and removing the second insulating layer and exposing the first layer. And removing the conductive material layer.

Hereinafter, a wiring forming method of a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are process cross-sectional views showing a wiring forming method of a semiconductor device according to a first embodiment of the present invention.

In the method for forming a wiring of a semiconductor device according to the first embodiment of the present invention, in the method for forming a pattern of the conductive line by selectively growing a conductive material such as Cu on the nucleation layer, the buried plug and the conductive line filling the connection hole are formed. It is formed simultaneously with the same material.

In the wiring forming method of the semiconductor device according to the first embodiment of the present invention, first, as shown in FIG. 2 (a), the lower wiring or the lower conductive layer 21 is formed on the semiconductor substrate 20 and electrically connected thereto. In order to insulate, the first insulating film 22 is formed using an oxide film or the like.

The first insulating film 22 is selectively etched to form a connection hole 23 in order to be connected to the upper wiring or the upper conductive layer formed in a later step.

Subsequently, as shown in FIG. 2 (b), the first conductive material as a seed layer for preventing the diffusion of the main material constituting the upper wiring layer or the upper conductive layer formed in a later process and growing the upper conductive layer. 24 is formed on the first insulating film 22 including the connection holes 23.

At this time, the first conductive material 2 is formed of metal compounds such as TiN, TiW, W, or the like by sputtering or chemical vapor deposition (CVD).

Subsequently, as shown in FIG. 2 (c), a second insulating film 25, such as a tetraethyleorthosilicate (TEOS) oxide film, is formed on the entire surface including the first conductive material 24 as a sacrificial insulating film, and a trench is formed in the form of a conductive line. Thereby selectively exposing the first conductive material 24 of the trench bottom surface.

Subsequently, the buried plug and the upper conductive layer are formed by growing the second conductive material 26 on the exposed first conductive material 24 and filling it in the connection hole 23 and the trench as shown in FIG. (27) is formed simultaneously.

In this case, as the upper conductive layer 27, a metal such as aluminum, Ag, Cu, or a metal alloy thereof is used.

In the case where aluminum (Al) is applied as the second conductive material 26, when the aluminum is applied, an organic metal CVD (MOCVD) device is used.

In this case, as an organometallic source, DMEAA (Dimethylethylamine alane), that is, [(CH ₃ ) ₂ (CH ₃₎

CH ₂ ) N] AlH ₃ is incorporated through a carrier gas using a bubbler.

At this time, the pressure is 0.5 ~ 5torr, the flow rate is 100 ~ 1000sccm, and the temperature is 130 ~ 170 ℃. In addition, when copper (Cu) is applied, a liquid source such as (hfac) Cu (TMVS): (heafluroacetylacetonate Cu trimethylvinylsilane) or Cu (hfac) ₂

It is formed by the MOCVD method using a solid source such as.

Subsequently, as shown in FIG. 2E, after removing the second insulating film 25 used as the sacrificial insulating film, the first conductive material 24 is selectively removed using the upper conductive layer 27 as a mask. The wiring forming process of the semiconductor device according to the first embodiment of the invention is completed.

3 (a) to 3 (d) are process cross-sectional views showing a wiring forming method of the semiconductor device according to the second embodiment of the present invention.

The second embodiment of the present invention is a method of using the interlayer insulating film without removing the sacrificial insulating film even after the upper wiring is formed.

First, as shown in FIG. 3A, the lower conductive layer 32 is formed on the substrate 31, and the first insulating layer 33 is formed on the whole including the lower conductive layer 32.

Subsequently, a first photoresist (not shown) is applied and then patterned.

By using the patterned first photoresist as a mask, the insulating layer 33 is selectively removed so that a portion of the surface of the lower conductive layer 32 is exposed, thereby connecting for electrical connection with the upper conductive layer to be formed in a later process. The hole 34 is formed.

Subsequently, as illustrated in FIG. 3B, the first conductive material layer 35 is formed on the entire surface including the exposed lower conductive layer 32 and then selectively etched.

At this time, the first conductive material layer 35 is used as a seed layer for preventing the diffusion of the main material constituting the upper conductive layer to be formed in a later process and growing the upper conductive layer.

As the material, metal compounds such as TiN, TiW, W, or metal materials are used, and are formed by sputtering or chemical vapor deposition.

Subsequently, as illustrated in FIG. 3C, a second insulating layer 36 is formed on the first doped material layer 35 including the first insulating layer 33.

The second insulating layer 36, such as the TEOS oxide layer, is selectively etched to expose the surface of the first conductive material layer 35 to form the trench 37 for the upper conductive layer pattern.

Subsequently, as shown in FIG. 3 (d), the buried plug and the top conduction are selectively grown by filling the second conductive material layer on the first conductive material layer 35 and filling it in the connection hole 34 and the trench 37. Forming the layer 38 simultaneously completes the wiring forming process of the semiconductor device according to the second embodiment of the present invention.

At this time, as the second conductive material 38, a metal such as aluminum, Ag, Cu or the like or a metal alloy thereof is applied. When aluminum (Al) is applied as the second conductive material 38, an organic metal CVD (MOCVD) device is used.

In this case, as the organometallic source, DEMEAA (Dimethylethylamine alane), that is, [(CH ₃ ) ₂ (CH

₃ CH ₂ ) N] AlH ₃ is mixed through a carrier gas using a bubbler.

At this time, the pressure is 0.5 ~ 5torr, the flow rate is 100 ~ 1000sccm, and the temperature is 130 ~ 170 ℃. In addition, when copper (Cu) is applied, a liquid source such as (hfac) Cu (TMVS): (heafluroacetylacetonate Cu trimethylvinysilane) or Cu (hfac) _{2 is used.}

It is formed by the MOCVD method using a solid source such as.

As described above, the wiring forming method of the semiconductor device of the present invention has the following effects.

First, the landfill plug and the upper conductive layer are formed at the same time to simplify the process.

Second, no heterogeneous material is formed between the buried plug and the upper conductive layer, thereby improving the contact resistance and reliability of the wiring.

Third, it does not use a separate interlayer insulating film to improve the efficiency of the process.

Claims (24)

Forming a first insulating layer on the substrate on which the lower conductive layer is formed; Selectively removing the first insulating layer to form a connection hole and forming a seed layer in a region including the connection hole; Forming a second conductive layer on the first insulating layer including the seed layer and then selectively removing the second insulating layer to form an upper conductive layer pattern extending with the connection hole; And forming a second conductive material layer in the connection hole and the upper conductive layer pattern. The method of claim 1, A wiring forming method for a semiconductor device, wherein the first insulating layer is formed using an oxide film. The method of claim 1, wherein the seed layer is a conductive layer for preventing diffusion of an upper conductive layer and growing an upper conductive layer. And the material of the upper conductive layer is one of aluminum, silver, and copper. The method of claim 1, And a material of the seed layer is a metal compound such as TiN, TiW, W or a metal material. The method of claim 4, wherein When aluminum is used as the material of the upper conductive layer, MOCVD is used, and as an organic metal source, DMEAA (Dimethyleethyiamine alane), that is, [(CH ₃ ) ₂ (CH ₃ CH ₂ ) N] AlH ₃ is used. A wiring formation method of a semiconductor device. The method of claim 6, In case of using aluminum, the pressure is 0.5 ~ 5torr, the flow rate is 100 ~ 1000sccm, and the temperature is 130 ~ 170 ℃. The method of claim 4, wherein When the copper is applied, the source thereof is (hfac) Cu (TMVS): (hexafluroacetylaceto A method of forming a wiring in a semiconductor device, comprising using a liquid source such as nate Cu trimethylvinylsilane) or a solid source such as Cu (hfac) ₂ . Forming a first insulating layer on the substrate on which the lower conductive layer is formed; Selectively removing the first insulating layer to form a first connection hole and forming a first conductive material layer on the front surface including the connection hole; Forming a second connection hole on the first conductive material layer and then selectively removing the second insulating layer to form a second connection hole extending from the first connection hole and having a wider width than the first connection hole; , Forming an upper conductive layer by forming a second conductive material layer on the first conductive material layer at the same height as the second insulating layer; Removing the second insulating layer and removing the exposed first conductive material layer. The method of claim 9, And the first conductive material layer is a seed layer for preventing diffusion of the upper conductive layer and for growing the upper conductive layer. The method of claim 10, The method of claim 9, The material of the second insulating layer is a TEOS (Tetraethyleorthosilicate) oxide film. The method of claim 9, And wherein the second conductive material layer is any one of aluminum, silver, and copper. The method of claim 13, When aluminum is applied as the second conductive material layer, a MOCVD apparatus is used, and as an organometallic source, dimethyleethyiamine alane (DMEAA), that is, [(CH ₃ ) ₂ (CH ₃ CH ₂ ) N] A method for forming a wiring of a semiconductor device, characterized by using AlH ₃ . The method of claim 14, In case of using aluminum, the pressure is 0.5 ~ 5torr, the flow rate is 100 ~ 1000sccm, and the temperature is 130 ~ 170 ℃. The method of claim 13, When the copper is applied, the source thereof is (hfac) Cu (TMVS): (hexafluroacetylaceto A method of forming a wiring in a semiconductor device, comprising using a liquid source such as nate Cu trimethylvinylsilane) or a solid source such as Cu (hfac) ₂ . Forming a first insulating layer on the substrate on which the lower conductive layer is formed; Selectively removing the first insulating layer to form a first connection hole and forming a first conductive material layer on the entire surface including the connection hole; Selectively removing the first conductive material layer and forming a second insulating layer on the entire surface including the first conductive material layer; Selectively removing the second insulating layer to form a second connection hole extending with the first connection hole and having a width wider than that of the first connection hole; And growing a second conductive material layer on the first conductive material layer to form an upper conductive layer having the same height as that of the second insulating layer. The method of claim 17, And the first conductive material layer is a seed layer for preventing diffusion of the upper conductive layer and for growing the upper conductive layer. The method of claim 18, The first conductive material is a metal compound or a metal material such as TiN, TiW, W, the wiring forming method of a semiconductor device. The method of claim 17, The material of the second insulating layer is a TEOS (Tetraethyleorthosilicate) oxide film. The method of claim 17, And wherein the second conductive material layer is any one of aluminum, silver, and copper. The method of claim 21, When aluminum is applied as the second conductive material layer, a MOCVD apparatus is used, and as an organometallic source, dimethyleethyiamine alane (DMEAA), that is, [(CH ₂ ) ₃ (CH ₃ CH ₂ ) N] A method for forming a wiring of a semiconductor device, characterized by using AlH ₃ . The method of claim 22, In case of using aluminum, the pressure is 0.5 ~ 5 torr, the flow rate is 100 ~ 1000sccm, and the temperature is 130 ~ 170 ℃. When the copper is applied, the source thereof is (hfac) Cu (TMVS): (hexafluroacetylaceto A method of forming a wiring in a semiconductor device, comprising using a liquid source such as nate Cu trimethylvinylsilane) or a solid source such as Cu (hfac) ₂ .