KR100195330B1 - Semiconductor ic wire and forming method - Google Patents
Semiconductor ic wire and forming method Download PDFInfo
- Publication number
- KR100195330B1 KR100195330B1 KR1019950065783A KR19950065783A KR100195330B1 KR 100195330 B1 KR100195330 B1 KR 100195330B1 KR 1019950065783 A KR1019950065783 A KR 1019950065783A KR 19950065783 A KR19950065783 A KR 19950065783A KR 100195330 B1 KR100195330 B1 KR 100195330B1
- Authority
- KR
- South Korea
- Prior art keywords
- conductive layer
- layer
- connection hole
- forming
- integrated circuit
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 238000000034 method Methods 0.000 title claims abstract description 33
- 230000004888 barrier function Effects 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 6
- 239000004020 conductor Substances 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 28
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 28
- 238000005229 chemical vapour deposition Methods 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 19
- 239000010949 copper Substances 0.000 claims description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 15
- 229910052802 copper Inorganic materials 0.000 claims description 14
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 7
- 229910052709 silver Inorganic materials 0.000 claims description 7
- 239000004332 silver Substances 0.000 claims description 7
- 150000002902 organometallic compounds Chemical class 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 5
- 230000001939 inductive effect Effects 0.000 claims 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims 1
- 239000010408 film Substances 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000006911 nucleation Effects 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- -1 copper Chemical compound 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000011534 incubation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 집적회로 배선구조 및 그의 형성방법에 관한 것으로써, 하부의 제1전도층과, 제1전도층과의 사이에 제1전도층과의 반응을 조절하기위한 전도성물질인 배리어층을 개재하여 형성되고, 저저항 전도성물질로 된 상부의 제2전도층을 포함하여 이루어진 샌드위치 형태의 배선구조이며, 본 발명의 반도체 집적회로 배선 형성방법은, 1) 반도체 기판에 절연층을 형성하는 단계와, 2) 절연층을 식각하여 접속구멍(contact hole)을 형성하는 공정과, 3) 절연층 전면을 덮도록 제1전도층을 형성하여 접속구멍 바닥에서 반도체 기판과 접속되도록 형성하는 단계와, 4) 제1전도층 전면을 덮도록 전도성물질인 배리어층과, 제2전도층을 순차로 형성하되, 배리어층은 제1전도층과 제2전도층 사이에서 제1전도층과 제2전도층의 반응조절하기 위한 배리어층이고, 제2전도층의 상면이 비교적 평탄하도록 형성하는 단계를 포함하여 이루어진다.The present invention relates to a semiconductor integrated circuit wiring structure and a method of forming the same, and includes a barrier layer, which is a conductive material for controlling a reaction between a first conductive layer and a first conductive layer between the lower conductive layer and the first conductive layer. It is a sandwich-type wiring structure formed through the second conductive layer formed of a low resistance conductive material, interposed, the semiconductor integrated circuit wiring formation method of the present invention, 1) forming an insulating layer on a semiconductor substrate 2) forming a contact hole by etching the insulating layer, and 3) forming a first conductive layer to cover the entire surface of the insulating layer so as to be connected to the semiconductor substrate at the bottom of the connecting hole; 4) A barrier layer and a second conductive layer which are conductive materials are sequentially formed to cover the entire surface of the first conductive layer, and the barrier layer is formed between the first conductive layer and the second conductive layer. Barrier layer for controlling the reaction of And the second comprises the step of forming the upper surface of the conductive layer to be relatively flat.
Description
제1도는 본 발명에 따른 일실시예의 반도체 집적회로 배선구조를 설명하기 위해 도시한 반도체 소자의 일부 단면도.1 is a partial cross-sectional view of a semiconductor device shown for explaining a semiconductor integrated circuit wiring structure of an embodiment according to the present invention.
제2도의 (a) 내지 (e)는 본 발명에 따른 일실시예의 반도체 집적회로 배선 형성방법을 설명하기 위해 반도체 소자의 일부를 도시한 공정 단면도.2A to 2E are cross-sectional views showing a part of a semiconductor device for explaining a method for forming a semiconductor integrated circuit wiring according to an embodiment of the present invention.
제3도는 본 발명의 다른 실시예의 반도체 집적회로 배선구조 및 그의 형성방법을 설명하기 위해 도시한 반도체 소자 일부의 단면도.3 is a cross-sectional view of a portion of a semiconductor device shown for explaining a semiconductor integrated circuit wiring structure and a method of forming the same according to another embodiment of the present invention.
제4도는 본 발명의 또 다른 실시예의 반도체 집적회로 배선구조 및 그의 형성방법을 설명하기 위해 도시한 반도체 소자 일부의 단면도.4 is a cross-sectional view of a portion of a semiconductor device shown for explaining a semiconductor integrated circuit wiring structure and a method of forming the same according to another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 실리콘기판 12 : 불순물 확산영역11 silicon substrate 12 impurity diffusion region
13 : 절연층 14 : 접속구멍13 insulation layer 14 connection hole
15a,15b,15c : 배선층 15a-1,15b-1,15c-1 : 제1전도층15a, 15b, 15c: wiring layer 15a-1, 15b-1, 15c-1: first conductive layer
15a-2,15b-2,15c-2 : 배리어층 15a-3,15b-3,15c-3 : 제2전도층15a-2,15b-2,15c-2: barrier layer 15a-3,15b-3,15c-3: second conductive layer
16 : 감광막마스크16: photoresist mask
본 발명은 반도체 집적회로의 배선구조 및 그의 형성방법에 관한 것으로써, 배리어(Barrier) 물질을 중간에 가지는 샌드위치 배선구조를 채택하므로써 배선의 저항과 신뢰성을 개선할 수 있도록 한 배선구조 및 그의 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure of a semiconductor integrated circuit and a method for forming the same. The present invention relates to a wiring structure and a method of forming the same, by adopting a sandwich wiring structure having a barrier material in between. It is about.
알루미늄과 그 합금박막은 전기전도도가 높고, 건식식각에 의한 패턴 형성이 용이하며 실리콘산화막과의 접착성이 우수한 동시에 비교적 가격이 저렴하므로 반도체 회로의 배선재료로써 널리 사용되어 왔다. 한편 구리는 알루미늄에 비하여 비저항(Resistivity)이 낮고 일렉트로마이그레이션(Electromigration)이나 스트레스 마이그레이션(Stress Migration) 특성이 우수하므로 신뢰성을 더욱 개선할 수 있으며, 스퍼터링이나 화학기상증착법으로 형성하는 방법이 연구되고 있다. 그러나 알루미늄이나 구리를 전도선으로 적용하는 경우에는 실리콘과의 사이에 배리어(Barrier) 물질을 개재할 필요가 있다. 특히 구리는 실온(room temperature)에서 실리콘 내에서의 확산계수가 10-8cm2/sec으로 매우 빠른 격자간 침입형(interstitial) 확산속도를 나타낸다. 또 실리콘 내에 고용된 Cu는 재결합 센터(recombination center)로 작용하므로 소수 캐리어(minority carrier)의 수명을 감소시키고 소자의 성능을 저해하는 요인이 된다. 알루미늄의 경우, DMAH나 DMEAA 등의 소오스 가스를 이용하여 알루미늄 전도선을 형성하는 경우에 있어서도 절연막 위에서는 알루미늄막의 핵생성을 위한 인큐베이션(Incubation) 시간이 길므로 전면(Blanket) 증착을 위해서도 Ti/TiN 등의 배리어 물질이 필요하게 된다. 따라서, 일반적인 반도체 집적회로 제조에 있어서 접속구멍(contact hole)을 형성한 후, 실리콘과의 사이에 확산방지와 핵생성층으로써의 역할을 위해 전도성의 배리어 물질을 형성이 필요하게 된다.Aluminum and its alloy thin films have been widely used as wiring materials for semiconductor circuits because of their high electrical conductivity, easy pattern formation by dry etching, good adhesion with silicon oxide films, and relatively low cost. On the other hand, copper has a lower resistivity and better electromigration or stress migration characteristics than aluminum, so that the reliability can be further improved and a method of forming by sputtering or chemical vapor deposition has been studied. However, when aluminum or copper is used as the conductive line, it is necessary to interpose a barrier material with silicon. In particular, copper exhibits a very fast interstitial diffusion rate with a diffusion coefficient of 10 −8 cm 2 / sec in silicon at room temperature. In addition, Cu dissolved in silicon acts as a recombination center, reducing the lifetime of minority carriers and degrading device performance. In the case of aluminum, even in the case of forming an aluminum conductive line using source gas such as DMAH or DMEAA, the incubation time for nucleation of the aluminum film is long on the insulating film, so that Ti / TiN is also used for blanket deposition. Barrier materials such as these are required. Therefore, after forming contact holes in general semiconductor integrated circuit fabrication, it is necessary to form a conductive barrier material for preventing diffusion and acting as a nucleation layer between silicon.
그런데, 배리어층의 형성에 있어서는 집적회로의 집적도가 증가함에 따라 소자의 크기가 감소하고 배선이 미세화, 다층화되므로써 높은 종횡비(aspect ratio)를 갖는 접속구멍의 밑면과 측면에서의 단차피복성의 영향을 받게 된다. 즉, 접속구멍 밑면이나 측벽에 배리어 특성을 유지할 수 있는 최소 두께 이상을 확보하여 신뢰성 있는 배리어를 형성하기 위하여 기존에는 시준기(collimator)를 이용한 스퍼터링이나 화학기상증착법(CVD)을 적용해야만 했다. 따라서, 공정이 복잡하고 재현성 및 가공성이 불리한 문제가 있었다.However, in the formation of the barrier layer, as the degree of integration of the integrated circuit increases, the size of the device decreases and the wiring becomes finer and multilayered, thereby affecting the step coverage of the bottom and side surfaces of the connection hole having a high aspect ratio. do. In other words, sputtering using a collimator or chemical vapor deposition (CVD) has to be applied in order to form a reliable barrier by securing a minimum thickness that can maintain a barrier property on the bottom or sidewall of the connection hole. Therefore, there is a problem that the process is complicated and the reproducibility and workability are disadvantageous.
이에 본 발명의 반도체 집적회로의 배선구조는. 하부의 제1전도층과, 제1전도층과의 사이에 제1전도층과의 반응을 조절하기 위한 전도성물질인 배리어층을 개재하여 형성되고, 저저항 전도성물질로 된 상부의 제2전도층을 포함하여 이루어진 샌드위치 형태의 배선구조이다.Therefore, the wiring structure of the semiconductor integrated circuit of the present invention. An upper second conductive layer formed of a low resistance conductive material formed between a lower first conductive layer and a first conductive layer through a barrier layer that is a conductive material for controlling a reaction with the first conductive layer. The sandwich structure includes a wiring structure.
구체적으로는, 반도체 기판과, 반도체 기판 위에 형성되고 접속구멍(contact hole)이 형성된 절연층과, 제1전도층과, 제1전도층과의 사이에 제1전도층과의 반응을 조절하기 위한 배리어층을 개재하여 형성되는 제2전도층을 포함하여 이루어진 샌드위치 형태의 배선층이, 절연층 상에 형성되고 접속구멍을 통하여 반도체 기판과 접속된 것이 특징이다.Specifically, for controlling the reaction between the semiconductor substrate, an insulating layer formed on the semiconductor substrate and having a contact hole, the first conductive layer, and the first conductive layer between the first conductive layer and the first conductive layer. A sandwich-type wiring layer including a second conductive layer formed through a barrier layer is formed on an insulating layer and connected to a semiconductor substrate through a connection hole.
여기서, 배선층과 반도체 기판의 접속은 제1전도층, 배리어층 및 제2전도층이 접속구멍을 채우며 접속구멍 내에서 샌드위치 형태를 이루며 접속되거나, 제1전도층이 접속구멍을 실질적으로 매립하여 접속되거나, 제1전도층과 배리어층이 접속구멍을 매립하되 접속구멍에 매립된 배리어층 부위는 내부가 빈 형태를 포함하며 적어도 접속구멍의 상부쪽에서 접속구멍을 폐쇄한다. 또, 제1전도층은 플라즈마 화학기상증착법(CVD)로 형성된 층이며, 제2전도층은 저저항 물질로써 알루미늄, 구리 또는 은으로 형성되거나 이들의 화합물로 형성된다.Here, the connection between the wiring layer and the semiconductor substrate is made by connecting the first conductive layer, the barrier layer, and the second conductive layer to form a sandwich in the connection hole while filling the connection hole, or the first conductive layer is connected by substantially filling the connection hole. Alternatively, the first conductive layer and the barrier layer fill the connection hole, but the barrier layer portion embedded in the connection hole has a hollow interior and closes the connection hole at least at the upper side of the connection hole. The first conductive layer is a layer formed by plasma chemical vapor deposition (CVD), and the second conductive layer is formed of aluminum, copper, or silver as a low resistance material, or a compound thereof.
본 발명의 반도체 집적회로 배선 형성방법은, 1) 반도체 기판에 절연층을 형성하는 단계와, 2) 절연층을 식각하여 접속구멍(contact hole)을 형성하는 공정과, 3) 접속구멍 부위를 포함한 절연층 전면을 덮도록 제1전도층을 형성하여, 접속구멍바닥에서 반도체 기판과 접속되도록 형성하는 단계와, 4) 제1전도층 전면을 덮도록 전도성물질인 배리어층과, 제2전도층을 순차로 형성하되, 배리어층은 제1전도층과 제2전도층 사이에서 제1전도층과 제2전도층의 반응조절하기 위한 층이고, 접속구멍 부위의 제2전도층 상면이 비교적 평탄하도록 형성하는 단계를 포함하여 이루어진다.The method for forming a semiconductor integrated circuit wiring according to the present invention includes the steps of 1) forming an insulating layer on a semiconductor substrate, 2) forming a contact hole by etching the insulating layer, and 3) a connection hole portion. Forming a first conductive layer to cover the entire surface of the insulating layer, and forming a first conductive layer to be connected to the semiconductor substrate at the bottom of the connection hole; The barrier layer is sequentially formed, and the barrier layer is a layer for controlling the reaction between the first conductive layer and the second conductive layer between the first conductive layer and the second conductive layer, and the upper surface of the second conductive layer in the connection hole is relatively flat. It comprises a step.
여기서, 제1전도층은 유기금속화합물을 소오스(source) 가스로한 알루미늄을 플라즈마 화학기상증착법을 이용하여 형성하되, DMEAA를 소오스 가스로 이용하여 300 내지 800mTorr의 압력과 100℃ 내지 300℃의 온도에서 5 내지 50W의 전력으로 플라즈마를 유기시켜서 증착하고, 제2전도층을 형성은, 저저항물질로써 알루미늄, 구리 또는 은으로 형성되거나 이들의 화합물로 형성되며, 유기금속화합물로 된 소스를 이용하여 플라즈마 CVD법을 이용한다.Here, the first conductive layer is formed by using a plasma chemical vapor deposition method of aluminum with a source gas of the organometallic compound, using DMEAA as a source gas at a pressure of 300 to 800mTorr and a temperature of 100 ℃ to 300 ℃ The plasma is organically deposited at a power of 5 to 50 W, and the second conductive layer is formed by using aluminum, copper, or silver as a low resistance material, or a compound thereof, and using a source made of an organometallic compound. The CVD method is used.
또한, 반도체 기판과 배선층의 접속을 위해 제1전도층이 접속구멍을 실질적으로 매립하거나, 제1전도층과 배리어층으로 접속구멍을 매립하되, 배리어층은 접속구멍의 상부쪽에서 접속구멍을 폐쇄하도록 형성된다.In addition, the first conductive layer substantially fills the connection hole for the connection between the semiconductor substrate and the wiring layer, or the connection hole is filled with the first conductive layer and the barrier layer, but the barrier layer closes the connection hole at the upper side of the connection hole. Is formed.
이하, 첨부한 도면을 참조하여 본 발명의 실시예를 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제1도는 본 발명에 따른 일실시예의 반도체 집적회로 배선구조를 설명하기 위해 도시한 반도체 소자의 일부 단면도이고, 제2도의 (a) 내지 (e)는 본 발명에 따른 일실시예의 반도체 집적회로 배선 형성방법을 설명하기 위해 반도체 소자의 일부를 도시한 공정 단면도이다.1 is a partial cross-sectional view of a semiconductor device shown for explaining a semiconductor integrated circuit wiring structure of an embodiment according to the present invention, Figure 2 (a) to (e) is a semiconductor integrated circuit wiring of an embodiment according to the present invention It is a process sectional drawing which shows a part of semiconductor element in order to demonstrate the formation method.
제1도에 도시한 바와 같이 본 발명의 일실시예의 반도체 집적회로 배선구조는, 소스 및 드레인과 같은 불순물 확산영역(12)이 형성된 실리콘기판(11)과, 그 위에 절연층(13)으로 실리콘산화막이 형성되어 있다. 이 실리콘산화막에는 접속구멍이 형성되어 그를 통하여 실리콘기판(11)이 배선층(15a)과 접속하게 된다. 배선층은 제1전도층(15a-1), 배리어층(15a-2) 및 제2전도층(15a-3)으로 이루어진 샌드위치 형태로써 접속구멍 내에서도 샌드위치 구조를 띄고 있으며, 기판과 접하는 제1전도층(15a-1), 배리어층(15a-2)은 제1전도층인 알루미늄과 제2전도층(15a-3)이 반응을 일으키는 것을 효과적으로 방지하게 되며 Ti/TiN 등으로 형성된다. 제2전도층(15a-3)은 알루미늄, 구리, 은(Silver) 등의 저저항 물질을 적용할 수 있다.As shown in FIG. 1, the semiconductor integrated circuit wiring structure of an embodiment of the present invention includes a silicon substrate 11 having an impurity diffusion region 12 such as a source and a drain formed thereon, and a silicon as an insulating layer 13 thereon. An oxide film is formed. Connection holes are formed in the silicon oxide film so that the silicon substrate 11 is connected to the wiring layer 15a. The wiring layer has a sandwich structure composed of the first conductive layer 15a-1, the barrier layer 15a-2, and the second conductive layer 15a-3, and has a sandwich structure in the connection hole, and the first conductive layer is in contact with the substrate. The barrier layer 15a-2 effectively prevents the first conductive layer aluminum from reacting with the second conductive layer 15a-3 and is formed of Ti / TiN or the like. The second conductive layer 15a-3 may be made of a low resistance material such as aluminum, copper, or silver.
또한 제2도를 참조하여 본 발명의 일실시예의 반도체 집적회로 배선 형성방법을 설명하면, 우선 먼저 (a)와 같이 실리콘기판(11) 위에 소오스와 드레인 등의 불순물 확산영역(12)이 형성된 상태에서 실리콘산화막 등의 절연층(13)을 형성하고 실리콘기판(11)과 배선층의 접속을 위해 절연층(13)을 식각하여 접속구멍(14)을 형성한다.In addition, referring to FIG. 2, a method for forming a semiconductor integrated circuit wiring according to an exemplary embodiment of the present invention will first be described. First, as shown in FIG. The insulating layer 13, such as a silicon oxide film, is formed, and the insulating layer 13 is etched to form a connection hole 14 for the connection between the silicon substrate 11 and the wiring layer.
이어, (b)와 같이 제1전도층(15a-1)을 절연층(13)인 실리콘산화막 상의 전면에 증착형성하여 접속구멍(14) 내에서 실리콘기판(11)과 접속하도록 형성하는데, 플라즈마 화학기상증착법을 이용하여 알루미늄으로 형성하면 실리콘산화막 같은 절연막위에서도 전면 증착을 할 수 있다. 이때, 그 형성은 DMAH 또는 DMEAA 등의 유기금속화합물 소오스로 적용한 플라즈마 화학기상증착법으로 형성하며, 접속구멍에서 최소한의 단차피복성을 확보할 수 있는 두께, 바람직하기로는 1000Å 내지 2000Å 정도가 되도록 한다. 증착온도는 100℃ 내지 300℃ 바람직하기로는 100℃ 내지 200℃의 콜드 챔버(cold chamber)이고, 압력은 300 내지 800mtorr 정도이다. 특히 알루미늄의 소오스로써 DMEAA를 적용하는 경우에는 캐리어(Carrier) 가스로써 수소를 적용하는 것을 포함한다. 이때 플라즈마 전압은 5 내지 50W 바람직하게는 5 내지 15W가 되도록 한다. 알루미늄막은 분당 1500Å에서 4000Å까지의 증착속도를 갖도록 조절할 수 있으며 분당 약 2500Å의 속도로 성장시킨 경우에 증착막의 비저항이 약 5μΩ으로 나타났다. 한편 플라즈마 화학기상증착법으로 형성된 알루미늄막을 하부 전도층으로써 2000Å 이하의 두께로 충분히 얇게 형성하게 되면 접속구멍의 밑면에서 Si 기판과 접촉한다고 할지라도 Si과의 반응량을 극소화할 수 있게 된다.Subsequently, as shown in (b), the first conductive layer 15a-1 is deposited on the entire surface of the silicon oxide film, which is the insulating layer 13, to be formed so as to be connected to the silicon substrate 11 in the connection hole 14. When formed of aluminum using chemical vapor deposition, the entire surface can be deposited on an insulating film such as a silicon oxide film. At this time, the formation is formed by a plasma chemical vapor deposition method applied to an organometallic compound source such as DMAH or DMEAA, so as to have a thickness capable of securing a minimum step coverage in the connection hole, preferably 1000 kPa to 2000 kPa. The deposition temperature is 100 ° C. to 300 ° C., preferably a cold chamber at 100 ° C. to 200 ° C., and the pressure is about 300 to 800 mtorr. In particular, in the case of applying DMEAA as a source of aluminum, it includes applying hydrogen as a carrier gas. At this time, the plasma voltage is 5 to 50W, preferably 5 to 15W. The aluminum film can be controlled to have a deposition rate from 1500 kW to 4000 kW per minute, and the resistivity of the deposited film is about 5 μm when grown at a rate of about 2500 kW per minute. On the other hand, when the aluminum film formed by the plasma chemical vapor deposition method is formed sufficiently thin with a thickness of 2000 kPa or less as the lower conductive layer, the amount of reaction with Si can be minimized even if the bottom surface of the connection hole contacts the Si substrate.
계속하여, (c)와 같이 배리어층(15a-2)을 제1전도층(15a-1)과 마찬가지로 접속구멍(14)을 완전히 매립하지 않을 정도의 두께로 형성하는데, Ti/TiN 등의 전도성 물질을 스퍼터링 등의 물리적 증착법으로 100 내지 500Å의 두께로 형성한다. 이렇게 배리어층(15a-2)을 형성하면 배선의 저항을 더욱 낮추기 위하여 하부의 제1전도층(15a-1)을 알루미늄으로, 차후 형성될 상부 전도층인 제2전도층을 구리등과 같이 알루미늄과 반응성이 높은 저저항 물질을 적용할 때, 이 두 물질 사이에 반응이 일어나는 것을 효과적으로 방지할 수 있다. 또한 200Å 이하의 얇은 두께로 배리어층(15a-2)을 적용하면 후속되는 열공정에 의하여 제1전도층인 알루미늄막안으로 차후 형성되는 제2전도층으로 구리막을 적용했을 때, 구리 원자가 적정량 도우핑이 되도록 조절할 수 있게 된다. 이렇게 되면 알루미늄막을 구리가 포함된 합금막으로 변화시킬 수 있으므로 하부의 제1전도층(15a-1)인 알루미늄막의 일렉트로마이그레션(Electromigration) 특성을 개선할 수 있으며 실리콘과의 반응량도 감소시킬 수 있게 된다.Subsequently, as in (c), the barrier layer 15a-2 is formed to have a thickness such that the connection hole 14 is not completely filled like the first conductive layer 15a-1. The material is formed to a thickness of 100 to 500 kPa by physical vapor deposition such as sputtering. When the barrier layer 15a-2 is formed as described above, the lower first conductive layer 15a-1 is made of aluminum and the second conductive layer, which is to be formed later, is made of aluminum, such as copper, to further lower the resistance of the wiring. When applying a low-resistance material that is highly reactive, it is possible to effectively prevent a reaction between the two materials. In addition, when the barrier layer 15a-2 is applied with a thin thickness of 200 μs or less, an appropriate amount of copper atoms are doped when a copper film is applied to a second conductive layer which is subsequently formed into an aluminum film, which is a first conductive layer, by a subsequent thermal process. This can be adjusted to be. In this case, the aluminum film may be changed to an alloy film containing copper, thereby improving the electromigration characteristics of the aluminum film, which is the first conductive layer 15a-1, and may reduce the reaction amount with silicon. It becomes possible.
다음에, (d)와 같이 제2전도층(15a-3)을 배리어층(15a-2) 상에 상면이 비교적 평탄하도록 형성하는데, 스퍼터링과 같은 기존의 물리적 증착법 또는 저압화학기상증착법 등으로 형성한다. 제2전도층(15a-3)으로는 알루미늄을 비롯하여 구리나 은 및 그들의 화합물 등으로 된 저저항 물질을 적용할 수 있으며, 화학기상증착법(CVD)을 적용하여 알루미늄으로 형성하는 경우는 DMAH나 DMEAA 소오스를 이용하여 형성하며, 구리인 경우에는 (hfac)Cu(TMVS) 등의 소스를 이용하여 형성할 수 있다.Next, as shown in (d), the second conductive layer 15a-3 is formed on the barrier layer 15a-2 so that the upper surface is relatively flat, and is formed by conventional physical vapor deposition such as sputtering or low pressure chemical vapor deposition. do. As the second conductive layer 15a-3, a low-resistance material made of aluminum, copper, silver, or a compound thereof may be used. In the case of forming aluminum by chemical vapor deposition (CVD), DMAH or DMEAA may be used. It may be formed using a source, and in the case of copper, it may be formed using a source such as (hfac) Cu (TMVS).
다음에, (e)와 같이 감광막마스크(16)를 이용하여 제2전도층(15a-3), 배리어층(15a-2) 및 제1전도층(15a-1)을 차례로 식각하여 샌드위치 구조로 된 배선라인을 형성한다.Next, as shown in (e), the second conductive layer 15a-3, the barrier layer 15a-2 and the first conductive layer 15a-1 are sequentially etched using the photosensitive film mask 16 to form a sandwich structure. The wiring line is formed.
제3도는 본 발명의 다른 실시예의 반도체 집적회로 배선구조 및 그의 형성방법을 설명하기 위해 도시한 반도체 소자 일부의 단면도이다.3 is a cross-sectional view of a portion of a semiconductor device shown for explaining a semiconductor integrated circuit wiring structure and a method of forming the same according to another embodiment of the present invention.
제3도에 도시한 본 발명의 다른 실시예의 반도체 집적회로 배선은, 배선층(15b)의 하부층인 제1전도층(15b-1)의 두께를 접속구멍 반지름 이상으로 형성하므로써 제1전도층(15b-1)만으로 접속구멍을 채운, 샌드위치 형태의 배선구조이다. 이렇게 형성하므로써, 제1전도층(15b-1) 위에 배리어층(15b-2)을 형성할 때 배리어 물질의 인테그러티(Integrity)를 확보할 수 있게 된다. 도면부호(15b-3)은 제2전도층을 나타내고, 제1도 및 제2도와 같은 부위는 같은 부호를 사용하였다.In the semiconductor integrated circuit wiring according to another embodiment of the present invention shown in FIG. 3, the first conductive layer 15b is formed by forming the thickness of the first conductive layer 15b-1, which is the lower layer of the wiring layer 15b, over the connection hole radius. It is a sandwich-type wiring structure filled with connection holes only with -1). In this way, integrity of the barrier material can be ensured when the barrier layer 15b-2 is formed on the first conductive layer 15b-1. Reference numeral 15b-3 denotes a second conductive layer, and the same reference numerals are used for the same parts as those in FIGS. 1 and 2.
제4도는 본 발명의 또 다른 실시예의 반도체 집적회로 배선구조 및 그의 형성방법을 설명하기 위해 도시한 반도체 소자 일부의 단면도이다.4 is a cross-sectional view of a portion of a semiconductor device shown for explaining a semiconductor integrated circuit wiring structure and a method of forming the same according to another embodiment of the present invention.
배선층(15c)의 하부전도층인 제1전도층(15c-1)의 두께가 접속구멍을 매립할 정도로 두껍지 않을 경우에 배리어층(15c-2)의 두께를 두껍게 형성하므로써 접속구멍의 상부쪽에서 접속구멍을 폐쇄하고 그 표면에서 배리어 물질의 인테그러티(Integrity)를 확보할 수 있도록 한 구조와 방법에 관한 것으로써, 도면부호(15c-3)은 제2전도층을 나타내고, 제1도 및 제2도와 같은 부위는 같은 부호를 사용하였다.If the thickness of the first conductive layer 15c-1, which is the lower conductive layer of the wiring layer 15c, is not thick enough to fill the connection hole, the thickness of the barrier layer 15c-2 is formed so as to be connected from the upper side of the connection hole. A structure and method for closing the aperture and ensuring the integrity of the barrier material at its surface, wherein reference numeral 15c-3 denotes a second conductive layer, and FIGS. The same reference numerals are used for the same parts as 2 degrees.
상술한 바와 같이 본 발명은 콘택홀이나 비아(Via) 홀에 플라즈마 화학기상증착법으로 하부 전도층을 형성하므로써 단차피복성을 확보한 다음, 그 위에 불순물의 상호 확산을 막기 위한 배리어 금속층을 형성한 후, 저저항 물질로 된 상부 전도층을 형성하는 배리어 물질을 중간에 가지는 샌드위치 배선구조를 채택하므로써, 시준기(collimator)를 이용한 스퍼터링법이나 화학기상증착법 적용하지 않더라도 스퍼터링을 적용하여 인테그러티(intergrity)가 만족되는 배리어층을 형성하여 반도체 기판과 금속 배선층과의 반응을 억제할 뿐 아니라, 배선의 저항과 신뢰성을 개선할 수 있다.As described above, the present invention ensures step coverage by forming a lower conductive layer in a contact hole or via hole by plasma chemical vapor deposition, and thereafter forms a barrier metal layer thereon to prevent mutual diffusion of impurities thereon. By adopting sandwich wiring structure with intermediate barrier material forming upper conductive layer of low resistance material, sputtering is applied without sputtering or chemical vapor deposition using collimator. By forming a barrier layer satisfactory, the reaction between the semiconductor substrate and the metal wiring layer can be suppressed and the resistance and reliability of the wiring can be improved.
Claims (17)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950065783A KR100195330B1 (en) | 1995-12-29 | 1995-12-29 | Semiconductor ic wire and forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950065783A KR100195330B1 (en) | 1995-12-29 | 1995-12-29 | Semiconductor ic wire and forming method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970053559A KR970053559A (en) | 1997-07-31 |
| KR100195330B1 true KR100195330B1 (en) | 1999-06-15 |
Family
ID=19447162
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950065783A KR100195330B1 (en) | 1995-12-29 | 1995-12-29 | Semiconductor ic wire and forming method |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100195330B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10978384B2 (en) | 2018-08-31 | 2021-04-13 | Samsung Electronics Co., Ltd. | Integrated circuits including multi-layer conducting lines |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1042793A1 (en) | 1997-12-16 | 2000-10-11 | Infineon Technologies AG | Barrier layer for copper metallizing |
-
1995
- 1995-12-29 KR KR1019950065783A patent/KR100195330B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10978384B2 (en) | 2018-08-31 | 2021-04-13 | Samsung Electronics Co., Ltd. | Integrated circuits including multi-layer conducting lines |
| US11646261B2 (en) | 2018-08-31 | 2023-05-09 | Samsung Electronics Co., Ltd. | Integrated circuits including multi-layer conducting lines |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970053559A (en) | 1997-07-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR910007108B1 (en) | Intergrate semiconductor circuit comprising at least two metallization levels composed of aluminium or aluminium compounds and a method for the manufacture of same | |
| JP2832824B2 (en) | Method for forming wiring of semiconductor device | |
| US6013578A (en) | Method for forming a metal wiring structure of a semiconductor device | |
| US20020019127A1 (en) | Interconnect structure and method of making | |
| US20050023686A1 (en) | Multilayer diffusion barrier for copper interconnections | |
| EP0119497B1 (en) | Method of forming electrode/wiring layer | |
| US7186642B2 (en) | Low temperature nitride used as Cu barrier layer | |
| JPH03220751A (en) | Method of manufacturing inter-level contact and semiconductor structure | |
| JP4168397B2 (en) | Boron doped titanium nitride layer for high aspect ratio semiconductor devices | |
| US6093968A (en) | Germanium alloy contact to a silicon substrate | |
| KR100195330B1 (en) | Semiconductor ic wire and forming method | |
| US5641993A (en) | Semiconductor IC with multilayered Al wiring | |
| KR100289515B1 (en) | Barrier emtal layer and method of forming the same | |
| US5948705A (en) | Method of forming interconnection line | |
| JPH0283978A (en) | Semiconductor device | |
| KR100186509B1 (en) | Method of forming metal interconnector in semiconductor device | |
| KR960004078B1 (en) | Contact forming method by stacked thin layer structure | |
| KR100247643B1 (en) | A reaction chamber for forming metal layer and method for forming metal layer in semiconductor device using the same | |
| KR100197992B1 (en) | Forming method for metal wiring in semiconductor device | |
| KR100272662B1 (en) | Method of manufacturing metal wiring in semiconductor device | |
| KR100623594B1 (en) | Methodo for forming Al line of semiconductor device by using refractory metal liner | |
| JP2559829B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
| KR100223748B1 (en) | Method for forming multiple layer metal wiring in semiconductor device | |
| KR20030090872A (en) | Method for forming a semiconductor device's contact | |
| KR100196228B1 (en) | Interconnection manufacturing method of semiconductor integrated circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20090121 Year of fee payment: 11 |
|
| LAPS | Lapse due to unpaid annual fee |