KR100197992B1 - Forming method for metal wiring in semiconductor device - Google Patents
Forming method for metal wiring in semiconductor device Download PDFInfo
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- KR100197992B1 KR100197992B1 KR1019960024250A KR19960024250A KR100197992B1 KR 100197992 B1 KR100197992 B1 KR 100197992B1 KR 1019960024250 A KR1019960024250 A KR 1019960024250A KR 19960024250 A KR19960024250 A KR 19960024250A KR 100197992 B1 KR100197992 B1 KR 100197992B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
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Abstract
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 반도체 기판의 불순물 접합영역을 노출시키는 콘택홀을 형성하고, 전체표면 상부에 확산방지막을 형성한 다음, 상기 확산방지막 상부에 제1티타늄막/실리콘막/제2티타늄막의 적층구조를 증착하여 상기 콘택홀을 매립하고, 상기 제1티타늄막/실리콘막/제2티타늄막의 적층구조를 반응시키는 열처리공정으로 티타늄 실리사이드로 형성한 다음, 상기 하부절연층 상부구조를 전면식각하여 콘택플러그를 형성하고, 전체표면상부에 금속배선을 형성하여 상기 콘택홀의 내부를 CVD 방법을 이용한 티타늄 실리사이드로 형성함으로써 금속배선의 동작특성과 단차피복비를 향상시켜 반도체소자의 특성 및 신뢰성을 향상시키며 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for forming a metal wiring of a semiconductor device, comprising forming a contact hole exposing an impurity junction region of a semiconductor substrate, forming a diffusion barrier over the entire surface, and then forming a first titanium film / Forming a layer of titanium silicide by depositing a stacked structure of a silicon film / second titanium film to fill the contact hole, and reacting the stacked structure of the first titanium film / silicon film / second titanium film to form titanium silicide; A contact plug is formed by etching the upper surface of the layer, and metal wiring is formed on the entire surface, and the inside of the contact hole is formed of titanium silicide using a CVD method to improve the operation characteristics and the step coverage ratio of the metal wiring. It is a technology that improves characteristics and reliability, and thereby enables high integration of semiconductor devices.
Description
제1도는 종래기술의 제1실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.1 is a cross-sectional view showing a metal wiring formation method of a semiconductor device according to a first embodiment of the prior art.
제2도는 종래기술의 제2실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.2 is a cross-sectional view showing a metal wiring formation method of a semiconductor device according to a second embodiment of the prior art.
제3도는 종래기술의 제3실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.3 is a cross-sectional view showing a metal wiring forming method of a semiconductor device according to a third embodiment of the prior art.
제4a도 내지 제4f도는 본 발명의 제1실시예에 반도체소자의 금속배선 형성방법을 도시한 단면도.4A to 4F are cross-sectional views showing a metal wiring forming method of a semiconductor device in a first embodiment of the present invention.
제5도는 본 발명의 제2실시예에 반도체소자의 금속배선 형성방법을 도시한 단면도.5 is a cross-sectional view showing a metal wiring formation method of a semiconductor device in a second embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11, 41, 61, 71 : 반도체기판 13, 43, 63, 73 : 불순물 접합영역11, 41, 61, 71: semiconductor substrate 13, 43, 63, 73: impurity junction region
15, 45, 65, 75 : 하부절연층 17, 47, 67, 77 : 콘택홀15, 45, 65, 75: lower insulating layer 17, 47, 67, 77: contact hole
19 : 티타늄막 / 티타늄질화막의 적층구조19: laminated structure of titanium film / titanium nitride film
21 : 제1티타늄막 23 : 실리콘막21: first titanium film 23: silicon film
25 : 제2티타늄막 27 : 티타늄 실리사이드25: second titanium film 27: titanium silicide
29 : 미반응 티타늄막 31, 35, 49, 81 : 알루미늄합금29: unreacted titanium film 31, 35, 49, 81: aluminum alloy
33 : TiAlxSiy69, 79 : 텅스텐막33: TiAl x Si y 69, 79: tungsten film
51 : 보이드51: void
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 특히 비저항이 낮은 티타늄 실리사이드(TiSi2)를 이용하여 콘택홀을 매립함으로써 소자의 동작특성을 향상시키고, 콘택저항을 감소시켜 동작특성이 우수한 금속배선을 형성하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device. In particular, the contact hole is filled using titanium silicide (TiSi 2 ) having a low specific resistance to improve the operation characteristics of the device and to reduce the contact resistance, thereby providing excellent metal characteristics. It relates to a technique for forming a wiring.
일반적으로, 소자간이나 소자와 외부회로 사이를 전기적으로 접속시키기 위한 반도체소자의 배선은, 배선을 위한 소정의 콘택홀 및 비아홀을 배선재료로 매립하여 배선층을 형성하고 후속공정을 거쳐 이루어지며, 낮은 저항을 필요로 하는 곳에는 금속배선을 사용한다.In general, the wiring of a semiconductor device for electrically connecting between devices or between an element and an external circuit is made through a subsequent process by filling a predetermined contact hole and via hole for wiring with a wiring material and forming a wiring layer. Metal wiring is used where resistance is required.
상기 금속배선은 알루미늄(A1)에 소량의 실리콘이나 구리가 포함되거나 실리콘과 구리가 모두 포함되어 비저항이 낮으면서 가공성이 우수한 알루미늄합금을 배선재료로 하여 물리기상증착금속배선 형성방법을 도시한 단면도.(Physical Vapor Deposition, 이하에서 PVD 라 함) 방법의 스퍼터링으로 상기의 콘택홀 및 비아홀을 매립하는 방법으로 형성한다.The metal wiring is a cross-sectional view showing a method of forming a physical vapor deposition metal wiring using a small amount of silicon or copper in aluminum (A1), or a silicon alloy containing both silicon and copper as a wiring material with low resistivity and excellent workability. (Physical Vapor Deposition, hereinafter referred to as PVD) is formed by the method of embedding the above-mentioned contact hole and via hole by sputtering.
또한, 단차피복비가 우수한 텅스텐(W)을 이용하여 금속배선을 형성하기도 한다.In addition, metal wiring may be formed using tungsten (W) having excellent step coverage ratio.
제1도는 종래기술의 제1실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도로서, 상기 금속배선을 알루미늄합금으로 형성하는 방법을 도시한다.1 is a cross-sectional view showing a method for forming metal wirings of a semiconductor device according to a first embodiment of the prior art, which shows a method for forming the metal wirings from an aluminum alloy.
먼저, 반도체기판(41)에 불순물 접합영역(43)을 형성하고, 전체표면상부를 평탄화시키는 하부절연층(45)을 형성한다. 이때, 상기 하부절연층(45)은 상기 반도체기판(41) 상부에 소자분리절연막(도시안됨), 워드라인(도시안됨), 비트라인(도시안됨) 또는 캐패시터(도시안됨)를 형성하고 비.피.에스.지.(Boro Phospho Silicate Glass, 이하에서 BPSG 라 함)와 같이 유동성이 우수한 절연물질로 평탄화시켜 형성한다.First, an impurity junction region 43 is formed in the semiconductor substrate 41, and a lower insulating layer 45 is formed to planarize the entire upper surface. In this case, the lower insulating layer 45 forms an isolation layer (not shown), a word line (not shown), a bit line (not shown), or a capacitor (not shown) on the semiconductor substrate 41. It is formed by planarizing it with an insulating material having excellent fluidity, such as Bos Phospho Silicate Glass (hereinafter referred to as BPSG).
그 다음에, 콘택마스크(도시안됨)를 이용한 식각공정으로 상기 하부절연층(45)을 식각하여 상기 불순물 접합영역(43)을 노출시키는 콘택홀(47)을 형성한다.Next, the lower insulating layer 45 is etched by an etching process using a contact mask (not shown) to form a contact hole 47 exposing the impurity junction region 43.
그리고, 전체표면상부에 알루미늄합금(49)을 물리기상증착(Physical Vapor Deposition, 이하에서 PVD 라 함) 방법으로 증착하여 금속배선을 형성한다.Then, the aluminum alloy 49 is deposited on the entire surface by physical vapor deposition (hereinafter referred to as PVD) to form metal wiring.
그러나, 반도체소자가 고집적화됨에따라 상기 콘택홀(47)의 크기가 작아져 상기 알루미늄합금(49)이 상기 콘택홀(47)을 완전히 매립할 수 없어 보이드(51)와 같은 단점을 발생시킨다.However, as the semiconductor device is highly integrated, the size of the contact hole 47 decreases, which causes the aluminum alloy 49 to not completely fill the contact hole 47, which causes disadvantages such as the void 51.
이로인하여, 접합누설전류를 발생시키고 소자의 동작특성을 저하시켜 반도체소자의 특성 및 신뢰성을 저하시키고 그에 따른 반도체소자의 고집적화를 어렵게 하는 문제점이 있다. (제1도)As a result, there is a problem in that the junction leakage current is generated and the operation characteristics of the device are lowered, thereby deteriorating the characteristics and reliability of the semiconductor device and consequently making the integration of the semiconductor device difficult. (Figure 1)
제2도는 종래기술의 제2실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도로서, 상기 금속배선을 텅스텐막으로 형성하는 방법을 도시한다.2 is a cross-sectional view showing a method for forming metal wirings of a semiconductor device according to a second embodiment of the prior art, which shows a method for forming the metal wirings with a tungsten film.
먼저, 반도체기판(61)에 불순물 접합영역(63)을 형성하고, 전체표면상부를 평탄화시키는 하부절연층(65)을 형성한다. 이때, 상기 하부절연층(65)은 상기 반도체기판(61) 상부에 소자분리절연막(도시안됨), 워드라인(도시안됨), 비트라인(도시안됨) 또는 캐패시터(도시안됨)를 형성하고 BPSG와 같이 유동성이 우수한 절연물질로 평탄화시켜 형성한다.First, an impurity junction region 63 is formed in the semiconductor substrate 61, and a lower insulating layer 65 is formed to planarize the entire upper surface. In this case, the lower insulating layer 65 may form an isolation layer (not shown), a word line (not shown), a bit line (not shown), or a capacitor (not shown) on the semiconductor substrate 61. It is formed by flattening with an insulating material having excellent fluidity.
그 다음에, 콘택마스크(도시안됨)를 이용한 식각공정으로 상기 하부절연층(65)을 식각하여 상기 불순물 접합영역(63)을 노출시키는 콘택홀(67)을 형성한다.Next, the lower insulating layer 65 is etched by an etching process using a contact mask (not shown) to form a contact hole 67 exposing the impurity junction region 63.
그리고, 전체표면상부에 텅스텐막(69)을 화학기상증착(Chemical Vapor Deposition, 이하에서 CVD 라 함) 방법으로 증착하여 금속배선을 형성한다.Then, a tungsten film 69 is deposited on the entire surface by chemical vapor deposition (hereinafter referred to as CVD) to form metal wiring.
그러나, 상기 텅스텐막(69)은 상기 제1실시예에 사용된 알루미늄 합금보다 비저항이 3∼4 정도로 크기 때문에 금속배선의 동작특성을 느리게 하여 반도체 소자의 특성을 저하시키는 문제점이 있다. (제2도)However, since the tungsten film 69 has a specific resistance of about 3 to 4 larger than that of the aluminum alloy used in the first embodiment, there is a problem in that the operation characteristics of the metal wiring are slowed and the characteristics of the semiconductor device are lowered. (Figure 2)
제3도는 종래기술의 제3실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도로서, 텅스텐막으로 플러그를 형성하고 그 상부에 알루미늄합금을 증착하여 금속배선을 형성하는 방법을 도시한다.3 is a cross-sectional view illustrating a method of forming metal wirings of a semiconductor device according to a third embodiment of the prior art, and illustrates a method of forming a metal wiring by forming a plug with a tungsten film and depositing an aluminum alloy thereon.
먼저, 반도체기판(71)에 불순물 접합영역(73)을 형성하고, 전체표면상부를 평탄화시키는 하부절연층(75)을 형성한다. 이때, 상기 하부절연층(75)은 상기 반도체기판(71) 상부에 소자분리절연막(도시안됨),워드라인(도시안됨), 비트라인(도시안됨) 또는 캐패시터(도시안됨)를 형성하고 비.피.에스.지.(Boro Phospho Silicate Glass, 이하에서 BPSG 라 함)와 같이 유동성이 우수한 절연물질로 평탄화시켜 형성한다.First, an impurity junction region 73 is formed in the semiconductor substrate 71, and a lower insulating layer 75 is formed to planarize the entire upper surface. In this case, the lower insulating layer 75 forms an isolation layer (not shown), a word line (not shown), a bit line (not shown), or a capacitor (not shown) on the semiconductor substrate 71. It is formed by planarizing it with an insulating material having excellent fluidity, such as Bos Phospho Silicate Glass (hereinafter referred to as BPSG).
그 다음에, 콘택마스크(도시안됨)를 이용한 식각공정으로 상기 하부절연층(75)을 식각하여 상기 불순물 접합영역(73)을 노출시키는 콘택홀(77)을 형성한다.Subsequently, the lower insulating layer 75 is etched by an etching process using a contact mask (not shown) to form a contact hole 77 exposing the impurity junction region 73.
그리고, 전체표면상부에 텅스텐막(79)을 화학기상증착(Chemical Vapor Deposition, 이하에서 CVD 라 함) 방법으로 증착하여 상기 콘택홀(77)을 매립한다.The contact hole 77 is buried by depositing a tungsten film 79 on the entire surface by chemical vapor deposition (hereinafter, referred to as CVD).
그 다음에, 상기 텅스텐막(79)은 전면식각하여 상기 콘택홀(77)에만 상기 텅스텐막(77)을 남겨 텅스텐막(79) 플러그를 형성한다.Next, the tungsten film 79 is etched entirely to leave the tungsten film 77 in the contact hole 77 to form a tungsten film 79 plug.
그리고, 전체표면상부에 알루미늄합금(81)을 소정두께 증착하여 금속배선을 형성한다.Then, a predetermined thickness is deposited on the entire surface of the aluminum alloy 81 to form metal wiring.
상기 제3실시예에 따른 금속배선 형성방법은, 상기 제2실시예보다 동작특성이 증가하지만, 공정이 복잡하고 상기 콘택홀 내부에서 상기 텅스텐막 플러그에 의한 저항이 증가되어 전체적인 동작특성이 고집적화된 반도체소자를 만족시키지 못하는 문제점이 있다.In the method for forming a metal wiring according to the third embodiment, the operating characteristics are increased compared to the second embodiment, but the process is complicated and the resistance by the tungsten film plug is increased in the contact hole, thereby increasing the overall operating characteristics. There is a problem that does not satisfy the semiconductor device.
따라서, 상기한 문제점들을 해결하기 위하여, 단차피복비가 우수한 CVD 방법을 이용하여 콘텍홀 내부를 티타늄 실리사이드로 매립함으로써 금속배선의 동작특성을 향상시켜 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problems, by using the CVD method having excellent step coverage ratio, the inside of the contact hole is filled with titanium silicide to improve the operation characteristics of the metal wiring, thereby improving the characteristics and reliability of the semiconductor device and thereby It is an object of the present invention to provide a method for forming metal wirings in a semiconductor device that enables high integration.
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 금속배선 형성방법의 제1특징은, 반도체기판의 불순물 접합영역을 노출시키는 콘택홀을 형성하는 공정과, 전체표면상부에 확산방지막을 형성하는 공정과, 상기 확산방지막 상부에 제1티타늄막/실리콘막/제2티타늄막의 적층구조를 증착하여 상기 콘택홀을 매립하는 공정과, 상기 제1티타늄막/실리콘막/제2티타늄막의 적층구조를 반응시키는 열처리공정으로 티타늄 실리사이드를 형성하는 공정과, 상기 하부절연층 상부구조를 전면식각하여 콘택플러그를 형성하는 공정과, 전체표면상부에 금속배선을 형성하는 공정을 포함하는 것이다.In order to achieve the above object, a first aspect of the method for forming a metal wiring of a semiconductor device according to the present invention is to form a contact hole for exposing an impurity junction region of a semiconductor substrate, and to form a diffusion barrier film over the entire surface And depositing the contact hole by depositing a stacked structure of a first titanium film / silicon film / a second titanium film on the diffusion barrier and reacting the stacked structure of the first titanium film / silicon film / second titanium film. Forming a titanium silicide by a heat treatment process, forming a contact plug by etching the upper structure of the lower insulating layer and forming a metal wiring on the entire surface.
또한, 본 발명에 따른 반도체소자의 금속배선 형성방법의 제2 특징은, 반도체기판의 불순물 접합영역을 노출시키는 콘택홀을 형성하는 공정과, 전체표면상부에 확산방지막을 형성하는 공정과, 상기 확산방지막 상부에 제1티타늄막/실리콘막/제2티타늄막의 적층구조를 증착하여 상기 콘택홀을 매립하는 공정과, 상기 제1티타늄막/실리콘막/제2티타늄막의 적층구조를 반응시키는 열처리공정으로 티타늄 실리사이드를 형성하는 공정과, 전체표면상부에 금속배선물질인 알루미늄합금을 고온에서 증착하여 상기 티타늄 실리사이드 형성시 유발되는 미반응 티타늄막을 TiAlxSiy으로 형성하는 공정을 포함하는 것이다.In addition, a second aspect of the method for forming metal wirings of a semiconductor device according to the present invention includes the steps of forming a contact hole exposing an impurity junction region of a semiconductor substrate, forming a diffusion barrier on the entire surface, and the diffusion Depositing the stacked structure of the first titanium film / silicon film / second titanium film on the prevention layer to fill the contact hole; Forming a titanium silicide; and forming an unreacted titanium film formed of TiAl x Si y by depositing an aluminum alloy, which is a metal wiring material, on the entire surface at a high temperature.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제4a도 내지 제4f도는 본 발명에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도이다.4A through 4F are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention.
먼저, 반도체기판(11)에 불순물 접합영역(13)을 형성하고, 전체표면상부를 평탄화시키는 하부절연층(15)을 형성한다. 이때, 상기 하부절연층(15)은 상기 반도체기판(11) 상부에 소자분리절연막(도시안됨),워드라인(도시안됨), 비트라인(도시안됨) 또는 캐패시터(도시안됨)를 형성하고 비.피.에스.지.(Boro Phospho Silicate Glass, 이하에서 BPSG 라 함)와 같이 유동성이 우수한 절연물질로 평탄화시켜 형성한다.First, the impurity junction region 13 is formed in the semiconductor substrate 11, and the lower insulating layer 15 is formed to planarize the entire upper surface. In this case, the lower insulating layer 15 forms an isolation layer (not shown), a word line (not shown), a bit line (not shown), or a capacitor (not shown) on the semiconductor substrate 11. It is formed by planarizing it with an insulating material having excellent fluidity, such as Bos Phospho Silicate Glass (hereinafter referred to as BPSG).
그 다음에, 콘택마스크(도시안됨)를 이용한 식각공정으로 상기 하부절연층(15)을 식각하여 상기 불순물 접합영역(13)을 노출시키는 콘택홀(17)을 형성한다. (제4a도)Next, the lower insulating layer 15 is etched by an etching process using a contact mask (not shown) to form a contact hole 17 exposing the impurity junction region 13. (Figure 4a)
그리고, 전체표면상부에 티타늄막/티타늄질화막의 적층구조(19)로 형성된 확산방지막을 형성한다.Then, a diffusion barrier film formed of a laminated structure 19 of titanium film / titanium nitride film is formed on the entire surface.
여기서, 상기 티타늄막은 후속공정에서 반도체기판(11)과 반응하여 일정두께의 티타늄 실리사이드막을 형성함으로써 저항을 낮추기 위한 것이다.Here, the titanium film is to lower the resistance by forming a titanium silicide film having a predetermined thickness by reacting with the semiconductor substrate 11 in a subsequent step.
그 다음에, 상기 티타늄막/티타늄질화막의 적층구조(19)의 확산방지능력을 증가시키기 위하여 산소를 주입함으로써 상기 티타늄질화막을 티타늄산화질화막(도시안됨)으로 형성한다. (제4b도)Then, the titanium nitride film is formed as a titanium oxynitride film (not shown) by injecting oxygen to increase the diffusion preventing ability of the laminated film 19 of the titanium film / titanium nitride film. (Figure 4b)
그 다음에, 전체표면상부에 제1티타늄막(21), 실리콘막(23) 및 제2티타늄막(25)을 순차적으로 각각 일정두께 증착하되, CVD 방법으로 증착하여 상기 콘택홀(17)을 매립한다.Subsequently, the first titanium film 21, the silicon film 23 and the second titanium film 25 are sequentially deposited on the entire surface, respectively, and the contact holes 17 are deposited by CVD. Landfill
이때, 상기 제1,2티타늄막(21, 25)은 PVD 방법으로 형성할 수도 있다. (제4c도)In this case, the first and second titanium films 21 and 25 may be formed by a PVD method. (Figure 4c)
그 다음에, 600∼850℃ 정도의 온도에서 열처리공정을 실시하여 상기 제1,2티타늄막(21, 25)과 상기 실리콘막(23)을 반응시킴으로써 티타늄 실리사이드(27)을 형성한다.Next, a titanium silicide 27 is formed by reacting the first and second titanium films 21 and 25 with the silicon film 23 by performing a heat treatment at a temperature of about 600 to 850 ° C.
이때, 상기 열처리공정은 급속열처리(Rapid Thermal processing, 이하에서 RTP 라 함) 공정으로 실시하거나, 일반적인 열처리 반응로에서 실시한다.At this time, the heat treatment step is carried out in a rapid thermal processing (hereinafter referred to as RTP) process, or in a general heat treatment reactor.
그리고, 상기 제2티타늄막(25)의 일부는 반응하지 않은 상태인 미반응 티타늄막(29)을 형성한다. (제4d도)A portion of the second titanium film 25 forms an unreacted titanium film 29 in an unreacted state. (Figure 4d)
그 다음에, 전면식각공정으로 상기 미반응 티타늄막(29), 티타늄 실리사이드(27) 및 티타늄막/티타늄질화막의 적층구조(19)을 식각하여 상기 콘택홀(17)을 매립하는 콘택플러그를 형성한다.Next, a contact plug for filling the contact hole 17 is formed by etching the unreacted titanium film 29, the titanium silicide 27, and the stacked structure 19 of the titanium film / titanium nitride film by a front etching process. do.
여기서, 상기 콘택플러그는 티타늄막/티타늄질화막의 적층구조(19)와 티타늄 실리사이드(27)로 형성한다. (제4e도)Here, the contact plug is formed of a stacked structure 19 and a titanium silicide 27 of a titanium film / titanium nitride film. (Figure 4e)
그 다음에, 전체표면상부에 알루미늄합금(31)을 소정두께 형성하여 금속배선을 형성한다.Next, the aluminum alloy 31 is formed to a predetermined thickness on the entire surface to form metal wiring.
이때, 상기 알루미늄합금(31)은 PVD 방법으로 형성한다. (제4f도)At this time, the aluminum alloy 31 is formed by the PVD method. (Figure 4f)
제5도는 본 발명의 제2실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도이다.5 is a cross-sectional view illustrating a metal wiring forming method of a semiconductor device in accordance with a second embodiment of the present invention.
먼저, 제4a도 내지 제4d도의 공정을 실시한다.First, the process of FIG. 4A-FIG. 4D is implemented.
그리고, 상기 미반응 티타늄막(29) 상부에 알루미늄합금(35)을 증착하여 금속배선을 형성하되, 상기 알루미늄합금(35)의 증착온도를 400∼550℃ 정도로 함으로써 상기 미반응 티타늄막(29)을 TiAlxSiy으로 형성하여 금속배선의 저항을 감소시키며, 금속배선의 일렉트로-마이그레이션(electro-migration) 특성을 향상시킨다.In addition, the metal alloy is formed by depositing the aluminum alloy 35 on the unreacted titanium film 29, but the deposition temperature of the aluminum alloy 35 is about 400 to 550 ° C. so that the unreacted titanium film 29 is removed. Is formed of TiAl x Si y to reduce the resistance of the metal wiring and to improve the electro-migration characteristics of the metal wiring.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 금속배선 형성방법은, 비저항이 낮은 티타늄 실리사이드를 이용하여 금속배선을 형성하되, CVD 방법으로 형성함으로써 금속배선의 동작특성을 향상시키고 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 잇점이 있다.As described above, in the method of forming the metal wiring of the semiconductor device according to the present invention, the metal wiring is formed by using titanium silicide having a low specific resistance, but by the CVD method, the operation characteristics of the metal wiring are improved, and the characteristics of the semiconductor device and There is an advantage to improve the reliability and thereby high integration of the semiconductor device.
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