KR0156126B1 - Formation method of contact hole in semiconductor device - Google Patents
Formation method of contact hole in semiconductor device Download PDFInfo
- Publication number
- KR0156126B1 KR0156126B1 KR1019940026828A KR19940026828A KR0156126B1 KR 0156126 B1 KR0156126 B1 KR 0156126B1 KR 1019940026828 A KR1019940026828 A KR 1019940026828A KR 19940026828 A KR19940026828 A KR 19940026828A KR 0156126 B1 KR0156126 B1 KR 0156126B1
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- Prior art keywords
- forming
- contact hole
- contact
- plug
- insulating film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
Abstract
본 발명은 반도체장치의 콘택형성방법에 관한 것으로, 플러그(plug)형성공정의 피복단차효과를 개선시키기 위한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact in a semiconductor device, and to improve the coating step effect of a plug forming process.
본 발명은 실리콘기판상에 형성된 콘택홀을 포함하는 절연막 전면에 밀착층을 형성하는 단계와, 상기 콘택홀 측면에 측벽절연막을 형성하는 단계, 상기 콘택홀 내부를 포함한 기판 전면에 장벽층을 형성하는 단계, 열처리공정을 행하여 상기 실리콘기판과 기판과 접촉된 부분의 밀착층을 반응시켜 실리사이드를 형성하는 단계, 상기 콘택홀 내부에 금속을 매립시켜 플러그를 형성하는 단계로 이루어지는 반도체장치의 콘택형성방법을 제공함으로써 플러그형성시의 오버행 및 키홀등의 생성을 방지할 수 있도록 한다.The present invention provides a method for forming an adhesion layer on an entire surface of an insulating film including a contact hole formed on a silicon substrate, forming a sidewall insulating film on a side of the contact hole, and forming a barrier layer on an entire surface of the substrate including an inside of the contact hole. And forming a silicide by reacting the adhesion layer between the silicon substrate and the portion in contact with the substrate by performing a heat treatment, and forming a plug by embedding a metal in the contact hole. By providing it, it is possible to prevent the generation of overhangs, keyholes, and the like during plug formation.
Description
제1도는 종래의 반도체장치의 콘택형성방법을 도시한 공정순서도.1 is a process flowchart showing a contact forming method of a conventional semiconductor device.
제2도는 본 발명의 반도체장치의 콘택형성방법을 도시한 공정순서도.2 is a process flowchart showing a contact forming method of a semiconductor device of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘기판 2 : 산화막1 silicon substrate 2 oxide film
3 : 밀착층 4 : 장벽층3: adhesion layer 4: barrier layer
5 : 플러그 7 : 절연막5: plug 7: insulating film
7A : 측벽절연막 8 : 실리사이드7A: sidewall insulating film 8: silicide
본 발명은 반도체장치의 콘택형성방법에 관한 것으로, 특히 플러그(plug)형성공정의 피복단차효과를 개선한 콘택형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contact forming method of a semiconductor device, and more particularly, to a contact forming method having an improved covering step effect in a plug forming step.
반도체장치 제조공정중 종래의 금속과 실리콘의 콘택형성방법을 제1도를 참조하여 설명하면 다음과 같다.Referring to FIG. 1, a conventional method for forming a contact between a metal and silicon in a semiconductor device manufacturing process is as follows.
먼저, 제1도(a)에 도시된 바와 같이 실리콘기판(1)상에 절연막으로서, 산화막(2)을 형성하고 이를 선택적으로 식각하여 콘택홀을 형성한 다음, 콘택홀을 포함한 산화막(2) 전면에 접촉저항을 감소시키는 역할을 하는 한편 밀착층(glue layer)(3)으로 사용되는 Ti박막을 스퍼터링에 의해 형성하고, 이위에 확산을 방지하기 위한 장벽층(4)으로서, TiN막을 스퍼터링에 의해 형성한다.First, as shown in FIG. 1A, an oxide film 2 is formed on the silicon substrate 1 as an insulating film and then selectively etched to form a contact hole, and then an oxide film 2 including the contact hole. While reducing the contact resistance on the entire surface, the Ti thin film used as the glue layer 3 is formed by sputtering, and as a barrier layer 4 for preventing diffusion thereon, the TiN film is sputtered. By forming.
다음에 제1도(b)에 도시된 바와 같이 CVD(Chemical Vapor Deposition)방법에 의해 텅스텐(5)을 상기 결과물 전면에 블랭킷(blanket) 증착한 후, 제1도(c)에 도시된 바와 같이 텅스텐을 에치백하여 콘택홀내에만 남긴다.Next, a blanket was deposited on the entire surface of the resultant by CVD (Chemical Vapor Deposition) method as shown in FIG. 1 (b), and then as shown in FIG. 1 (c). The tungsten is etched back leaving only in the contact hole.
상기 종래기술에 있어서는 Ti막, TiN막을 형성하는데 주로 스퍼터링방법을 사용하기 때문에 콘택홀 상부에는 두껍게 형성되고 하부로 갈수록 박막의 두께가 얇아지는 오버행(overhang)이 발생하게 된다.In the prior art, since the sputtering method is mainly used to form the Ti film and the TiN film, an overhang is formed in the upper portion of the contact hole and becomes thinner toward the lower portion.
또한, 소자의 집적도가 증가함에 따라 콘택홀의 애스팩트비(aspect ratio)가 증가하므로 경사진 측벽을 갖는 콘택홀 형성이 불가능하게 되어 제1도에 도시된 바와 같은 수직측벽을 갖는 콘택홀 형성만이 가능하게 된다. 이로 인해 플러그 형성을 위한 텅스텐 증착시 제1도(b)에 도시된 바와 같은 키홀(key hole)(6)이 발생하게 되며, 텅스텐의 에치백공정시에 제1도(c)와 같은 키홀이 노출되게 되어 이후의 배선공정과 소자의 신뢰성에 나쁜 영향을 미치게 된다. 이와 같은 키홀의 생성을 방지하기 위해 콘택홀을 형성한 후 그 측면에 측벽을 형성하여 스텝커버리지를 낮추기도 하나, 이 경우에는 금속과 실리콘과의 접촉면적이 감소되므로 접촉저항이 증가하는 문제를 유발시키게 된다.In addition, the aspect ratio of the contact hole increases as the degree of integration of the device increases, making it impossible to form a contact hole having an inclined sidewall. It becomes possible. This results in a key hole 6 as shown in FIG. 1 (b) during tungsten deposition for plug formation, and a key hole as shown in FIG. 1 (c) during tungsten etch back process. The exposure will adversely affect subsequent wiring processes and device reliability. In order to prevent the formation of such a keyhole, the contact hole is formed and then sidewalls are formed on the side to reduce step coverage, but in this case, the contact area between the metal and silicon is reduced, resulting in an increase in contact resistance. Let's go.
본 발명은 상술한 문제를 해결하기 위한 것으로, 플러그의 키홀생성을 억제할 수 있는 반도체장치의 콘택형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object thereof is to provide a method for forming a contact of a semiconductor device which can suppress key hole generation of a plug.
상기 목적을 달성하기 위한 본 발명의 반도체장치의 콘택형성방법은 실리콘기판상에 형성된 콘택홀을 포함하는 절연막 전면에 밀착층을 형성하는 단계와, 상기 콘택홀 측면에 측벽절연막을 형성하는 단계, 상기 콘택홀 내부를 포함한 기판 전면에 장벽층을 형성하는 단계, 열처리공정을 행하여 상기 실리콘기판과 기판과 접촉된 부분의 밀착층을 반응시켜 실리사이드를 형성하는 단계, 상기 콘택홀 내부에 금속을 매립시켜 플러그를 형성하는 단계로 이루어진다.The contact forming method of the semiconductor device of the present invention for achieving the above object is to form a contact layer on the entire surface of the insulating film including a contact hole formed on a silicon substrate, forming a sidewall insulating film on the side of the contact hole, Forming a barrier layer on the entire surface of the substrate including the contact hole; and performing a heat treatment process to react the adhesion layer between the silicon substrate and the part in contact with the substrate to form silicide, and to embed a metal into the contact hole. Forming a step.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2도에 본 발명에 의한 반도체장치의 콘택형성방법을 공정순서에 따라 도시하였다. 먼저, 제2도(a)에 도시된 바와 같이 실리콘기판(1)상에 절연막으로서, 예컨대 산화막(2)을 형성하고 이를 선택적으로 식각하여 기판의 소정부분을 노출시키는 콘택홀을 형성한 후, 콘택홀을 포함한 산화막(2) 전면에 접촉저항을 감소시키는 역할을 하는 한편 밀착층(3)의 역할을 하는 박막으로서, 예컨데 Ti박막을 형성한다. Ti박막이외에도 Co, W, Mo등을 이용할 수 있다.2 shows a method for forming a contact of a semiconductor device according to the present invention according to the process sequence. First, as shown in FIG. 2 (a), as an insulating film, for example, an oxide film 2 is formed on the silicon substrate 1 and selectively etched to form a contact hole for exposing a predetermined portion of the substrate. As a thin film which serves to reduce the contact resistance on the entire surface of the oxide film 2 including the contact hole and serves as the adhesion layer 3, for example, a Ti thin film is formed. Co, W, Mo, etc. can be used besides Ti thin film.
이어서 제2도(b)에 도시된 바와 같이 상기 Ti박막상에 절연막(7)으로서, 예컨대 산화막을 형성한 후, 이를 예치백하여 제2도(c)에 도시된 바와 같이 콘택홀 측면에 측벽절연막(7A)을 형성한다.Subsequently, as shown in FIG. 2 (b), an oxide film, for example, an oxide film is formed on the Ti thin film, and then deposited back into the sidewalls on the side of the contact hole as shown in FIG. The insulating film 7A is formed.
다음에 제2도(d)에 도시된 바와 같이 장벽층(4)으로서, 예컨대 TiN 또는 TiNx(0＜x＜1)등의 내화금속질화막을 콘택홀의 바닥부분에서 100-1000Å두께가 되도록 형성한 후, 열처리공정을 행하여 실리콘기판과 기판과 접촉된 부분의 Ti박막을 반응시켜 실리사이드(8)를 형성한다.Next, as shown in FIG. 2 (d), as the barrier layer 4, a refractory metal nitride film such as TiN or TiNx (0 <x <1) is formed so as to have a thickness of 100-1000 kPa at the bottom of the contact hole. Then, a heat treatment step is performed to react the silicon substrate with the Ti thin film in contact with the substrate to form the silicide 8.
이어서 제2도(e)에 도시된 바와 같이 기판 전면에 도전층으로서, 예컨대 텅스텐을 상기 콘택홀이 매립되도록 블랭킷(blanket) 증착한 후, 제2도(f)에 도시된 바와 같이 에치백하여 텅스텐 플러그(5)를 형성한다. 이때, 텅스텐 대신 알루미늄 플로우 공정을 이용하여 플러그를 형성하는 것도 가능하다.Subsequently, as shown in FIG. 2E, a blanket is deposited on the entire surface of the substrate as a conductive layer, for example tungsten, and then etched back as shown in FIG. The tungsten plug 5 is formed. In this case, it is also possible to form a plug by using an aluminum flow process instead of tungsten.
상기 절연막측벽위에 형성되는 TiN막은 확산 장벽층 및 플러그 형성을 위한 알루미늄 플로우공정에서의 밀착층으로 작용한다.The TiN film formed on the insulating film side wall serves as an adhesion layer in the aluminum flow process for forming the diffusion barrier layer and the plug.
상기와 같은 본 발명은 그 측면에 절연막측벽이 형성된 콘택홀에 플러그 형성을 위한 금속이 증착되므로 절연막측벽으로 인해 금속층의 스텝커버리지가 향상되어 오버행 및 키홀등이 생성되지 않는다.In the present invention as described above, since the metal for forming the plug is deposited in the contact hole in which the insulating film side wall is formed, the step coverage of the metal layer is improved due to the insulating film side wall, so that no overhang and key holes are generated.
또한 절연막측벽이 형성되기 전에 접촉저항을 낮추기 위한 Ti박막을 형성함으로써 절연막측벽으로 인한 금속과 실리콘기판과의 접촉면적감소에 의해 접촉저항이 저하되는 문제가 발생하지 않게 된다.In addition, since the Ti thin film for lowering the contact resistance is formed before the insulating film side wall is formed, the problem that the contact resistance decreases due to the reduction of the contact area between the metal and the silicon substrate due to the insulating film side wall does not occur.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940026828A KR0156126B1 (en) | 1994-10-20 | 1994-10-20 | Formation method of contact hole in semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940026828A KR0156126B1 (en) | 1994-10-20 | 1994-10-20 | Formation method of contact hole in semiconductor device |
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| KR960015730A KR960015730A (en) | 1996-05-22 |
| KR0156126B1 true KR0156126B1 (en) | 1998-12-01 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100493013B1 (en) * | 1998-11-30 | 2005-08-01 | 삼성전자주식회사 | Metal wiring layer formation method of semiconductor device_ |
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| KR100423065B1 (en) * | 1996-12-28 | 2004-06-10 | 주식회사 하이닉스반도체 | Method for preventing key hole from being generated in semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100493013B1 (en) * | 1998-11-30 | 2005-08-01 | 삼성전자주식회사 | Metal wiring layer formation method of semiconductor device_ |
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| KR960015730A (en) | 1996-05-22 |
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