KR0150989B1 - Formation wiring method for semiconductor device - Google Patents
Formation wiring method for semiconductor device Download PDFInfo
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- KR0150989B1 KR0150989B1 KR1019940018078A KR19940018078A KR0150989B1 KR 0150989 B1 KR0150989 B1 KR 0150989B1 KR 1019940018078 A KR1019940018078 A KR 1019940018078A KR 19940018078 A KR19940018078 A KR 19940018078A KR 0150989 B1 KR0150989 B1 KR 0150989B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
Abstract
반도체소자의 배선 형성방법이 개시되어 있다. 개구부를 포함하는 절연막이 형성되어 있는 반도체 기판 상에 티타늄을 증착하여 티타늄막을 형성하고, 상기 티타늄막을 질화시켜 제1티타늄질화막을 형성한 다음, 제1티타늄질화막 상에 제2티타늄질화막을 형성하고, 상기 결과물 상에 금속을 증착하여 금속층을 형성한다. 화학기상증착방법으로 티타늄질화막을 증착하기 전에 하부의 티타늄막을 질화시킴으로써 단차도포성이 우수하고 기공이 없는 콘택 매몰은 물론, 결함물질의 생성을 방지하여 낮은 콘택저항을 갖는 신뢰성있는 금속배선 형성이 가능하다.A method of forming a wiring of a semiconductor device is disclosed. Forming a titanium film by depositing titanium on a semiconductor substrate having an insulating film including openings, nitriding the titanium film to form a first titanium nitride film, and then forming a second titanium nitride film on the first titanium nitride film, Metal is deposited on the resultant to form a metal layer. By depositing the titanium nitride film before depositing the titanium nitride film by chemical vapor deposition method, it is possible to form a reliable metal wire with low contact resistance by preventing contact formation without pore contact and excellent contact coverage without porosity and generation of defective materials. Do.
Description
제1(a)도 내지 제1(e)도는 종래의 금속배선 형성방법의 일례를 설명하기 위한 단면도들이고,1 (a) to (e) are cross-sectional views for explaining an example of a conventional metal wiring forming method,
제2(a)도 내지 제2(f)도는 본 발명에 의한 금속배선 형성방법의 일례를 설명하기 위한 단면도들이고,2 (a) to 2 (f) are cross-sectional views for explaining an example of the metal wiring forming method according to the present invention,
제3(a)도 및 제3(b)도는 질화 처리를 실시한 경우와 실시하지 않은 경우의 콘택 개구부의 단면을 비교한 SEM 사진들이다.3 (a) and 3 (b) are SEM photographs comparing cross sections of contact openings with and without nitriding.
본 발명은 고집적 반도체소자의 배선 형성방법에 관한 것으로, 특히 오믹층인 티타늄막 표면을 질화시켜 안정적이고 신뢰성있는 배선을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring of a highly integrated semiconductor device, and more particularly, to a method for forming a stable and reliable wiring by nitriding a surface of a titanium film as an ohmic layer.
현재, 반도체 기억소자에서 일반적으로 사용되고 있는 배선 형성기술은 실리콘 기판과 접촉하는 오믹층(ohmic layer)으로서 티타늄(Ti)을 증착하고, 그 위에 배선재료, 예컨대 알루미늄(A1)과의 상호확산을 방지하는 베리어층(barrier layer)으로서 티타늄질화막(TiN)을 사용하고 있다. 이와 같은 배선 구조에서 티타늄과 티타늄 질화막을 증착시키는 방법으로는 주로 스퍼터(sputter) 방법이 많이 쓰이고 있다. 그러나, 반도체소자의 고집적화에 따라 콘택 사이즈는 감소하게 되었고, 어스팩트비(aspect ratio)는 증가하게 되었다. 이에 따라 종래 스퍼터 방법에 의한 티타늄질화막의 단차도포성(step coverage)이 불량하여 누설 접합전류 및 콘택 저항의 증가와 불안정을 초래하게 되었다.At present, a wiring forming technique generally used in semiconductor memory devices deposits titanium (Ti) as an ohmic layer in contact with a silicon substrate, and prevents interdiffusion with wiring materials such as aluminum (A1) thereon. A titanium nitride film (TiN) is used as a barrier layer. In such a wiring structure, a method of depositing titanium and a titanium nitride film is mainly used as a sputter method. However, as the integration of semiconductor devices is increased, the contact size is reduced and the aspect ratio is increased. As a result, the step coverage of the titanium nitride film by the conventional sputtering method is poor, leading to an increase and instability of the leakage junction current and the contact resistance.
이러한 문제를 해결하고자 최근에는 콜리메이터(collimator)를 이용한 스퍼터링 방식이 연구되어 단차도포성 향상을 이루었으나, 256M급 이상, 0.25㎛이하의 콘택홀에서는 어스펙트비가 3.0 이상으로 예상됨으로 콜리메이터를 이용한 스퍼터링 방법으로도 신뢰성 있는 티타늄질화막의 형성이 불가능하다.In order to solve this problem, sputtering method using collimator has been studied recently to improve step coverage, but the sputtering method using collimator is expected to have an aspect ratio of 3.0 or more in contact holes of 256M or more and 0.25 µm or less. It is also impossible to form a reliable titanium nitride film.
따라서, 스퍼터 증착방법의 이러한 단점을 보완하고 높은 어스팩트비에서도 좋은 단차도포성을 얻을 수 있는 화학기상증착방법(CVD)으로의 전환이 필요하게 되었다.Therefore, it is necessary to switch to the chemical vapor deposition method (CVD) which can compensate for these disadvantages of the sputter deposition method and obtain good step coverage even at high aspect ratios.
제1(a)도 내지 제1(e)도는 종래의 방법에 의한 배선형성의 일례를 설명하기 위한 단면도들이다.1 (a) to 1 (e) are cross-sectional views for explaining an example of wiring formation by a conventional method.
제1(a)도를 참조하면, 반도체기판(10) 상에 필드산화막(12)으로 소자분리영역을 정의하고, 상기 기판(10)에 불순물을 주입하여 소오스/드레인 영역(14)을 형성한다. 이어서 콘택이 형성될 절연막 예컨대, 산화막(16)을 성장시킨다.Referring to FIG. 1A, a device isolation region is defined by a field oxide film 12 on a semiconductor substrate 10, and impurities are implanted into the substrate 10 to form a source / drain region 14. . Next, an insulating film, for example, an oxide film 16, on which a contact is to be formed is grown.
제1(b)도를 참조하면, 사진식각공정으로 상기 산화막(16)을 식각하여 콘택 개구부(h)를 형성한다.Referring to FIG. 1 (b), the oxide layer 16 is etched by the photolithography process to form the contact opening h.
제1(c)도를 참조하면, 상기 소오스/드레인 영역(14)과 오믹 콘택을 하는 티타늄을 상기 산화막(16) 위와 콘택 개구부(contact hole: h) 내부에 스퍼터 방법으로 증착하여 오믹층(ohmic layer)으로서 티타늄막(18)을 형성한다.Referring to FIG. 1 (c), a titanium in ohmic contact with the source / drain region 14 is deposited on the oxide layer 16 and in a contact hole h by a sputtering method. As a layer, a titanium film 18 is formed.
제1(d)도를 참조하면, 상기 티타늄막(18) 상에 질화 티타늄을 화학기상증착(CVD) 방법에 의해 증착하여 확산 방지막으로서 티타늄질화막(20)을 형성한다.Referring to FIG. 1 (d), titanium nitride is deposited on the titanium film 18 by chemical vapor deposition (CVD) to form a titanium nitride film 20 as a diffusion barrier.
제1(e)도를 참조하면, 상기 증착된 티타늄질화막(20) 상에 전도물 예컨대, 알루미늄을 증착하여 배선층(22)을 형성한다.Referring to FIG. 1 (e), the wiring layer 22 is formed by depositing a conductive material such as aluminum on the deposited titanium nitride film 20.
그러나, 스퍼터 방법에 의해 티타늄막을 형성한 다음, 상기 티타늄막 상에 TiCl4와 NH3를 사용하여 화학기상증착방법으로 티타늄질화막을 형성한다. 이때, TiCl4에 존재하는 염소(Cl)와 하부 티타늄막의 티타늄(Ti)과 반응하여 결함(defect)을 발생시킨다. 이러한 결함은 결과적으로 콘택의 저항 및 누설전류의 증가를 초래하게 된다. 상기 결함의 단면 SEM 사진이 제3도에 도시되어 있다.However, after the titanium film is formed by the sputtering method, the titanium nitride film is formed by chemical vapor deposition using TiCl 4 and NH 3 on the titanium film. At this time, defects are generated by reacting with chlorine (Cl) present in TiCl 4 and titanium (Ti) of the lower titanium film. These defects result in an increase in the resistance and leakage current of the contact. A cross-sectional SEM photograph of the defect is shown in FIG.
따라서, 본 발명의 목적은 티타늄막 상에 CVD 방법에 의해 티타늄질화막을 형성함에 있어서, 콘택 및 배선의 저항을 감소시켜 보다 신뢰성있는 반도체소자 금속배선 형성방법을 제공하는데 있다.Accordingly, an object of the present invention is to provide a more reliable method for forming a semiconductor device metal wiring by reducing the resistance of contacts and wirings in forming a titanium nitride film by a CVD method on a titanium film.
상기 목적을 달성하기 위해 본 발명은, 개구부를 포함하는 절연막이 형성되어 있는 반도체 기판 상에 티타늄을 증착하여 티타늄막을 형성하는 단계, 상기 티타늄막을 질화시켜 제1티타늄질화막을 형성하는 단계, 및 상기 결과물 상에 금속을 증착하여 금속층을 형성하는 단계를 구비하는 것을 특징으로 하는 반도체소자 금속배선 형성방법을 제공한다.In order to achieve the above object, the present invention, the step of forming a titanium film by depositing titanium on a semiconductor substrate having an insulating film including an opening, the step of nitriding the titanium film to form a first titanium nitride film, and the resultant It provides a method for forming a semiconductor device metal wiring, comprising the step of forming a metal layer by depositing a metal on the.
이때, 상기 공정은 상기 제1티타늄질화막 상에 제2티타늄질화막을 형성하는 단계를 더 구비할 수 있다. 또한 상기 제1티타늄질화막은 methylhydrazine 또는 diemethylhydrazine을 사용하여 형성하고, 200∼700℃ 온도에서 형성하는 것이 바람직하다.In this case, the process may further include forming a second titanium nitride film on the first titanium nitride film. In addition, the first titanium nitride film is formed using methylhydrazine or diemethylhydrazine, it is preferable to form at a temperature of 200 ~ 700 ℃.
본 발명은 티타늄질화막을 CVD 방법으로 증착하기 전에 티타늄막 표면을 질화시켜, 상기 티타늄질화막 증착시 필수적으로 사용되는 티타늄 소스 가스(예컨대 TiCl4, 이하 TiCl4라 한다)와 상기 티타늄(Ti)막과의 반응에 의해 생성되는 결함물질의 생성을 억제함으로써 낮은 콘택 저항을 얻는다.The present invention (for example, TiCl 4, hereinafter referred to as TiCl 4) by nitriding the titanium film surface prior to depositing the titanium nitride film by the CVD method, the titanium nitride film is essentially a titanium source gas used during the deposition and the titanium (Ti) film and A low contact resistance is obtained by suppressing the generation of the defective material produced by the reaction of.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명하고자 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2(a)도 내지 제2(f)도는 본 발명에 의한 반도체소자의 금속배선 형성방법을 설명하기 위한 일 실시예를 나타내며, 상기 도면에서의 같은 참조 번호는 같은 물질을 나타낸다.2 (a) to 2 (f) show one embodiment for explaining a method for forming metal wirings of a semiconductor device according to the present invention, wherein like reference numerals in the drawings denote like materials.
제2(a)도는 콘택 개구부 형성 전의 단계를 나타내는 단면도이다. 실리콘 기판(50) 상의 소자분리 영역에 필드 산화막(52)를 통상적인 방법에 의해 성장시키고, 상기 기판(50)에 불순물을 주입하여 소오스/드레인 영역(54)을 형성한 다음, 상기 소오스/드레인 영역(54)위에 절연막 예컨대, 산화막(56)을 성장시킨다.2 (a) is a cross-sectional view showing a step before forming the contact opening. The field oxide film 52 is grown in a device isolation region on the silicon substrate 50 by a conventional method, and impurities are implanted into the substrate 50 to form a source / drain region 54, and then the source / drain An insulating film, for example, an oxide film 56 is grown on the region 54.
제2(b)도는 상기 절연막에 콘택 개구부(m)를 형성하는 단계를 나타내는 단면도이다. 상기 산화막(56) 상에 포토레지스트를 도포하고 이를 노광 및 현상하여 포토레지스트 패턴(도시되지 않음)을 형성한다. 이어서 상기 포토레지스트 패턴을 식각 마스크로 사용하여 상기 산화막(56)을 반응성 이온 에칭(RIE)으로 식각하여 개구부(m)을 형성한다.FIG. 2B is a cross-sectional view illustrating a step of forming a contact opening m in the insulating film. A photoresist is applied on the oxide film 56, and the photoresist is exposed and developed to form a photoresist pattern (not shown). Subsequently, the oxide layer 56 is etched using reactive ion etching (RIE) to form the opening m using the photoresist pattern as an etching mask.
제2(c)도는 상기 절연막(56) 상에 티타늄막(58)을 형성하는 단계를 나타내는 단면도이다. 상기 포토레지스트 패턴을 제거한 다음, 상기 절연막(56) 위에 티타늄을 스퍼터 방법으로 증착하여 오믹 층, 예컨대, 티타늄막(58)을 형성한다.FIG. 2C is a cross-sectional view illustrating a step of forming the titanium film 58 on the insulating film 56. After removing the photoresist pattern, titanium is deposited on the insulating film 56 by a sputtering method to form an ohmic layer, for example, a titanium film 58.
제2(d)도는 상기 티타늄막(58)을 질화시켜 제1티타늄질화막(60)을 형성하는 단계를 나타내는 단면도이다. 상기 티타늄막(58) 상에 methylhydrazine을 흘려 티타늄막 표면을 질화시킴으로써 제1티타늄질화막(60)을 형성한다. 후속 공정에서 제2티타늄질화막을 형성하기 위해 사용되는 TiCl4소스 가스와 상기 증착된 티타늄막(58)과의 결합으로 생성되는 결함물질은 콘택저항을 증가시킨다. 따라서, 상기 티타늄막(58)을 질화시킴으로써 TiCl4가스에 함유된 Cl기에 의한 티타늄막(58) 표면에서의 결함물질 생성을 방지하여 안정적이고 신뢰성 있는 콘택 및 배선공정을 이룰 수 있다. 이때, 상기 질화공정시 200∼700℃의 온도를 유지하는 것이 바람직하다.FIG. 2D is a cross-sectional view illustrating a step of forming the first titanium nitride film 60 by nitriding the titanium film 58. The first titanium nitride film 60 is formed by flowing methylhydrazine onto the titanium film 58 to nitride the surface of the titanium film. In a subsequent process, the defect material generated by combining TiCl 4 source gas used to form the second titanium nitride film with the deposited titanium film 58 increases the contact resistance. Therefore, by nitriding the titanium film 58, it is possible to prevent the generation of defects on the surface of the titanium film 58 by Cl group contained in the TiCl 4 gas, thereby achieving a stable and reliable contact and wiring process. At this time, it is preferable to maintain the temperature of 200 ~ 700 ℃ during the nitriding process.
한편, 경우에 따라서는 상기 제1티타늄질화막만으로 확산 방지막을 구성할 수도 있다.In some cases, the diffusion barrier layer may be formed of only the first titanium nitride layer.
상기 질화공정의 실시 여부에 따른 결과 즉, 질화 처리를 실시한 경우와 실시하지 않은 경우의 단면 SEM 사진을 제3(a)도 및 제3(b)도에 도시하였다.The results according to whether or not the nitriding process is performed, that is, cross-sectional SEM photographs with and without nitriding are shown in FIGS. 3 (a) and 3 (b).
제2(e)도는 제2티타늄질화막(62)을 형성하는 단계를 나타내는 단면도이다. 상기 제1티타늄질화막(60) 상에 TiCl4가스를 소스로 사용하여 질화 텅스텐을 화학기상증착방법, 예컨대, 저압 화학기상증착법(LPCVD: Low Pressure Chemical Vapor Deposition)에 의해 증착하여 제2티타늄질화막(62)을 확산 방지막으로 형성한다.FIG. 2E is a cross-sectional view illustrating a step of forming the second titanium nitride film 62. Using a TiCl 4 gas as a source on the first titanium nitride film 60, tungsten nitride is deposited by a chemical vapor deposition method, for example, a low pressure chemical vapor deposition (LPCVD) method to deposit a second titanium nitride film ( 62 is formed as a diffusion barrier.
제2(f)도는 배선층(64)을 형성하는 단계를 나타내는 단면도이다. 상기 제2티타늄질화막(62)위에 금속을 스퍼터링 방법으로 증착하여 금속층을 형성한 다음, 상기 금속을 용융점 이하의 고온에서 진공중에서 열처리 하여 리플로우(reflow) 시켜서 콘택을 기공없이 매물하는 배선층(64)을 형성한다. 상기 금속으로서는 예를 들면, 알루미늄-1% 실리콘 또는 알루미늄-0.5% 구리-1% 실리콘 등과 같이 실리콘 성분을 함유하는 알루미늄 합금을 사용한다.FIG. 2 (f) is a cross-sectional view showing the step of forming the wiring layer 64. As shown in FIG. A wiring layer 64 for depositing a metal on the second titanium nitride film 62 by sputtering to form a metal layer, and then heat-treating the metal at a high temperature below the melting point in vacuum to reflow to sell the contact without pores. To form. As the metal, for example, an aluminum alloy containing a silicon component such as aluminum-1% silicon or aluminum-0.5% copper-1% silicon is used.
제3(a)도 및 제3(b)도는 상기 실시예의 공정 중 질화시키는 단계에서, 질화처리 유·무에 따른 콘택 개구부의 단면을 비교한 SEM 사진이다.3 (a) and 3 (b) are SEM images comparing the cross sections of the contact openings with and without nitriding in the nitriding in the process of the above embodiment.
제3(a)도는 티타늄을 증착한 후 질화처리를 실시하지 않고, 질화티타늄을 증착하여 수득한 콘택 개구부의 단면을 나타내는 SEM 사진으로서, 상기 티타늄질화막 증착시 사용되는 소스 가스(TiCl4)와 상기 증착된 티타늄(Ti)과의 화학반응으로 결함물질이 생성되어 있음을 보여준다.FIG. 3 (a) is a SEM photograph showing a cross section of a contact opening obtained by depositing titanium nitride without depositing titanium after depositing titanium, and the source gas (TiCl 4 ) used for depositing the titanium nitride film and the The chemical reaction with the deposited titanium (Ti) shows that the defective material is produced.
제3(b)도는 상기 티타늄을 증착한 후 상기 실시예의 방법에 따라 질화처리를 실시하고, 질화티타늄을 증착하여 수득한 콘택 개구부의 단면을 나타내는 SEM 사진으로, 상기 티타늄막과 상기 티타늄질화막의 계면에 어떤 결함물질도 생성되어 있지 않음을 보여준다.FIG. 3 (b) is a SEM photograph showing a cross section of a contact opening obtained by depositing the titanium and performing nitride treatment according to the method of the embodiment and depositing titanium nitride, wherein the interface between the titanium film and the titanium nitride film. Shows that no defects have been produced.
이상, 상술한 바와 같이 본 발명에 의하면 화학기상증착방법으로 티타늄질화막을 증착하기 전에 하부의 티타늄막을 질화시킴으로써 단차도포성이 우수하고 기공이 없는 콘택 매몰은 물론 결함물질의 생성을 방지하여 낮은 콘택 저항을 갖는 신뢰성있는 금속배선 형성이 가능하다.As described above, according to the present invention, before depositing the titanium nitride film by the chemical vapor deposition method, the lower titanium film is nitrided to provide excellent step coverage and prevent contact formation without pores, as well as to prevent the generation of defects, thereby lowering the contact resistance. It is possible to form a reliable metal wiring with.
본 발명은 상기 실시예에만 한정되지 않으며, 많은 변형이 본 발명이 속한 기술적 사상내에서 당 분야에서 통상의 지식을 가진 자에 의해 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea to which the present invention pertains.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| KR1019940018078A KR0150989B1 (en) | 1994-07-26 | 1994-07-26 | Formation wiring method for semiconductor device |
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| KR1019940018078A KR0150989B1 (en) | 1994-07-26 | 1994-07-26 | Formation wiring method for semiconductor device |
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| KR960005797A KR960005797A (en) | 1996-02-23 |
| KR0150989B1 true KR0150989B1 (en) | 1998-12-01 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100451493B1 (en) * | 1998-09-02 | 2004-12-04 | 주식회사 하이닉스반도체 | Metal wiring formation method of semiconductor device |
| KR100480582B1 (en) * | 1998-03-10 | 2005-05-16 | 삼성전자주식회사 | Fabricating method of barrier film of semiconductor device and fabricating method of metal wiring using the same |
-
1994
- 1994-07-26 KR KR1019940018078A patent/KR0150989B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100480582B1 (en) * | 1998-03-10 | 2005-05-16 | 삼성전자주식회사 | Fabricating method of barrier film of semiconductor device and fabricating method of metal wiring using the same |
| KR100451493B1 (en) * | 1998-09-02 | 2004-12-04 | 주식회사 하이닉스반도체 | Metal wiring formation method of semiconductor device |
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| KR960005797A (en) | 1996-02-23 |
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