KR960015730A - Contact Forming Method of Semiconductor Device - Google Patents

Contact Forming Method of Semiconductor Device Download PDF

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Publication number
KR960015730A
KR960015730A KR1019940026828A KR19940026828A KR960015730A KR 960015730 A KR960015730 A KR 960015730A KR 1019940026828 A KR1019940026828 A KR 1019940026828A KR 19940026828 A KR19940026828 A KR 19940026828A KR 960015730 A KR960015730 A KR 960015730A
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KR
South Korea
Prior art keywords
forming
contact hole
plug
contact
adhesion layer
Prior art date
Application number
KR1019940026828A
Other languages
Korean (ko)
Other versions
KR0156126B1 (en
Inventor
변정수
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019940026828A priority Critical patent/KR0156126B1/en
Publication of KR960015730A publication Critical patent/KR960015730A/en
Application granted granted Critical
Publication of KR0156126B1 publication Critical patent/KR0156126B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체장치의 콘택형성방법에 관한 것으로, 플러그(plug) 형성공정의 피복단차효과를 개선시키기 위한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact in a semiconductor device, and to improve the coating step effect of a plug forming step.

본 발명은 실리콘기판상에 형성된 콘택홀을 포함하는 절연막 전면에 밀착층을 형성하는 단계와, 상기 콘택홀 측면에 측벽절연막을 형성하는 단계, 상기 콘택홀 내부를 포함한 기판 전면에 장벽층을 형성하는 단계, 열처리 공정을 행하여 상기 실리콘기판과 기판과 접촉된 부분의 밀착층을 반응시켜 실리사이드를 형성하는 단계, 상기 콘택홀 내부에 금속을 매립시켜 플러그를 형성하는 단계로 이루어지는 반도체장치의 콘택형성방법을 제공함으로써 플러그형성시의 오버행 및 키홀등의 생성을 방지할 수 있도록 한다.The present invention provides a method for forming an adhesion layer on an entire surface of an insulating film including a contact hole formed on a silicon substrate, forming a sidewall insulating film on a side of the contact hole, and forming a barrier layer on an entire surface of the substrate including an inside of the contact hole. And forming a silicide by reacting the adhesion layer between the silicon substrate and the portion in contact with the substrate to form a silicide, and embedding a metal in the contact hole to form a plug. By providing it, it is possible to prevent the generation of overhangs, keyholes, and the like during plug formation.

Description

반도체장치의 콘택형성방법Contact Forming Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 종래의 반도체장치의 콘택형성방법을 도시한 공정 순서도,1 is a process flowchart showing a contact forming method of a conventional semiconductor device;

제2도는 본 발명의 반도체장치의 콘택형성방법을 도시한 공정순서도.2 is a process flowchart showing a contact forming method of a semiconductor device of the present invention.

Claims (5)

실리콘기판상에 형성된 콘택홀을 포함하는 절연막 전면에 밀착층을 형성하는 단계와, 상기 콘택홀 측면에 측벽절연막을 형성하는 단계, 상기 콘택홀 내부를 포함한 기판 전면에 장벽층을 형성하는 단계, 열처리공정을 행하여 상기 실리콘기판과 기판과 접촉된 부분의 밀착층을 반응시켜 실리사이드를 형성하는 단계, 상기 콘택홀내부에 금속을 매립시켜 플러그를 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체장치의 콘택형성방법.Forming an adhesion layer on the entire surface of the insulating film including the contact hole formed on the silicon substrate, forming a sidewall insulating film on the side of the contact hole, forming a barrier layer on the entire surface including the inside of the contact hole, and heat treatment Forming a silicide by reacting the adhesion layer between the silicon substrate and the portion in contact with the substrate, and forming a plug by embedding a metal in the contact hole. . 제1항에 있어서, 상기 밀착층은 Ti, Co, Mo, W등의 금속으로 형성하는 것을 특징으로 하는 반도체장치의 콘택형성방법.The method of claim 1, wherein the adhesion layer is formed of a metal such as Ti, Co, Mo, or W. 제1항에 있어서, 상기 장벽층은 내화금속질화막으로 형성하는 것을 특징으로 하는 반도체장치의 콘택형성 방법.The method of claim 1, wherein the barrier layer is formed of a refractory metal nitride film. 제1항에 있어서, 상기 플러그는 텅스텐을 블랭킷 증착한 후 에치백하는 공정에 의해 형성하는 것을 특징으로 하는 반도체장치의 콘택형성방법.The method of claim 1, wherein the plug is formed by blanket deposition of tungsten and then etched back. 제1항에 있어서, 상기 플러그는 알루미늄 플로우공정에 의해 형성하는 것을 특징으로 하는 반도체장치의 콘택형성방법.The method of claim 1, wherein the plug is formed by an aluminum flow process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940026828A 1994-10-20 1994-10-20 Formation method of contact hole in semiconductor device KR0156126B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940026828A KR0156126B1 (en) 1994-10-20 1994-10-20 Formation method of contact hole in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940026828A KR0156126B1 (en) 1994-10-20 1994-10-20 Formation method of contact hole in semiconductor device

Publications (2)

Publication Number Publication Date
KR960015730A true KR960015730A (en) 1996-05-22
KR0156126B1 KR0156126B1 (en) 1998-12-01

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Application Number Title Priority Date Filing Date
KR1019940026828A KR0156126B1 (en) 1994-10-20 1994-10-20 Formation method of contact hole in semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100423065B1 (en) * 1996-12-28 2004-06-10 주식회사 하이닉스반도체 Method for preventing key hole from being generated in semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100493013B1 (en) * 1998-11-30 2005-08-01 삼성전자주식회사 Metal wiring layer formation method of semiconductor device_

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100423065B1 (en) * 1996-12-28 2004-06-10 주식회사 하이닉스반도체 Method for preventing key hole from being generated in semiconductor device

Also Published As

Publication number Publication date
KR0156126B1 (en) 1998-12-01

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