KR970003845A - Metal wiring formation method of semiconductor device - Google Patents

Metal wiring formation method of semiconductor device Download PDF

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Publication number
KR970003845A
KR970003845A KR1019950017494A KR19950017494A KR970003845A KR 970003845 A KR970003845 A KR 970003845A KR 1019950017494 A KR1019950017494 A KR 1019950017494A KR 19950017494 A KR19950017494 A KR 19950017494A KR 970003845 A KR970003845 A KR 970003845A
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KR
South Korea
Prior art keywords
film
forming
titanium
tungsten
entire surface
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KR1019950017494A
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Korean (ko)
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최근민
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김주용
현대전자산업 주식회사
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Priority to KR1019950017494A priority Critical patent/KR970003845A/en
Publication of KR970003845A publication Critical patent/KR970003845A/en

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Abstract

본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 반도체기판 상부에 평탄화된 층간절연막을 형성하고 금속배선 콘택마스크를 이용한 식각공정으로 콘택홀을 형성한 다음, 전체표면상부에 PVD 또는 CVD 방법으로 티타늄막을 일정두께 형성하고 상기 티타늄막 상부에 제1티타늄질화막을 CVD 방법으로 두껍게 형성하고 그 상부에 제2티타늄질화막을 PVD 방법으로 얇게 형성한 다음, 전체표면상부에텅스텐막을 일정두께 전면증착하고 상기 텅스텐막을 전면식각함으로써 상기 콘택홀에 매립된 텅스텐막을 제외한 텅스텐막을 제거하여 텅스텐 콘택플러그를 형성한 다음, 전체표면상부에 금속층을 형성하여 상기 텅스텐 콘택플로그와 접속시킴으로써 PVD 및 CVD 방법으로 형성된 박막의 단점을 개선함으로써 반도체소자의 특성 및 신뢰성을 향상시키고 반도체소자의 고집적회로를 가능하게 하는 기술이다.The present invention relates to a method for forming a metal wiring of a semiconductor device, to form a planarized interlayer insulating film on the semiconductor substrate, and to form a contact hole by an etching process using a metal wiring contact mask, and then PVD or CVD on the entire surface A titanium film is formed to a certain thickness, and a first titanium nitride film is formed thick on the titanium film by the CVD method, and a second titanium nitride film is formed thin on the upper surface of the titanium film by PVD method. Disadvantages of thin films formed by PVD and CVD methods by forming a tungsten contact plug by removing the tungsten film except the tungsten film embedded in the contact hole by front etching the tungsten film, and then forming a metal layer on the entire surface of the tungsten contact plug. Improve the characteristics and reliability of semiconductor devices It is a technology that enables a highly integrated circuit of a semiconductor device.

Description

반도체소자의 금속배선 형성방법Metal wiring formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1E도는 본 발명의 실시예에 따른 반도체소자의 금속배선 형성공정을 도시한 개략도.1E is a schematic diagram showing a metal wiring forming process of a semiconductor device according to an embodiment of the present invention.

Claims (8)

반도체기판 상부에 제1층간절연막을 형성하는 공정과, 상기 제1층간절연막 상부 일측에 도전배선을 형성하는 공정과, 전체표면상부에 평탄화된 제2층간절연막을 형성하는 공정과, 금속배선 콘택마스크를 이용한 식각공정으로 상기 반도체기판의 예정된 부분을 노출시키는 제1콘택홀을 형성하는 동시에 상기 도전배선을 노출시키는 제2콘택홀을 형성하는 공정과, 전체표면상부에 티타늄막을 일정두께 형성하는 공정과, 상기 티타늄막 상부에 CVD 방법으로 제1티타늄질화막을 일정두께 형성하는 공정과, 상기 제1티타늄질화막 상부에 PVD 방법으로 제2티타늄질화막을 일정두께 형성하는 공정과, 전체표면상부에 텅스텐막을 일정두께 전면증착하는 공정과, 상기 텅스텐막을 전면식각하여 상기 제1콘택홀과 제2콘택홀에 매립된 텅스텐 콘택플러그를 형성하는 공정과, 전체표면상부에 알루미늄합금을 일정두께 형성하는 공정을 포함하는 반도체소자의 금속배선 형성방법.Forming a first interlayer insulating film on the semiconductor substrate, forming a conductive wiring on one side of the first interlayer insulating film, forming a flattened second interlayer insulating film on the entire surface, and a metal wiring contact mask. Forming a first contact hole for exposing a predetermined portion of the semiconductor substrate by an etching process and forming a second contact hole for exposing the conductive wiring; forming a predetermined thickness of a titanium film on the entire surface; Forming a first titanium nitride film on the titanium film by a CVD method, forming a second titanium nitride film on the first titanium nitride film by a PVD method, and a tungsten film on the entire surface. And depositing a tungsten contact plug embedded in the first contact hole and the second contact hole by etching the entire surface of the tungsten film. Step, a metal wiring method for forming a semiconductor device including a step of an upper aluminum alloy on the entire surface to form a predetermined thickness. 제1항에 있어서, 상기 티타늄막은 PVD 방법으로 형성되는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein the titanium film is formed by a PVD method. 제1항에 있어서, 상기 티타늄막은 50 내지 300Å 두께로 형성되는 것을 특징으로 하는 반도체소자의 금속 배선 형성방법.The method of claim 1, wherein the titanium film is formed to have a thickness of about 50 to about 300 microns. 제1항에 있어서, 상기 제1티타늄질화막은 50 내지 900Å 두께로 형성되는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.2. The method of claim 1, wherein the first titanium nitride film is formed to a thickness of 50 to 900 kHz. 제1항에 있어서, 상기 제1티타늄질화막은 TDMAT를 금속유기화합물 소오스로 하여 형성되는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein the first titanium nitride film is formed using a TDMAT as a metal organic compound source. 제1항에 있어서, 상기 제2티타늄질화막은 10 내지 300Å 두께로 형성되는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein the second titanium nitride film is formed to have a thickness of about 10 to about 300 microns. 제1항에 있어서, 상기 텅스텐막은 3000 내지 5000Å 두께로 형성되는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.2. The method of claim 1, wherein the tungsten film is formed to a thickness of 3000 to 5000 kPa. 제1항에 있어서, 상기 알루미늄합금은 4000 내지 6000Å 두께로 형성되는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method of claim 1, wherein the aluminum alloy is formed to a thickness of 4000 to 6000 GHz metal wiring method of a semiconductor device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950017494A 1995-06-26 1995-06-26 Metal wiring formation method of semiconductor device KR970003845A (en)

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KR1019950017494A KR970003845A (en) 1995-06-26 1995-06-26 Metal wiring formation method of semiconductor device

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KR1019950017494A KR970003845A (en) 1995-06-26 1995-06-26 Metal wiring formation method of semiconductor device

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KR970003845A true KR970003845A (en) 1997-01-29

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