KR960019511A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR960019511A
KR960019511A KR1019940028515A KR19940028515A KR960019511A KR 960019511 A KR960019511 A KR 960019511A KR 1019940028515 A KR1019940028515 A KR 1019940028515A KR 19940028515 A KR19940028515 A KR 19940028515A KR 960019511 A KR960019511 A KR 960019511A
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South Korea
Prior art keywords
forming
layer
contact hole
contact
conductive layer
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KR1019940028515A
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Korean (ko)
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KR0156122B1 (en
Inventor
이경일
주승기
이재갑
김재호
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문정환
금성일렉트론 주식회사
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Priority to KR1019940028515A priority Critical patent/KR0156122B1/en
Publication of KR960019511A publication Critical patent/KR960019511A/en
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Publication of KR0156122B1 publication Critical patent/KR0156122B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure

Abstract

본 발명은 반도체장치의 제조방법에 관한 것으로, 콘택홀의 애스팩트비가 큰 초고직접소자에 적당한 배선기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a wiring technique suitable for an ultra-high direct element having a large aspect ratio of contact holes.

본 발명은 하부도전층을 포함하는 반도체기판상에 제1절연막을 형성하는 단계와, 상기 제1절연막을 선택적으로 식각하여 상기 하부도전층을 노출시키는 제1콘택홀을 형성하는 단계, 상기 제1콘택홀내부를 포함한 제1절연막 상부에 실리사이드 형성을 위한 금속층을 형성하는 단계, 상기 금속층상에 장벽층을 형성하는 단계, 상기 제1콘택홀내부에 매립되도록 콘택플러그를 형성하는 단계, 상기 제1절연막 및 콘택플러그 상부에 제2절연막을 형성하는 단계, 상기 제2절연막을 선택적으로 식각하여 상기 제1콘택홀 상부에 상기 콘택플러그를 노출시키는 제2콘택홀을 형성하는 단계, 및 상기 제2콘택홀내부를 포함한 제2절연막 상부에 상기 콘택플러그를 통해 상기 하부도전층과 접속되는 상부도전층을 형성하는 단계를 포함하여 이루어지는 반도체장치의 제조방법을 제공함으로써 콘택홀을 2단계로 나누어 형성하여 각각의 콘택홀 형성시에 실제 애스팩트비보다 반이하로 줄어든 애스팩트비를 갖는 콘택홀을 형성할 수 있도록 하여 콘택홀에서의 스텝커버리지를 향상시킨다.The present invention provides a method for forming a semiconductor device including forming a first insulating layer on a semiconductor substrate including a lower conductive layer, selectively etching the first insulating layer to form a first contact hole exposing the lower conductive layer, and forming a first contact hole. Forming a metal layer for silicide formation on the first insulating layer including a contact hole, forming a barrier layer on the metal layer, and forming a contact plug to be buried in the first contact hole; Forming a second insulating film over the insulating film and the contact plug, selectively etching the second insulating film to form a second contact hole over the first contact hole to expose the contact plug, and the second contact Forming an upper conductive layer on the second insulating layer including a hole, the upper conductive layer being connected to the lower conductive layer through the contact plug. By providing a method of formation, the contact holes are formed in two steps so that contact holes having an aspect ratio reduced by less than half of the actual aspect ratio can be formed at each contact hole formation. Improve.

Description

반도체장치의 제조방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4도는 본 발명의 반도체장치의 콘택형성방법을 도시한 공정순서도.4 is a process flowchart showing a contact forming method of a semiconductor device of the present invention.

Claims (10)

하부도전층을 포함하는 반도체기판상에 제1절연막을 형성하는 단계와, 상기 제1절연막을 선택적으로 식각하여 상기 하부도전층을 노출시키는 제1콘택홀을 형성하는 단계, 상기 제1콘택홀내부를 포함한 제1절연막 상부에 실리사이드 형성을 위한 금속층을 형성하는 단계, 상기 금속층상에 장벽층을 형성하는 단계, 상기 제1콘택홀내부에 매립되도록 콘택플러그를 형성하는 단계, 상기 제1절연막 및 콘택플러그 상부에 제2절연막을 형성하는 단계, 상기 제2절연막을 선택적으로 식각하여 상기 제1콘택홀 상부에 상기 콘택플러그를 노출시키는 제2콘택홀을 형성하는 단계, 및 상기 제2콘택홀내부를 포함한 제2절연막 상부에 상기 콘택플러그를 통해 상기 하부도전층과 접속되는 상부도전층을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체장치의 제조방법.Forming a first insulating layer on the semiconductor substrate including a lower conductive layer, selectively etching the first insulating layer to form a first contact hole exposing the lower conductive layer, and in the first contact hole Forming a metal layer for silicide formation on the first insulating layer, forming a barrier layer on the metal layer, forming a contact plug to be buried in the first contact hole, and forming the contact plug. Forming a second insulating layer over the plug, selectively etching the second insulating layer to form a second contact hole exposing the contact plug on the first contact hole, and forming an inside of the second contact hole And forming an upper conductive layer on the second insulating layer, the upper conductive layer being connected to the lower conductive layer through the contact plug. Method for manufacturing a device. 제1항에 있어서, 상기 실리사이드 형성을 위한 금속층은 Ti, Co, Mo등으로 형성하는 것을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the metal layer for silicide formation is formed of Ti, Co, Mo, or the like. 제1항에 있어서, 상기 장벽층은 TiN으로 형성하는 것을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the barrier layer is formed of TiN. 제1항에 있어서, 상기 실리사이드 형성을 위한 금속 층 및 장벽층은 컬리메이터를 이용한 스퍼터링방법 또는 CVD방법에 의해 형성하는 것을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the metal layer and the barrier layer for silicide formation are formed by a sputtering method using a collimator or a CVD method. 제1항에 있어서, 상기 제1절연막 및 제2절연막은 산화막으로 형성하는 것을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the first insulating film and the second insulating film are formed of an oxide film. 제1항에 있어서, 상기 상부도전층은 Al, Cu, W등의 금속으로 형성하는 것을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the upper conductive layer is formed of metal such as Al, Cu, or W. 제1항에 있어서, 상기 제1콘택홀과 제2콘택홀의 폭의 차이가 ±0.2㎛가 되도록 형성하는 것을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the difference between the widths of the first contact holes and the second contact holes is ± 0.2 μm. 제1항에 있어서, 상기 제2콘택홀을 형성하는 단계후에 제1콘택홀 내부를 포함한 제2절연막 상부에 장벽층을 형성하는 공정이 더 포함되는 것을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, further comprising forming a barrier layer on the second insulating layer including the inside of the first contact hole after the forming of the second contact hole. 제8항에 있어서, 상기 장벽층은 TiN을 컬리메이터를 이용한 스퍼터링방법이나 CVD방법에 의해 형성하는 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 8, wherein the barrier layer is formed by sputtering using a collimator or a CVD method. 제1항에 있어서, 상기 상부도전층을 형성하는 단계후에 상기 제2절연막 및 상부도전층상부에 절연막을 형성하고, 이 절연막을 선택적으로 식각하여 상기 제2콘택홀 상부에 콘택홀을 형성한 후, 이 콘택홀을 매립시는 도전층을 형성하는 공정을 적어도 1회 이상 실시하는 단계를 더 포함하는 것을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein after forming the upper conductive layer, an insulating layer is formed on the second insulating layer and the upper conductive layer, and the insulating layer is selectively etched to form a contact hole on the second contact hole. And at least one step of forming a conductive layer at the time of filling the contact hole. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940028515A 1994-11-01 1994-11-01 Fabrication method of semiconductor device KR0156122B1 (en)

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KR1019940028515A KR0156122B1 (en) 1994-11-01 1994-11-01 Fabrication method of semiconductor device

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Application Number Priority Date Filing Date Title
KR1019940028515A KR0156122B1 (en) 1994-11-01 1994-11-01 Fabrication method of semiconductor device

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KR960019511A true KR960019511A (en) 1996-06-17
KR0156122B1 KR0156122B1 (en) 1998-12-01

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KR100457408B1 (en) * 1997-12-30 2005-02-23 주식회사 하이닉스반도체 Method for forming tungsten plug of semiconductor device to improve reliability of semiconductor device

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