KR970052389A

KR970052389A - Contact hole formation method of semiconductor device

Info

Publication number: KR970052389A
Application number: KR1019950059283A
Authority: KR
Inventors: 이창원; 이수웅; 이성민
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1995-12-27
Filing date: 1995-12-27
Publication date: 1997-07-29

Abstract

본 발명은 콘택홀의 측벽에 턱이 형성되는 것을 방지하여 양호한 콘택프로파일을 얻을 수 있을 뿐만 아니라 후속의 금속배선막의 단차 피복성을 향상시킬 수 있는 반도체 장치의 콘택홀 형성방법에 관한 것이다.The present invention relates to a method for forming a contact hole in a semiconductor device which can prevent the formation of a jaw on the sidewall of the contact hole, thereby obtaining a good contact profile and improving the step coverage of a subsequent metal wiring film.

본 발명의 반도체 장치의 콘택홀 형성방법은 실리콘 기판상에 제1층간 절연막을 형성하는 공정과, 제1층간 절연막상에 비트라인을 형성하는 공정과, 비트라인 캡핑용 절연막으로 층간 절연막과 동일한 식각율을 갖는 막을 증착하는 공정과, 비트라인 캡핑용 절연막상에 제2층간 절연막을 형성하는 공정과, 제1 및 제2층간 절연막과 비트라인 캡핑용 절연막을 식각하여 콘택홀을 형성하는 공정을 포함한다.The method for forming a contact hole in a semiconductor device of the present invention comprises the steps of forming a first interlayer insulating film on a silicon substrate, forming a bit line on the first interlayer insulating film, and etching the same as that of the interlayer insulating film using an insulating film for bit line capping. A process of depositing a film having a rate, forming a second interlayer insulating film on the bit line capping insulating film, and forming a contact hole by etching the first and second interlayer insulating films and the bit line capping insulating film. do.

Description

Method for forming contact hole in semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 종래의 비트라인 캡핑용 절연막으로 PE-SiH₄막을 사용하였을 경우의 콘택홀의 단면 구조도.1 is a cross-sectional structure diagram of a contact hole when a PE-SiH ₄ film is used as a conventional bit line capping insulating film.

Claims

Forming a first interlayer insulating film 12 on the silicon substrate 11, forming a bit line 13 on the first interlayer insulating film 12, and forming an insulating film for bit line capping. Depositing a film 24 having an etch rate; forming a second interlayer insulating film 15 on the bit line capping insulating film 24; and first and second interlayer insulating films 12 and 15. And etching the bit line capping insulating film (24) to form a contact hole (16).

2. The method of claim 1, wherein a PE-PSG film is deposited to a thickness of 300 GPa with a bit line capping insulating film (24).

※ Note: The disclosure is based on the initial application.