KR100440267B1 - Method for forming metal interconnection of semiconductor device to improve metal interconnection filling characteristic in via hole and prevent void - Google Patents

Method for forming metal interconnection of semiconductor device to improve metal interconnection filling characteristic in via hole and prevent void Download PDF

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KR100440267B1
KR100440267B1 KR1019970081132A KR19970081132A KR100440267B1 KR 100440267 B1 KR100440267 B1 KR 100440267B1 KR 1019970081132 A KR1019970081132 A KR 1019970081132A KR 19970081132 A KR19970081132 A KR 19970081132A KR 100440267 B1 KR100440267 B1 KR 100440267B1
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peripheral circuit
circuit region
forming
region
planarization
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KR1019970081132A
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KR19990060886A (en
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남기원
김동현
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

Abstract

PURPOSE: A method for forming a metal interconnection of a semiconductor device is provided to improve a metal interconnection filling characteristic in a via hole and prevent a void by eliminating an interlayer dielectric between the first and second planarization layers before the via hole is formed. CONSTITUTION: The first planarization layer(202) and an interlayer dielectric(203) are sequentially formed on a semiconductor substrate(201) having various elements for fabricating a semiconductor device in a cell region(A) and on the semiconductor substrate in a peripheral circuit region(B). After a contact hole is formed in a selected region of the first planarization layer and the interlayer dielectric in the cell region, a charge storage node(205) is formed to bury the contact hole. A polysilicon layer for a plate electrode is formed on the resultant structure including the cell region and the peripheral circuit region. The polysilicon layer and the interlayer dielectric in the peripheral circuit region are removed to expose the first planarization layer in the peripheral circuit region. The second planarization layer(208) is formed on the resultant structure of the cell region and the peripheral circuit region. The selected regions of the second and first planarization layers in the peripheral circuit region are sequentially eliminated to form a via hole(209). After a barrier metal layer(210) is formed on the resultant structure, metal is reflowed to form a metal interconnection(211).

Description

반도체 소자의 금속 배선 형성 방법Metal wiring formation method of semiconductor device

본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 금속 배선을 위해 형성된 비아 홀내에 금속 배선의 매립 특성을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming metal wirings in semiconductor devices capable of improving the embedding characteristics of metal wirings in via holes formed for metal wiring.

반도체 소자의 제조 과정중 금속 배선을 형성하기 위해 비아 홀을 형성할 경우 작아지는 홀 사이즈와 깊어지는 홀 깊이에 의하여 점차 스텝커버러지가 나빠지고, 이에 따라 홀내의 금속 배선 매립이 악화되고 있다. 또한, 비아 홀을 형성한 후 실시하는 클리닝 공정과 금속 배선을 증착하기 전 실시하는 프리클리닝 공정에 의하여 발생되는 층간 절연막의 계면턱에 의하여 금속 배선이 홀내를 완전히 매립하지 못해 보이드를 형성하게 된다.When the via hole is formed to form the metal wiring during the manufacturing process of the semiconductor device, the step coverage gradually worsens due to the smaller hole size and the deeper hole depth, thereby deteriorating the embedding of the metal wiring in the hole. In addition, the voids are formed because the metal wires do not completely fill the holes due to the interface jaws of the interlayer insulating film generated by the cleaning process performed after the via holes are formed and the precleaning process performed before the deposition of the metal wires.

종래의 반도체 소자의 금속 배선 형성 방법을 도 1을 참조하여 설명하면 다음과 같다. 선택된 영역에 반도체 소자를 제조하기 위한 여러 요소, 예를 들어 트랜지스터 및 비트 라인 등이 형성된 반도체 기판(101) 상부에 제 1 평탄화막(102) 및 층간 절연막(103)을 순차적으로 형성한다. 층간 절연막(103) 및 제 1 평탄화막(102)의 선택된 영역, 즉 반도체 소자를 제조하기 위한 여러 요소가 형성된 반도체 기판(101)과 도통되는 콘택 홀을 형성한다. 콘택 홀이 형성된 층간 절연막(103)에서 제 1 평탄화막(102)까지의 측벽에 스페이서 산화막(104)을 형성한다. 콘택 홀이 매립되도록 제 1 폴리실리콘막을 형성하고 패터닝한 후 제 1 폴리실리콘막 측벽에 어느 정도의 높이를 갖는 스페이서를 제 2 폴리실리콘막으로 형성하여 전하저장 전극(105)을 형성한다. 그리고, 전체 구조 상부에 플레이트 전극으로 사용되는 제 3 폴리실리콘막(106)을 형성한다. 전체 구조 상부에 셀 영역(A)과 주변 회로 영역(B)을 구분하기 위한 감광막을 도포한 후 노광 및 식각 공정을 실시하여 셀 영역(A) 상부에 감광막 패턴(도시안됨)을 형성한다. 감광막 패턴(도시안됨)를 마스크로 식각 공정을 실시하여 주변 회로 영역(B)의 제 3 폴리실리콘막(106)을 제거한다. 감광막 패턴(도시안됨)을 제거한 후 제 2 평탄화막(107)을 형성한다. 주변 회로 영역(B)의 선택된 영역에 콘택 마스크를 이용한 건식 및 습식 식각 공정에 의해 비아 홀(108)을 형성한다. 이때, 제 1 및 제 2 평탄화막(102 및 107)과 층간 절연막(103)의 식각 속도의 차이에 의해 비아 홀(108)에 층간 절연막(103)에 의한 계면턱이 생기게 된다. 전체 구조 상부에 장벽 금속층(109)을 형성하는데, 계면턱에 의해 장벽 금속층(109)이 비아 홀(108)내에 증착되지 못한다. 이후, 알루미늄을 플로우시켜 금속 배선(110)을 형성한다. 이때, 층간 절연막(103)에 의한 계면턱에 의해 비아 홀(108)내에 금속 배선(110)이 제대로 증착되지 않아 보이드(C)가 형성되어 소자의 신뢰성을 저하시킨다.A method of forming a metal wiring of a conventional semiconductor device will be described below with reference to FIG. 1. The first planarization film 102 and the interlayer insulating film 103 are sequentially formed on the semiconductor substrate 101 on which various elements for manufacturing a semiconductor device, for example, a transistor and a bit line, are formed in the selected region. A contact hole is formed which is connected to the selected region of the interlayer insulating film 103 and the first planarization film 102, that is, the semiconductor substrate 101 on which various elements for manufacturing the semiconductor device are formed. The spacer oxide film 104 is formed on the sidewall from the interlayer insulating film 103 having the contact hole to the first planarization film 102. After forming and patterning the first polysilicon layer so as to fill the contact hole, a spacer having a certain height is formed on the sidewall of the first polysilicon layer as the second polysilicon layer to form the charge storage electrode 105. Then, the third polysilicon film 106 used as the plate electrode is formed on the entire structure. A photoresist film is formed on the entire structure to distinguish the cell region A from the peripheral circuit region B, and then an exposure and etching process is performed to form a photoresist pattern (not shown) on the cell region A. An etching process is performed using the photoresist pattern (not shown) as a mask to remove the third polysilicon film 106 in the peripheral circuit region B. After removing the photoresist pattern (not shown), the second planarization layer 107 is formed. Via holes 108 are formed in the selected region of the peripheral circuit region B by dry and wet etching processes using a contact mask. In this case, the interface jaw due to the interlayer insulating layer 103 is formed in the via hole 108 due to the difference in the etching speed between the first and second planarizing layers 102 and 107 and the interlayer insulating layer 103. A barrier metal layer 109 is formed over the entire structure, whereby the barrier metal layer 109 cannot be deposited in the via hole 108 by the interfacial barrier. Thereafter, aluminum is flowed to form the metal wiring 110. At this time, the metal wire 110 is not properly deposited in the via hole 108 due to the interfacial step formed by the interlayer insulating film 103, and thus voids C are formed, thereby reducing the reliability of the device.

따라서, 본 발명은 금속 배선을 형성하기 위한 비아 홀내에 완전하게 금속을 매립하여 반도체 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device capable of improving the reliability of a semiconductor device by completely filling a metal in a via hole for forming a metal wiring.

상술한 목적을 달성하기 위한 본 발명은 셀 영역에 반도체 소자를 제조하기 위한 여러 요소가 형성된 반도체 기판 상부와 주변 회로 영역의 반도체 기판 상부에 제 1 평탄화막 및 층간 절연막을 순차적으로 형성하는 단계와, 상기 셀 영역의 층간 절연막 및 제 1 평탄화막의 선택된 영역에 콘택 홀을 형성한 후 상기 콘택 홀이 매립되도록 전허저장 전극을 형성하는 단계와, 상기 셀 영역 및 주변 회로 영역을 포함한 전체 구조 상부에 플레이트 전극용 폴리실리콘막을 형성하는 단계와, 상기 주변 회로 영역에 형성된 플레이트 전극용 폴리실리콘막 및 층간 절연막을 제거하여 주변 회로 영역의 제 1 평탄화막을 노출시키는 단계와, 상기 셀 영역 및 주변 회로 영역 전체 구조 상부에 제 2 평탄화막을 형성하는 단계와, 상기 주변 회로 영역의 상기 제 2 및 제 1 평탄화막의 선택된 영역을 순차적으로 제거하여 비아 홀을 형성하는 단계와, 상기 비아 홀을 포함한 전체 구조 상부에 장벽 금속층을 형성한 후 금속을 플로우시켜 금속 배선을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.The present invention for achieving the above object is a step of sequentially forming a first planarization film and an interlayer insulating film on the semiconductor substrate formed on the semiconductor substrate of the semiconductor substrate in the peripheral circuit region and the various elements formed in the cell region, Forming a contact hole in a selected region of the interlayer insulating film and the first planarization film of the cell region, and then forming a fully-stored storage electrode so that the contact hole is filled; and a plate electrode over the entire structure including the cell region and the peripheral circuit region. Forming a polysilicon film for exposing, exposing the first planarization film of the peripheral circuit region by removing the polysilicon film and interlayer insulating film for the plate electrode formed in the peripheral circuit region, and overlying the entire structure of the cell region and the peripheral circuit region. Forming a second planarization film in said second circuit and said second and first of said peripheral circuit region Sequentially removing selected regions of the planarization layer to form via holes, and forming a barrier metal layer over the entire structure including the via holes, and then flowing metal to form metal wires. .

도 1은 종래의 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.BRIEF DESCRIPTION OF THE DRAWINGS The cross section of the element for demonstrating the metal wiring formation method of the conventional semiconductor element.

도 2(a) 내지 도 2(d)는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.2 (a) to 2 (d) are cross-sectional views of devices sequentially shown in order to explain a method for forming metal wirings of a semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>

101, 201 : 반도체 기판 102, 202 : 제 1 평탄화막101, 201: semiconductor substrate 102, 202: first planarization film

103, 203 : 층간 절연막 104, 204 : 스페이서 산화막103, 203: interlayer insulating film 104, 204: spacer oxide film

105, 205 : 전하저장 전극 106, 206 : 제 3 폴리실리콘막105, 205: charge storage electrode 106, 206: third polysilicon film

207 : 감광막 패턴 107, 208 : 제 2 평탄화막207: photosensitive film pattern 107, 208: second planarization film

108, 209 : 비아 홀 109, 210 : 장벽 금속층108, 209: via hole 109, 210: barrier metal layer

110, 211 : 금속 배선 A : 셀 영역110, 211: metal wiring A: cell area

B : 주변 회로 영역 C : 보이드B: peripheral circuit area C: void

첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.The present invention will be described in detail with reference to the accompanying drawings.

도 2(a) 내지 도 2(d)는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.2 (a) to 2 (d) are cross-sectional views of devices sequentially shown to explain a method for forming metal wirings of a semiconductor device according to the present invention.

도 2(a)를 참조하면, 선택된 영역에 반도체 소자를 제조하기 위한 여러 요소, 예를 들어 트랜지스터 및 비트 라인 등이 형성된 반도체 기판(201) 상부에 제 1 평탄화막(202) 및 층간 절연막(203)을 순차적으로 형성한다. 층간 절연막(203) 및 제 1 평탄화막(202)의 선택된 영역, 즉 반도체 소자를 제조하기 위한 여러 요소가 형성된 반도체 기판(201)과 도통되는 콘택 홀을 형성하고, 콘택 홀이 형성된 층간 절연막(203)에서 제 1 평탄화막(202)까지의 측벽에 스페이서 산화막(204)을 형성한다. 콘택 홀이 매립되도록 제 1 폴리실리콘막을 형성하고 패터닝한 후 제 1 폴리실리콘막 측벽에 어느 정도의 높이를 갖는 스페이서를 제 2 폴리실리콘막으로 형성하여 전하저장 전극(205)을 형성한다. 그리고, 전체 구조 상부에 플레이트 전극으로 사용되는 제 3 폴리실리콘막(206)을 형성한다.Referring to FIG. 2A, the first planarization layer 202 and the interlayer insulating layer 203 are formed on the semiconductor substrate 201 on which various elements, for example, transistors and bit lines, are formed in the selected region. ) Are formed sequentially. An interlayer insulating film 203 in which a contact hole is formed which is connected to a selected region of the interlayer insulating film 203 and the first planarization film 202, that is, the semiconductor substrate 201 in which various elements for manufacturing a semiconductor device are formed, and the contact hole is formed. ), A spacer oxide film 204 is formed on the sidewall of the first planarization film 202. After forming and patterning the first polysilicon film so as to fill the contact hole, a spacer having a certain height is formed on the sidewall of the first polysilicon film as the second polysilicon film to form the charge storage electrode 205. Then, a third polysilicon film 206 used as a plate electrode is formed on the entire structure.

도 2(b)를 참조하면, 전체 구조 상부에 셀 영역(A)과 주변 회로 영역(B)을 구분하기 위한 감광막을 도포한 후 노광 및 식각 공정을 실시하여 셀 영역(A) 상부에 감광막 패턴(207)을 형성한다. 감광막 패턴(207)를 마스크로 식각 공정을 실시하여 주변 회로 영역(B)의 제 3 폴리실리콘막(206) 및 층간 절연막(203)을 제거한다.Referring to FIG. 2 (b), a photoresist film for distinguishing the cell region A and the peripheral circuit region B is coated on the entire structure, followed by an exposure and etching process to form a photoresist pattern on the cell region A. 207 is formed. An etching process is performed using the photoresist pattern 207 as a mask to remove the third polysilicon film 206 and the interlayer insulating film 203 in the peripheral circuit region B.

본 발명에서는 제 3 폴리실리콘막(206)을 제거하기 위해 종래에 주식각 반응 가스로 사용하던 Cl2-HBr 기반 가스에서 HBr을 제거한 가스를 사용하거나, CF4, C2F6, CHF3등 불소 기반 가스를 사용하여 과도 식각할 때 층간 절연막(203)를 완전히 제거한다.In the present invention, in order to remove the third polysilicon film 206, a gas obtained by removing HBr from a Cl 2 -HBr based gas, which is conventionally used as a stock angle reaction gas, or CF 4 , C 2 F 6 , CHF 3, or the like. The interlayer insulating film 203 is completely removed when over-etching using a fluorine-based gas.

도 2(c)는 감광막 패턴(207)를 제거한 후 제 2 평탄화막(208)을 형성한 단면도이다.2C is a cross-sectional view of the second planarization film 208 formed after removing the photoresist pattern 207.

도 2(d)를 참조하면, 주변 회로 영역(B)의 선택된 영역에 콘택 마스크를 이용한 건식 및 습식 식각 공정에 의해 비아 홀(209)을 형성한다. 전체 구조 상부에 장벽 금속층(210)을 형성한 후 알루미늄을 플로우시켜 금속 배선(211)을 형성한다.Referring to FIG. 2D, the via hole 209 is formed in a selected region of the peripheral circuit region B by dry and wet etching processes using a contact mask. After forming the barrier metal layer 210 on the entire structure, aluminum is flowed to form the metal wiring 211.

비아 홀이 형성되는 부분에 층간 절연막이 제거되므로 제 2 평탄화막과 제 1 평탄화막이 맞닿아 있다. 따라서, 비아 홀 형성 후 실시하는 클리닝(cleaning) 공정과 금속 배선을 형성하기 전에 실시하는 프리클리닝(pre-cleaning) 공정에서 사용되는 습식 화학제(wet chemical)에 의한 평탄화막간의 층간 절연막에 의한 계면턱이 제거된다. 그러므로 금속 배선을 증착할 때 금속 배선이 비아 홀의 아래 부분까지 증착되어 보이드가 제거된다.Since the interlayer insulating film is removed at the portion where the via hole is formed, the second planarization film and the first planarization film contact each other. Therefore, the interface by the interlayer insulating film between the planarization film by the wet chemical used in the cleaning process performed after via hole formation and the pre-cleaning process performed before forming metal wiring. The jaw is removed. Therefore, when depositing metal wiring, the metal wiring is deposited to the lower portion of the via hole to remove voids.

상술한 바와 같이 본 발명에 의하면 제 1 및 제 2 평탄화막 사이의 층간 절연막을 비아 홀을 형성하기 전에 제거하므로써 평탄화막간의 층간 절연막에 의한 계면턱이 제거되어 비아 홀 내의 금속 배선 매립 특성을 향상시켜 보이드를 방지할 수 있으므로 반도체 소자의 신뢰성을 향상시킬 수 있다.As described above, according to the present invention, by removing the interlayer insulating film between the first and second planarizing films before forming the via holes, the interface barrier caused by the interlayer insulating film between the planarizing films is removed, thereby improving the embedding of metal wiring in the via holes. Since voids can be prevented, the reliability of the semiconductor device can be improved.

Claims (2)

셀 영역에 반도체 소자를 제조하기 위한 여러 요소가 형성된 반도체 기판 상부와 주변 회로 영역의 반도체 기판 상부에 제 1 평탄화막 및 층간 절연막을 순차적으로 형성하는 단계와,Sequentially forming a first planarization film and an interlayer insulating film over the semiconductor substrate having various elements for manufacturing the semiconductor device in the cell region and the semiconductor substrate in the peripheral circuit region; 상기 셀 영역의 층간 절연막 및 제 1 평탄화막의 선택된 영역에 콘택 홀을 형성한 후 상기 콘택 홀이 매립되도록 전허저장 전극을 형성하는 단계와,Forming a contact hole in a selected region of the interlayer insulating film and the first planarization film of the cell region, and then forming a fully-stored storage electrode to fill the contact hole; 상기 셀 영역 및 주변 회로 영역을 포함한 전체 구조 상부에 플레이트 전극용 폴리실리콘막을 형성하는 단계와,Forming a polysilicon film for a plate electrode on the entire structure including the cell region and the peripheral circuit region; 상기 주변 회로 영역에 형성된 플레이트 전극용 폴리실리콘막 및 층간 절연막을 제거하여 주변 회로 영역의 제 1 평탄화막을 노출시키는 단계와,Exposing the first planarization film of the peripheral circuit region by removing the polysilicon film for the plate electrode and the interlayer insulating layer formed in the peripheral circuit region; 상기 셀 영역 및 주변 회로 영역 전체 구조 상부에 제 2 평탄화막을 형성하는 단계와,Forming a second planarization layer over the entire structure of the cell region and the peripheral circuit region; 상기 주변 회로 영역의 상기 제 2 및 제 1 평탄화막의 선택된 영역을 순차적으로 제거하여 비아 홀을 형성하는 단계와,Sequentially removing selected regions of the second and first planarization layers of the peripheral circuit region to form via holes; 상기 비아 홀을 포함한 전체 구조 상부에 장벽 금속층을 형성한 후 금속을 플로우시켜 금속 배선을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And forming a metal wiring by forming a barrier metal layer on the entire structure including the via hole and then flowing the metal to form a metal wiring. 제 1 항에 있어서, 상기 주변 회로 영역의 플레이트 전극용 폴리실리콘막은 CF4, C2F6및 CHF3등의 불소 기반 가스를 이용한 식각 공정으로 제거하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The method of claim 1, wherein the polysilicon film for plate electrodes in the peripheral circuit region is removed by an etching process using a fluorine-based gas such as CF 4 , C 2 F 6, and CHF 3 . .
KR1019970081132A 1997-12-31 1997-12-31 Method for forming metal interconnection of semiconductor device to improve metal interconnection filling characteristic in via hole and prevent void KR100440267B1 (en)

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JPH05347411A (en) * 1992-06-15 1993-12-27 Mitsubishi Electric Corp Semiconductor device and its manufacture
JPH06291197A (en) * 1993-04-02 1994-10-18 Mitsubishi Electric Corp Manufacturing for semiconductor device
KR970052389A (en) * 1995-12-27 1997-07-29 김광호 Contact hole formation method of semiconductor device
KR970072176A (en) * 1996-04-24 1997-11-07 김광호 Method for forming interlayer insulating film of semiconductor device
KR19980026827A (en) * 1996-10-11 1998-07-15 김광호 How to Form Contact Holes
KR100248799B1 (en) * 1996-12-30 2000-03-15 김영환 A method for forming metal contact in semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05347411A (en) * 1992-06-15 1993-12-27 Mitsubishi Electric Corp Semiconductor device and its manufacture
JPH06291197A (en) * 1993-04-02 1994-10-18 Mitsubishi Electric Corp Manufacturing for semiconductor device
KR970052389A (en) * 1995-12-27 1997-07-29 김광호 Contact hole formation method of semiconductor device
KR970072176A (en) * 1996-04-24 1997-11-07 김광호 Method for forming interlayer insulating film of semiconductor device
KR19980026827A (en) * 1996-10-11 1998-07-15 김광호 How to Form Contact Holes
KR100248799B1 (en) * 1996-12-30 2000-03-15 김영환 A method for forming metal contact in semiconductor device

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