KR960002563A - Contact hole formation method of semiconductor device - Google Patents

Contact hole formation method of semiconductor device Download PDF

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Publication number
KR960002563A
KR960002563A KR1019940014254A KR19940014254A KR960002563A KR 960002563 A KR960002563 A KR 960002563A KR 1019940014254 A KR1019940014254 A KR 1019940014254A KR 19940014254 A KR19940014254 A KR 19940014254A KR 960002563 A KR960002563 A KR 960002563A
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KR
South Korea
Prior art keywords
forming
word line
etch
film
contact hole
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Application number
KR1019940014254A
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Korean (ko)
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KR100305642B1 (en
Inventor
설여송
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR1019940014254A priority Critical patent/KR100305642B1/en
Publication of KR960002563A publication Critical patent/KR960002563A/en
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Publication of KR100305642B1 publication Critical patent/KR100305642B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체소자의 콘택홀 형성방법에 관한 것으로, 종래 기술에서 식각장벽으로 사용되는 물질이 식각공정시 발생시키는 문제점을 해결하기 위하여, 알루미늄합금에 뜨거운 증류수나 과산화수소수에 습식산화시킨 알루미나를 식각장벽 물질로 사용함으로써 평탄화층에 대하여 높은 식각선택비를 갖도록하여 워드라인이나 반도체기판을 손상시키지 않고 자기 정렬적으로 콘택홀을 형성하여 반도체소자의 신뢰성 및 생산성을 향상시키고 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for forming a contact hole in a semiconductor device, in order to solve the problem that the material used as an etch barrier in the prior art during the etching process, etching alumina wet-oxidized in hot distilled water or hydrogen peroxide in aluminum alloy. By using it as a barrier material, it has a high etching selectivity with respect to the planarization layer to form contact holes in a self-aligned manner without damaging word lines or semiconductor substrates, thereby improving reliability and productivity of semiconductor devices and enabling high integration of semiconductor devices. It is a technique to do.

Description

반도체소자의 콘택홀 형성방법Contact hole formation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도 내지 제3도는 본 발명의 실시예에 의한 반도체소자의 콘택홀 형성공정을 도시한 단면도.1 to 3 are cross-sectional views showing a contact hole forming process of a semiconductor device according to an embodiment of the present invention.

Claims (4)

반도체소자의 콘택홀 형성방법에 있어서, 반도체기판 상부에 게이트산화막, 워드라인용 다결정실리콘막 및 층간절연막을 산화막을 순차적으로 증착하고 그 상부에 워드라인 마스크를 형성하는 공정과, 상기 워드라인 마스크를 이용하여 상기 층간절연막을 산화막, 워드라인용 다결정실리콘막을 순차적으로 식각하고 층간절연막과 워드라인을 형성한 다음, 상기 워드라인 마스크를 제거하고 상기 워드라인의 측벽에 산화막 스페이서를 형성하는 공정과, 전체구조상부에 일정두께의 식각장벽층을 증착하고 그 상부에 평탄화층과 콘택마스크를 순차적으로 형성하는 공정과, 상기 콘택마스크를 이용하고 상기 식각장벽층을 식각장벽으로하여 상기 평탄화층을 식각한 다음, 상기 식각장벽층을 이방성식각하되 과식각하여 상기 게이트산화막을 식각하고 상기 콘택마스크를 제거함으로써 콘택홀을 형성하는 공정을 포함하는 반도체소자의 콘택홀 형성방법.A method of forming a contact hole in a semiconductor device, comprising: sequentially depositing an oxide film on a semiconductor substrate, a polysilicon film for a word line, and an interlayer insulating film, and forming a word line mask thereon; Using the interlayer insulating film to sequentially etch the oxide film and the polysilicon film for the word line by using the interlayer insulating film, forming the interlayer insulating film and the word line, and then removing the word line mask and forming oxide spacers on the sidewalls of the word line. Depositing an etch barrier layer having a predetermined thickness on the structure and sequentially forming a planarization layer and a contact mask thereon; and etching the planarization layer using the contact mask and using the etch barrier layer as an etch barrier. And anisotropically etch the etch barrier layer to etch the gate oxide layer. Forming a contact hole by removing the contact mask. 제1항에 있어서, 상기 식각장벽층은 알루미나막으로 형성하는 것을 특징으로 하는 반도체소자의 콘택홀 형성방법.The method of claim 1, wherein the etch barrier layer is formed of an alumina film. 제2항에 있어서, 상기 알루미나막은 알루미늄합금을 뜨거운 증류수나 과산화수소수로 습식산화시켜 형성하는 것을 특징으로 하는 반도체소자의 콘택홀 형성방법.3. The method of claim 2, wherein the alumina film is formed by wet oxidation of an aluminum alloy with hot distilled water or hydrogen peroxide water. 제3항에 있어서, 상기 알루미늄합금은 1000Å 미만의 두께로 형성하는 것을 특징으로 하는 반도체소자의 콘택홀 형성방법.The method of claim 3, wherein the aluminum alloy is formed to a thickness of less than 1000 GPa. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940014254A 1994-06-22 1994-06-22 Method for forming contact hole of semiconductor device KR100305642B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940014254A KR100305642B1 (en) 1994-06-22 1994-06-22 Method for forming contact hole of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940014254A KR100305642B1 (en) 1994-06-22 1994-06-22 Method for forming contact hole of semiconductor device

Publications (2)

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KR960002563A true KR960002563A (en) 1996-01-26
KR100305642B1 KR100305642B1 (en) 2001-11-30

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KR100752196B1 (en) 2006-09-12 2007-08-27 동부일렉트로닉스 주식회사 Mos transistor

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