KR930020583A - Metallization Contact Formation Method - Google Patents

Metallization Contact Formation Method Download PDF

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KR930020583A
KR930020583A KR1019920005406A KR920005406A KR930020583A KR 930020583 A KR930020583 A KR 930020583A KR 1019920005406 A KR1019920005406 A KR 1019920005406A KR 920005406 A KR920005406 A KR 920005406A KR 930020583 A KR930020583 A KR 930020583A
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forming
layer
insulating film
etch stop
contact
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KR1019920005406A
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KR100230349B1 (en
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장택용
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 셀프얼라인에 의한 고집적 DRAM의 콘택형성방법에 관한 것으로, 반도체장치의 금속배선 콘택형성방법에 있어서, 반도체기판위에 트랜지스터를 형성한 후 상기 트랜지스터상에는 다층의 절연막을 형성하고 그 측면에는 스페이서를 형성하는 공정과, 상기 다층의 절연막 및 스페이서상에 식각저지층을 형성하는 공정, 상기식각저지층상에 평탄화층을 형성 후 포토리소그래피공정에 의해 콘택부위에 해당하는 부분을 상기 평탄화층을 식각하는 공정, 상기 남겨진 평탄화층을 마스크로 하여 식각저지층을 식각한후 결과물을 건식산화방식에 의해 산화시켜 상기 식각저지층 측면에 산화막을 형성하는 공정, 및 셀프얼라인방식에 의해 콘택부위를 오픈시킨 후 도전층을 증착하고 금속배선패턴으로 패터닝하는 공정이 구비된 것을 특징으로 하는 본 발명에 의하면, 셀프얼라인콘택공정을 이용하면서도 금속배선층의 패터닝을 용이하게 행할수 있는 콘택형성방법이 제공되므로 디바이스 제조공정에 적용했을때 보다 신뢰성 높은 디바이스의 실현에 기여할 수 있게 된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a highly integrated DRAM contact by self-alignment. In the method for forming a metal wiring contact of a semiconductor device, after forming a transistor on a semiconductor substrate, a multilayer insulating film is formed on the transistor, and a spacer is formed on the side thereof Forming a planarization layer on the multilayer insulating film and the spacer, forming a planarization layer on the etch stop layer, and then etching the planarization layer on a portion corresponding to the contact portion by a photolithography process. Process, etching the etch stop layer using the remaining planarization layer as a mask, and oxidizing the resultant by dry oxidation method to form an oxide film on the etch stop layer side, and opening the contact portion by the self-align method. And depositing a conductive layer and patterning the metal layer with a metallization pattern. According to the invention, the contact forming method, which while utilizing the self-aligned contact process can easily be carried out for patterning of metal wiring layer is provided it is possible to contribute to realization of a highly reliable device than when applied in a device manufacturing process.

Description

금속배선 콘택형성 방법Metallization Contact Formation Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2a도 내지 제2d도는 본 발명의 일실시예에 의한 금속배선 콘택형성 방법을 도시한 것이다.2a to 2d illustrate a metallization contact forming method according to an embodiment of the present invention.

제3a도 및 제3b도는 본 발명의 다른 실시예에 의한 금속배선 콘택형성 방법을 도시한 것이다.3A and 3B illustrate a metallization contact forming method according to another embodiment of the present invention.

Claims (16)

반도체장치의 금속배선 콘택형성방법에 있어서, 반도체기판위에 트랜지스터를 형성한 후 상기 트랜지스터상에는 다층의 절연막을 형성하고 그 측면에는 스페이서를 형성하는 공정과, 상기 다층의 절연막 및 스페이서상에 식각저지층을 형성하는 공정, 상기 식각저지층상에 평탄화층을 형성한 후 포토리소그래피공정에 의해 콘택부위에 해당하는 부분의 상기 평탄화층을 식각하는 공정, 상기 남겨진 평탄화층을 마스크로 하여 상기 식각저지층을 식각한 후 결과물을 건식산화방식에 의해 산화시켜 상기 식각저지층 측면에 산화막을 형성한 공정, 및 셀프얼라인방식에 의해 콘택부위를 오픈시킨 후 도전층을 증착하고 금속배선패턴으로 패터닝하는 공정이 구비된 것을 특징으로 하는 금속배선 콘택형성방법.A method for forming a metallization contact in a semiconductor device, comprising: forming a transistor on a semiconductor substrate, and then forming a multilayer insulating film on the transistor and forming a spacer on the side thereof; and forming an etch stop layer on the multilayer insulating film and the spacer. Forming a planarization layer on the etch stop layer, and then etching the planarization layer of a portion corresponding to a contact portion by a photolithography process, and etching the etch stop layer using the remaining planarization layer as a mask. Thereafter, the resultant was oxidized by a dry oxidation method to form an oxide film on the side of the etch stop layer, and a step of opening a contact portion by a self-alignment method, depositing a conductive layer, and patterning a metal wiring pattern. Metal wiring contact forming method, characterized in that. 제1항에 있어서, 상기 식각저지층측면에 산화막을 형성하는 공정과 도전층을 증착하고 금속배선패턴으로 패터닝하는 공정 사이에 상기 산화막 및 평탄화층 측면에 스페이서를 여성하는 공정이 포함되는 것을 특징으로 하는 금속배선 콘택형성방법.The method of claim 1, further comprising a process of forming a spacer on the side of the oxide layer and the planarization layer between a process of forming an oxide layer on the etch stop layer side and a process of depositing a conductive layer and patterning the conductive layer. A metallization contact forming method. 제1항에 있어서, 상기 트랜지스터상에는 다층의 절연막을 형성하고 그 측면에는 스페이서를 형성하는 공정은 상기 트랜지스터를 둘러싸도록 트랜지스터의 게이트 전극위에는 보호절연막을 형성하고 상기 게이트전극 및 보호절연막의 측면에는 스페이서 산화막을 형성한 다음 결과물 전면에 중간절연막을 형성하는 공정임을 특징으로 하는 금속배선 콘택형성방법.The method of claim 1, wherein the forming of a multilayer insulating film on the transistor and forming a spacer on a side thereof forms a protective insulating film on a gate electrode of the transistor so as to surround the transistor, and a spacer oxide film on a side of the gate electrode and the protective insulating film. And forming an intermediate insulating film on the entire surface of the resultant. 제3항에 있어서, 상기 보호절연막 및 중간절연막은 산화막임을 특징으로 하는 금속배선 콘택형성방법.4. The method of claim 3, wherein the protective insulating film and the intermediate insulating film are oxide films. 제1항에 있어서, 상기 식각저지층은 산화막과의 식각선택비가 높은 물질로 형성함을 특징으로 하는 금속배번 콘택형성방법.The method of claim 1, wherein the etch stop layer is formed of a material having a high etching selectivity with respect to an oxide film. 제5항에 있어서, 상기 산화막과의 식각선택비가 높은 물질은 폴리실리콘 또는 단결정실리콘임을 특징으로 하는 금속배선 콘택형성방법.The method of claim 5, wherein the material having a high etching selectivity with respect to the oxide layer is polysilicon or single crystal silicon. 제1항에 있어서, 상기 평탄화층은 BPSG로 형성함을 특징으로 하는 금속배선 콘택형성방법.The method of claim 1, wherein the planarization layer is formed of BPSG. 제1항에 있어서, 상기 셀프엘라인방식에 의해 콘택부위를 오픈시키는 공정 RIE에 의해 행하는 것을 특징으로 하는 금속배선 콘택형성방법.2. The method for forming a metal interconnect contact according to claim 1, wherein said contact is formed by a step RIE of opening a contact portion by said self-elline method. 반도체장치의 금속배선 콘택형성방법에 있어서, 반도체기판위에 트랜지스터를 형성한 후 상기 트랜지스터를 둘러싸도록 트랜지스터의 게이트전극위에는 보호 절연막을 형성하고 상기 게이트전극 및 보호절연막의 측면에는 스페이서 산화막을 형성하는 공정과, 상기 결과물전면에 산화마스크층 및 중간절연막을 순차적으로 형성하는 공정, 상기 중간절연막상에 식각저지층을 형성하는 공정, 상기 식각저지층상에 평탄화층을 형성한 후 포토리소그래피공정에 의해 콘택부우에 해당하는 부분의 상기 평탄화층을 식각하는 공정, 상기 남겨진 평탄화층을 마스크로하여 상기 식각저지층을 식각한 후 결과물을 습식산화 분위기에서 산화시키는 공정, 및 셀프얼라인방식에 의해 콘택부위에 오픈시킨 후 도전층을 증착하고 금속배선패턴을 패터닝하는 공정이 구비된 것을 특징으로 하는 금속배선 콘택형성방법.A method of forming a metallization contact in a semiconductor device, comprising: forming a transistor on a semiconductor substrate and forming a protective insulating film on the gate electrode of the transistor to surround the transistor and forming a spacer oxide film on the side of the gate electrode and the protective insulating film; And sequentially forming an oxide mask layer and an intermediate insulating film on the entire surface of the resultant, forming an etch stop layer on the intermediate insulating film, and forming a planarization layer on the etch stop layer, followed by a photolithography process. Etching the planarization layer of the corresponding portion, etching the etch stop layer using the remaining planarization layer as a mask, and oxidizing the result in a wet oxidation atmosphere, and opening the contact portion by a self-aligning method. Depositing a conductive layer and patterning a metallization pattern The metal wire forming the contact characterized in that the bar. 제9항에 있어서, 상기 보호절연막 및 중간절연막은 산화막임을 특징으로 하는 금속배선 콘택형성방법.10. The method of claim 9, wherein the protective insulating film and the intermediate insulating film are oxide films. 제9항에 있어서, 산화 산화마스크층은 Si3N4임을 특징으로 하는 금속배선 콘택형성 방법.The method of claim 9, wherein the oxide mask layer is Si 3 N 4 . 제9항에 있어서, 상기 산화마스크층은 50Å∼100Å의 두께로 얇게 형성하는것을 특징으로 하는 금속배선 콘택형성방법.10. The method of claim 9, wherein the oxide mask layer is formed thin in a thickness of 50 kPa to 100 kPa. 제9상에 있어서, 상기 식각저지층은 산화막과의 식각선택비가 높은 물질로 형성함을 특징으로 하는 금속배선 콘택형성방법.The method of claim 9, wherein the etch stop layer is formed of a material having a high etching selectivity with respect to an oxide film. 제13항에 있어서, 상기 산화막과의 식각선택비가 높은 물질은 폴리실리콘 또는 단결정실리콘임을 특징으로하는 금속배선 콘택형성방법.The method of claim 13, wherein the material having a high etching selectivity with respect to the oxide layer is polysilicon or single crystal silicon. 제9항에 있어서, 상기 평탄화층은 BPSG로 형성함을 특징으로 하는 금속배선 콘택형성방법.10. The method of claim 9, wherein the planarization layer is formed of BPSG. 제9항에 있어서, 상기 셀프얼라인방식에 의해 콘택부위를 오픈시키는 공정은 RIE에 의해 행하는 것을 특징으로 하는 금속배선 콘택형성방법.10. The method of claim 9, wherein the step of opening the contact portion by the self-aligning method is performed by RIE. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920005406A 1992-03-31 1992-03-31 Forming method of metal contact KR100230349B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010059016A (en) * 1999-12-30 2001-07-06 박종섭 Manufacturing method of semiconductor device
KR20020037684A (en) * 2000-11-14 2002-05-22 가네꼬 히사시 Method of manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010059016A (en) * 1999-12-30 2001-07-06 박종섭 Manufacturing method of semiconductor device
KR20020037684A (en) * 2000-11-14 2002-05-22 가네꼬 히사시 Method of manufacturing semiconductor device

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