KR970013125A - Semiconductor device structure - Google Patents

Semiconductor device structure Download PDF

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Publication number
KR970013125A
KR970013125A KR1019950025893A KR19950025893A KR970013125A KR 970013125 A KR970013125 A KR 970013125A KR 1019950025893 A KR1019950025893 A KR 1019950025893A KR 19950025893 A KR19950025893 A KR 19950025893A KR 970013125 A KR970013125 A KR 970013125A
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KR
South Korea
Prior art keywords
gate insulating
etching
polysilicon
gate
forming
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Application number
KR1019950025893A
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Korean (ko)
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KR0152933B1 (en
Inventor
한병율
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문정환
엘지반도체 주식회사
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Priority to KR1019950025893A priority Critical patent/KR0152933B1/en
Publication of KR970013125A publication Critical patent/KR970013125A/en
Application granted granted Critical
Publication of KR0152933B1 publication Critical patent/KR0152933B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 반도체 소자 제조방법에 관한 것으로, 반도체 기판에 게이트 절연막을 형성하는 공정과 ; 상기 게이트 절연막을 선택식각하여 매몰접촉창을 형성하는 공정과 ; 상기 매몰접촉창과 게이트 절연막 위에 폴리실리콘을 형성하는 공정과 ; 상기 폴리실리콘을 선택식각하여 매몰접촉창과 연결되는 제1 게이트와, 게이트 절연막 위에 형성되는 제2 게이트를 형성하는 공정과 ; 산화공정에 의해 상기 제1 게이트와 제2 게이트 표면에 희생산화막을 형성하는 공정 및 ; 상기 희생산화막을 식각하는 공정을 포함하여 소자 제조를 완료하므로써, 게이트 절연막의 두께가 아무리 얇아지더라도 실리콘 기판의 손상없이 게이트 전극을 형성할 수 있을 뿐 아니라 게이트 폴리실리콘의 과식각(over etch)을 산화막 식각장치에서 진행하므로써 기판 실리콘의 손상을 최소화할 수 있게 되어 소자의 전기적 특성을 향상시킬 수 있게 된다.The present invention relates to a method for manufacturing a semiconductor device, comprising: forming a gate insulating film on a semiconductor substrate; Selectively etching the gate insulating film to form a buried contact window; Forming polysilicon on the buried contact window and the gate insulating film; Selectively etching the polysilicon to form a first gate connected to the buried contact window and a second gate formed over the gate insulating layer; Forming a sacrificial oxide film on the surfaces of the first and second gates by an oxidation process; By completing the fabrication of the device including etching the sacrificial oxide film, the gate electrode can be formed without damaging the silicon substrate even if the thickness of the gate insulating film becomes thin, and the overetch of the gate polysilicon is prevented. By proceeding in the oxide etching apparatus, damage to the substrate silicon can be minimized, thereby improving the electrical characteristics of the device.

Description

반도체 소자 구조Semiconductor device structure

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 반도체 소자 구조를 도시한 단면도2 is a cross-sectional view showing a semiconductor device structure according to the present invention.

Claims (5)

반도체 기판에 게이트 절연막을 형성하는 공정과 ; 상기 게이트 절연막을 선택식각하여 매몰접촉창을 형성하는 공정과 ; 상기 매몰접촉창과 게이트 절연막 위에 폴리실리콘을 형성하는 공정과 ; 상기 폴리실리콘을 선택식각하여 매몰 접촉창과 연결되는 제1 게이트와, 게이트 절연막 위에 형성되는 제2 게이트를 형성하는 공정과 ; 산화공정에 의해 상기 제1 게이트와 제2 게이트 표면에 희생산화막을 형성하는 공정 및 ; 상기 희생산화막을 식각하는 공정을 포함하여 형성되는 것을 특징으로 하는 반도체 소자 제조방법.Forming a gate insulating film on the semiconductor substrate; Selectively etching the gate insulating film to form a buried contact window; Forming polysilicon on the buried contact window and the gate insulating film; Selectively etching the polysilicon to form a first gate connected to the buried contact window and a second gate formed over the gate insulating layer; Forming a sacrificial oxide film on the surfaces of the first and second gates by an oxidation process; And etching the sacrificial oxide film. 제1항에 있어서, 상기 제1 및 제2 게이트는 상기 폴리실리콘 위에 산화막과, 상기 산화막 위에 질화막을 형성하고 이를 마스크로 상기 폴리실리콘을 식각하여 형성하는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein the first and second gates are formed by forming an oxide film on the polysilicon and a nitride film on the oxide film, and etching the polysilicon using a mask. 제1항에 있어서, 상기 폴리실리콘은 “20% 식각부족 - 10% 과식각” 범위 내에서 식각되는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein the polysilicon is etched within a range of “20% lack of etching—10% over etching”. 제1항에 있어서, 상기 희생산화막은 50-500Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein the sacrificial oxide film is formed to a thickness of 50-500 kV. 제1항에 있어서, 상기 희생산화막 식각 공정은 60-600Å 두께의 식각량 범위 내에서 실시되는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein the sacrificial oxide etching process is performed within an etching amount range of about 60-600 μs.
KR1019950025893A 1995-08-22 1995-08-22 Method of fabricating semiconductor device KR0152933B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950025893A KR0152933B1 (en) 1995-08-22 1995-08-22 Method of fabricating semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950025893A KR0152933B1 (en) 1995-08-22 1995-08-22 Method of fabricating semiconductor device

Publications (2)

Publication Number Publication Date
KR970013125A true KR970013125A (en) 1997-03-29
KR0152933B1 KR0152933B1 (en) 1998-12-01

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KR0152933B1 (en) 1998-12-01

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