KR890007397A - Method of manufacturing semiconductor device for suppressing hillock formation of metal film - Google Patents

Method of manufacturing semiconductor device for suppressing hillock formation of metal film Download PDF

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Publication number
KR890007397A
KR890007397A KR870012164A KR870012164A KR890007397A KR 890007397 A KR890007397 A KR 890007397A KR 870012164 A KR870012164 A KR 870012164A KR 870012164 A KR870012164 A KR 870012164A KR 890007397 A KR890007397 A KR 890007397A
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KR
South Korea
Prior art keywords
semiconductor device
film
metal film
manufacturing semiconductor
insulating film
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Application number
KR870012164A
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Korean (ko)
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KR900006774B1 (en
Inventor
김의송
박승갑
이철진
류지효
Original Assignee
강진구
삼성반도체통신 주식회사
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Priority to KR1019870012164A priority Critical patent/KR900006774B1/en
Publication of KR890007397A publication Critical patent/KR890007397A/en
Application granted granted Critical
Publication of KR900006774B1 publication Critical patent/KR900006774B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음No content

Description

금속막의 힐록 생성억제를 위한 반도체 장치의 제조방법Method of manufacturing semiconductor device for suppressing hillock formation of metal film

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도(A)-(E)도는 종래 2층 배선공정의 층간절연막을 형성하는 제조공정의 단면도,1A to 1E are cross-sectional views of a manufacturing process for forming an interlayer insulating film of a conventional two-layer wiring process,

제2(A)-(E)도는 본 발명에 따른 금속막의 힐록 생성억제를 의한 반도체장치의 제조공정의 단면도.2 (A)-(E) are sectional views of the manufacturing process of a semiconductor device by inhibiting hillock formation of a metal film according to the present invention.

Claims (4)

반도체 장치의 제조방법에 있어서, 반도체 기판상에 형성된(10)상에 소정의 금속배선막(11)을 형성하는 제1공정과, 상기 금속배선막(11)상게 금속배선막의 힐록 발생억제를 위하여 300℃ 이하의 온도에서 플라즈마를 이용하여 소정두께의 제1절연막(12)을 형성하는 제2공정과, 상기 절연막(12)상이 CVD방법으로 제2절연막(13)을 형성하는 제3공정을 구비하여 상기 공정의 연속으로 이루어짐을 특징으로 하는 금속막의 힐록 생성억제를 위한 반도체 장치의 제조방법.A method of manufacturing a semiconductor device, comprising: a first step of forming a predetermined metal wiring film 11 on a 10 formed on a semiconductor substrate, and suppressing hillock generation of the metal wiring film on the metal wiring film 11. A second step of forming the first insulating film 12 having a predetermined thickness using plasma at a temperature of 300 ° C. or lower; and a third step of forming the second insulating film 13 on the insulating film 12 by a CVD method. And a process for producing a semiconductor device for inhibiting hillock formation of a metal film, characterized in that the process is performed continuously. 제1항에 있어서, 제2공정의 플라즈마를 이용한 절연막은 이산화규소막 또는 질화규소막 임을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film using the plasma of the second step is a silicon dioxide film or a silicon nitride film. 제1항에 있어서, 제2공정은 상온에서 이루어짐을 특징으로 하는 반도체 장치의 자제방법.The method of claim 1, wherein the second process is performed at room temperature. 제1항에 있어서, 상기 제3공정의 제2절연막은 SiO2, PSG, BSG, BPSG, SiON 또는 Si3N4중의 하나로 형성됨을 특징으로 하는 반도체 장치의 제조방법.The method of claim 1, wherein the second insulating layer of the third process is formed of one of SiO 2 , PSG, BSG, BPSG, SiON, or Si 3 N 4 . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019870012164A 1987-10-31 1987-10-31 Method of semiconductor device KR900006774B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019870012164A KR900006774B1 (en) 1987-10-31 1987-10-31 Method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870012164A KR900006774B1 (en) 1987-10-31 1987-10-31 Method of semiconductor device

Publications (2)

Publication Number Publication Date
KR890007397A true KR890007397A (en) 1989-06-19
KR900006774B1 KR900006774B1 (en) 1990-09-21

Family

ID=19265635

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870012164A KR900006774B1 (en) 1987-10-31 1987-10-31 Method of semiconductor device

Country Status (1)

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KR (1) KR900006774B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07302893A (en) * 1994-04-28 1995-11-14 Xerox Corp Dual layer of insulation and capping for hillock prevention in metal layer of thin film structure

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Publication number Publication date
KR900006774B1 (en) 1990-09-21

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