KR960026354A - Method of planarizing interlayer insulating layer and forming diffusion barrier layer of semiconductor device - Google Patents

Method of planarizing interlayer insulating layer and forming diffusion barrier layer of semiconductor device Download PDF

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Publication number
KR960026354A
KR960026354A KR1019940035443A KR19940035443A KR960026354A KR 960026354 A KR960026354 A KR 960026354A KR 1019940035443 A KR1019940035443 A KR 1019940035443A KR 19940035443 A KR19940035443 A KR 19940035443A KR 960026354 A KR960026354 A KR 960026354A
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South Korea
Prior art keywords
diffusion barrier
insulating layer
barrier layer
layer
forming
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KR1019940035443A
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Korean (ko)
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박상균
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김주용
현대전자산업 주식회사
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Priority to KR1019940035443A priority Critical patent/KR960026354A/en
Publication of KR960026354A publication Critical patent/KR960026354A/en

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Abstract

본 발명은 반도체 소자 제조공정 중 절연층 형성방법에 관한 것으로, 특히 층간절연층의 평탄화 및 불순물의 확산을 방지하기 위한 반도체 소자의 층간절연층 평탄화 및 확산방지층 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an insulating layer during a semiconductor device manufacturing process, and more particularly, to a method for planarizing an interlayer insulating layer and forming a diffusion barrier layer of a semiconductor device to prevent planarization of an interlayer insulating layer and diffusion of impurities.

Description

반도체 소자의 층간절연층 평탄화 및 확산방지층 형성방법Method of planarizing interlayer insulating layer and forming diffusion barrier layer of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도는 본 발명에 따른 층간절연층 평탄화 후의 단면도, 제1B도는 본 발명에 따른 불순물 확산 방지 산화층 형성 후의 단면도.1A is a sectional view after planarization of an interlayer insulating layer according to the present invention, and FIG. 1B is a sectional view after formation of an impurity diffusion preventing oxide layer according to the present invention.

Claims (6)

반도체 소자의 층간절연층 평탄화 및 확산방지층 형성방법에 있어서, 층간 원자의 확산이동을 방지하는 제1확산방지층을 형성하는 제1단계; 불순물 함유 절연층을 형성하는 제2단계; 상기 불순물 함유 절연층을 열처리하여 평탄화하되, 상부의 불순물 함유량이 하부의 불순물 함유량보다 적도록 하는 제3단계; 층간 원자의 확산이동을 방지하는 제2확산방지층을 형성하는 제4단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 층간절연층 평탄화 및 확산방지층 형성방법.A method of planarizing an interlayer insulating layer and forming a diffusion barrier layer of a semiconductor device, comprising: a first step of forming a first diffusion barrier layer to prevent diffusion movement of interlayer atoms; A second step of forming an impurity-containing insulating layer; A third step of planarizing the impurity-containing insulating layer by heat treatment, wherein the upper impurity content is smaller than the lower impurity content; And a fourth step of forming a second diffusion barrier layer to prevent diffusion movement of the interlayer atoms. 제1항에 있어서, 상기 제1확산방지층은 단차가 심한 도전층 표면을 따라 형성되는 것을 특징으로 하는 반도체 소자의 층간절연층 평탄화 및 확산방지층 형성방법.The method of claim 1, wherein the first diffusion barrier layer is formed along the surface of the conductive layer having a high level of step difference. 제1항 또는 제2항에 있어서, 상기 제1확산방지층은 산화층인 것을 특징으로 하는 반도체 소자의 층간절연층 평탄화 및 확산방지층 형성방법.The method of claim 1 or 2, wherein the first diffusion barrier layer is an oxide layer. 제1항에 있어서, 상기 제2단계의 불순물 함유 절연층은 BPSG 층인 것을 특징으로 하는 반도체 소자의 층간절연층 평탄화 및 확산방지층 형성방법.The method of claim 1, wherein the impurity-containing insulating layer of the second step is a BPSG layer. 제1항 또는 제4항에 있어서, 상기 제3단계는 수 mtorr의 저압, 800내지 1000℃의 온동하에서 열처리함으로써 이루어지는 것을 특징으로 하는 반도체 소자의 층간절연층 평탄화 및 확산방지층 형성방법.The method of claim 1 or 4, wherein the third step is performed by heat treatment at a low pressure of several mtorr and a temperature of 800 to 1000 ° C. 제1항 내지 제4항에 있어서, 상기 제4단계는 수백 mtorr의 압력,550 내지 800℃의 온도, 실리콘을 포함한 가스 분위기하에서 열처리함으로써 이루어지는 것을 특징으로 하는 반도체 소자의 층간절연층 평탄화 및 확산방지층 형성방법.The planarization and diffusion barrier layer of an interlayer insulating layer of claim 1, wherein the fourth step is performed by heat treatment under a pressure of several hundred mtorr, a temperature of 550 to 800 ° C., and a gas atmosphere containing silicon. Formation method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940035443A 1994-12-20 1994-12-20 Method of planarizing interlayer insulating layer and forming diffusion barrier layer of semiconductor device KR960026354A (en)

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KR1019940035443A KR960026354A (en) 1994-12-20 1994-12-20 Method of planarizing interlayer insulating layer and forming diffusion barrier layer of semiconductor device

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KR1019940035443A KR960026354A (en) 1994-12-20 1994-12-20 Method of planarizing interlayer insulating layer and forming diffusion barrier layer of semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000076857A (en) * 1999-03-18 2000-12-26 니시무로 타이죠 Semiconductor device and method of making thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000076857A (en) * 1999-03-18 2000-12-26 니시무로 타이죠 Semiconductor device and method of making thereof

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